Samsung S5PC100, User Manual

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HDMI S5PC100 USER’S MANUAL (REV1.0)
9.10-2
1.2 BLOCK DESCRIPTION
TMDS
Transmitter
TMDS
Channel
Coder
HAES &
HDCP Cipher
Register Files & Timing Generator
Buffer
Packet
Generator
Video Receiver
clk
ch0[9:0]
ch1[9:0]
ch2[9:0]
XhdmiTXCP
XhdmiTXCN
XhdmiTX0P
XhdmiTX0N
tmds_power_down
cipher
streams
HDMI
Controller
SPDIF data
form SPDIF
Y / Cb / Cr
(8bits data
from MIXER)
ADDR
WDATA
RDATA
ctrl
SPDIF
Receiver
XhdmiTX1P
XhdmiTX1N
XhdmiTX2P
XhdmiTX2N
SCLK_HDMI
Figure 9.10-1 HDMI Transmitter Block Diagram
1.2.1 Register File
Register File contains all registers setting and its interface uses 8-bit bus.
All of the packet data except the audio sample packet are stored in the register file.
1.2.2 HDMI Controller
Timing Generator in HDMI Controller generates the HDMI timing information such as pixel and line numbers
according to the horizontal active signal, horizontal sync signal, vertical sync signal and etc.
Second role is to control the packet transmission. It checks the timing information and if available, it generates
control signals to audio FIFO and packet generator.
a) Packet transmission control consideration
Most of packets are transmitted once per video frame (or field), such as GCP, AVI, and audio infoframes.
Especially, ACR packet should be transmitted at a rate of 128xFs/N where Fs are sampling frequency of audio
sample and N is content of ACR packet.
To meet this requirement, the system controller has video pixel clock counter and it counts that clock. HDMI
transmits ACR packet each time after it reaches to the CTS value.
Audio sample packets are transmitted any time if audio sample is available and packet transmission is allowed to
meet the audio sample packet jitter requirement.