Samsung S5PC100, User Manual, Page: 1800 / 1863

S5PC100 USER’S MANUAL (REV1.0) CRYPTO ENGINE BLOCK
11.3-21
4.3.6 FIFO-Rx Write Buffer (FRx_WrBuf, W, Address = 0xF401_0040~0xF401_0080)
FRx_WrBuf Bit Description Reset
Value
FRx_WrBuf
[31:0]
Write access to
FRx_WrBuf
makes FIFO-Rx to write data to the
FIFO memory regardless of the address given. That
is, any address between 0x0040 and 0x0080 triggers the FIFO
memory write. This feature lets the programmer use burst write
to the FIFO-Rx.
4.3.7 FIFO-Tx Control Register (FTx_Ctrl, R/W, Address = 0xF411_0000)
FTx_Ctrl Bit Description Reset
Value
FTx_WrPrivError [31]
Sets to 1 if write access to FIFO-Tx has resulted in a privilege
error (e.g. Host or the command are not allowed to access FIFO-
Tx). Resets to 0 on FTx_Reset = 1. Read only.
1’b0
FTx_RdPrivError [30]
Sets to 1 if read access to FIFO-Tx has resulted in a privilege
error (e.g. Host or the command are not allowed to access FIFO-
Tx). Resets to 0 on FTx_Reset = 1. Read only.
1’b0
Reserved [29:28] Reserved
FTx_Full [27]
Sets to 1 if FIFO-Tx buffer (FTx_RdBuf) is full. Resets to 0 on
FTx_Reset = 1. Read only.
1’b0
FTx_Empty [26]
Sets to 1 if FIFO-Tx buffer (FTx_RdBuf) is empty. Resets to 1 on
FTx_Reset = 1. Read only.
1’b1
FTx_Done [25]
Sets to 1 if FIFO-Tx has finished transferring FTx_MLen words of
data from the source. Resets to 0 on FTx_Reset = 1 or on read
access to FTx_Ctrl register. Read only.
1’b0
FTx_Running [24]
Sets to 1 if FIFO-Tx is transferring data from the source or
waiting for source output buffer is ready. Sets to 1 when
FTx_Start bit resets to 0. Resets to 0 on FTx_Reset = 1.
Read only.
1’b0
FTx_Wd2Read [23:16]
Number of words that is read from FIFO memory (FTx_RdBuf).
Resets to 0 on FTx_Reset = 1. Read only.
8’h00
FTx_Wd2Write [15:8]
Number of words that is written to FIFO memory (FTx_RdBuf).
Resets to 0 on FTx_Reset = 1. Read only.
8’h20
FTx_Src_Module [7:6]
Source module selection.
( 00 : AES, 01:DES/TDES, 10: SHA-1/PRNG, 11: Not Used )
Resets to 0 on FTx_Reset = 1. Read/Write.
1’b0
FTx_Host_Rd_En [5]
Enables Host read from FTx_Ctrl[31:16] and FTx_MLenCnt.
Resets to 0 on FTx_Reset = 1. Read/Write.
1’b0
FTx_Host_Wr_En [4]
Enables Host read from FTx_RdBuf. Resets to 0 on FTx_Reset =
1. Read/Write.
1’b0
Reserved [3] Reserved
FTx_Reset [2]
Stops current FIFO-Tx transfer and resets FSM and all the
register. Resets to 0 after reset. Read/Write.
1’b0
FTx_ERROR_En [1]
Enables ERROR response via HRESP port if host tries to access
FIFO-Tx and access is not enabled by FTx_Ctrl[4] or [5]. Resets
1’b0