Samsung S5PC100, User Manual

Page: 1389 / 1863

TVOUT & VIDEO DAC S5PC100 USER’S MANUAL (REV1.0)
9.7-68
5.39
SDO WSS 525 DATA REGISTERS (SDO_ARMWSS525, R/W, ADDRESS = 0XF000_ 03C4)
SDO_ARMWSS525 Bit Description Reset Value
Reserved [31:20] Reserved, read as zero, do not modify 0
CRC of WSS 525 Data [19:14] Bit alignment of the CRC register is according to their
incoming order. The first incoming bit becomes LSB,
i.e. CRC [19:14] = {b19, b18, b17, b16, b15, b14},
where bn represents data bit with their incoming order
n.
The CRC used is X^6+ X + 1, all preset to 1.
0
Word 2 of WSS 525 Data [13:6] Bit alignment of the Word 2 register is according to
their incoming order. The first incoming bit becomes
LSB, i.e. Word 2 [13:6] = {b13, b12, b11, b10, b9, b8,
b7, b6}, where bn represents data bit with their
incoming order n.
The Word 2 data are used for copy control:
b7, b6 :
00 copying permitted
01 one copy permitted
10 reserved
11 no copying permitted
b9 b8 :
(reserved)
b10 :
not analog pre-recorded medium analog pre-recorded
medium
b13, b12, b11 :
(reserved)
0
Word 1 of WSS 525 Data [5:2] Bit alignment of the Word 1 register is according to
their incoming order. The first incoming bit becomes
LSB, i.e. Word 1 [5:2] = {b5, b4, b3, b2}, where bn
represents data bit with their incoming order n.
The Word 1 data are used to indicate the existence of
Word 2 data:
b5, b4, b3, b2 :
0000 copy control information
1111 default
0