Samsung S5PC100, User Manual, Page: 1688 / 1863

S5PC100 USER’S MANUAL (REV1.0) AC97 CONTROLLER
10.4-5
3.4 AC-LINK DIGITAL INTERFACE PROTOCOL
Each AC97 Codec incorporates a five-pin digital serial interface that links it to the S5PC100 AC97 Controller. AC-
link is a full-duplex, fixed-clock and PCM digital stream. It employs a Time Division Multiplexed (TDM) scheme to
handle control register accesses and multiple input and output audio streams. The AC-link architecture divides
each audio frame into 12 outgoing and 12 incoming data streams. Each stream has 20-bit sample resolution and
requires a DAC and an Analog-to-Digital Converter (ADC) with a minimum 16-bit resolution.
SYNC
SDATA_OUT
SDATA_IN
Slot #
TAG
CMD
ADDR
CMD
DATA
PCM PCM
RSRVD
TAG
STATUS
ADDR
STATUS
DATA
PCM
LEFT
PCM
RIGHT
0 1 2 3 4 5 6 7 8 9 10 11 12
RSRVD RSRVD RSRVD RSRVD RSRVD RSRVD RSRVD
RSRVD RSRVD RSRVD RSRVD RSRVD RSRVD RSRVD
PCM
MIC
LEFT RIGHT
Figure 10.4-4 Bi-directional AC-link Frame with Slot Assignments
Figure 10.4-4 shows the slot definitions supported by S5PC100 AC97 Controller. The S5PC100 AC97 Controller
provides synchronization for all data transaction on the AC-link.
A data transaction is made up of 256 bits of information broken into groups of 13 time slots and is called a frame.
Time slot 0 is called the Tag Phase and it is 16 bits long. The other 12 time slots are called the Data Phase. The
Tag Phase contains one bit that identifies a valid frame and 12 bits that identify the time slots in the Data Phase
that contain valid data. Each time slot in the Data Phase is 20 bits long. A frame begins when SYNC goes high.
The amount of time that SYNC is high corresponds to the Tag Phase. AC97 frames occur at fixed 48 kHz
intervals and are synchronous to the 12.288 MHz bit rate clock, BITCLK. The controller and the Codec use the
SYNC and BITCLK to determine when to send transmit data and when to sample received data. A transmitter
transitions the serial data stream on each rising edge of BITCLK and a receiver samples the serial data stream on
falling edges of BITCLK. The transmitter must tag the valid slots in its serial data stream. The valid slots are
tagged in slot 0. Serial data on the AC-link is ordered most significant bit (MSB) to least significant bit (LSB). The
Tag Phase's first bit is bit 15 and the first bit of each slot in Data Phase is bit 19. The last bit in any slot is bit 0.
3.4.1 AC-link Output Frame (SDATA_OUT)
Slot 0: Tag Phase
In slot 0, the first bit is a bit (SDATA_OUT, bit 15) which represents the validity of the entire frame. If bit 15 is a 1,
the current frame contains at least a valid time slot. The next 12-bit positions correspond each 12 time slot
contains valid data. Bits 0 and 1 of slot 0 are used as CODEC IO bits for I/O reads and writes to the CODEC
registers as described in the next section. In this way, data streams of differing sample rate are transmitted across
AC-link at its fixed 48 kHz audio frame rate.