Samsung S5PC100, User Manual

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Power Management S5PC100 USER’S MANUAL (REV1.0)
2.4-56
10.1.6 Configure Memory Power at STOP mode (STOP_MEM_CFG, R/W, Address = 0xE010_801C)
STOP_MEM_CFG Bit Description Reset Value
Reserved [31:11] Reserved 0x0
CCAN [10] CCAN Block Memory control (0 = Off, 1 = Retention) 1
IRDA [9] IRDA Block Memory control (0 = Off, 1 = Retention) 1
MODEMIF [8] MODEM IF Block Memory control (0 = Off, 1 = Retention) 1
USBOTG [7] USB_OTG Block Memory control (0 = Off, 1 = Retention) 1
SDMMC [6] SDMMC Memory control (0 = Off, 1 = Retention) 1
CSSYS [5] CSSYS Memory control (0 = Off, 1 = Retention) 1
SECSS [4] SECSS control (0 = Off, 1 = Retention) 1
IRAMC2 [3] IRAMC2 (32KB) memory control (0 = Off, 1 = Retention) 1
IRAMC1 [2] IRAMC1 (32KB) memory control (0 = Off, 1 = Retention) 1
IRAMC0 [1] IRAMC0 (32KB) memory control (0 = Off, 1 = Retention) 1
Reserved [0] DO NOT CHANGE 1
Each bit is available if TOP_MEMORY_ON field of STOP_CFG is 0. Therefore, if TOP_MEMORY_ON filed of
STOP_CFG is 1, then each bit has no effect.
Memory corresponding to each bit, means SRAM inside corresponding IP module of Top domain, and used by
that module.
10.2 SYSTEM STABILIZATION COUNTER
10.2.1 Oscillator Frequency Scale Counter (OSC_FREQ, R/W, Address = 0xE010_8100)
OSC_FREQ Bit Description Reset Value
Reserved [31:16] Reserved 0x0
OSC_FREQ_VALUE [3:0]
Oscillator frequency scale counter
(OSC_FREQ_VALUE x oscillator_period > 200ns)
0xF
OSC_FREQ register is applied to control timing in power up/down sequence in the following cases :
1) power off of sub power-domain (MFC, G3D, LCD, TV) in NORMAL mode.
2) top domain on option in DEEP-IDLE mode
3) top domain off option in DEEP-STOP mode