Samsung S5PC100, User Manual, Page: 419 / 1863

DRAM CONTROLLER S5PC100 USER’S MANUAL (REV1.0)
5.1-36
4.2.15 PHY Status Register 0 (PhyStatus0, R, Address=0xE600_0040)
PHYSTATUS0 Bit Description R/W
Reset
Value
Reserved [31:14] Should be zero 0x0
ctrl_lock_value [13:4]
Locked Delay
Locked delay line encoding value
ctrl_lock_value[9:2]: number of delay cells for coarse lock
ctrl_lock_value[1:0]: control value for fine lock
R 0x0
Reserved [3] Should be zero 0x0
ctrl_locked [2]
DLL Lock
0 = Unlocks DLL,
1 = Locks DLL
R 0x0
ctrl_flock [1]
Fine Lock Information
It is indicated that DLL is locked with fine resolution, “phase
offset error” is less than 80ps. R 0xX
ctrl_clock [0]
Coarse Lock Information
It is indicated that DLL changes step delays of the “delay line”
and “phase offset error” is less than 160ps. R 0xX
4.2.16 PHY Status Register 1 (PhyStatus1, R, Address=0xE600_0044)
PHYSTATUS1 Bit Description R/W
Reset
Value
Reserved [31:0] R 0x0