Samsung S5PC100, User Manual, Page: 649 / 1863

S5PC100 USER’S MANUAL (REV1.0) UART
8.1-25
2) Baud Rate Error Tolerance
UART Frame error should be less than 1.87%(3/160)
tUPCLK = (U 1) x 16 x 1Frame / (PCLK ,UART_CLK or SCLK_UART) tUPCLK: Real UART Clock
tEXTUARTCLK = 1Frame / baud-rate tEXTUARTCLK: Ideal UART Clock
UART error = (tUPCLK
−
tEXTUARTCLK) / tEXTUARTCLK x 100%
1Frame = start bit + data bit + parity bit + stop bit.
3) UART Clock and PCLK Relation
There is a constraint on the ratio of clock frequencies for PCLK to UARTCLK.
The frequency of UARTCLK must be no more than 5.5/3 times faster than the frequency of PCLK :
F
UARTCLK
<= 5.5/3 X F
PCLK
F
UARTCLK
= baudrate x 16
This allows sufficient time to write the received data to the receive FIFO
6.12 UART INTERRUPT PENDING REGISTER
•
UINTP0, R/W, Address = 0xEC00_0030
•
UINTP1, R/W, Address = 0xEC00_0430
•
UINTP2, R/W, Address = 0xEC00_0830
•
UINTP3, R/W, Address = 0xEC00_0C30
Interrupt pending register contains the information of the interrupts that are generated.
UINTPn Bit Description Reset Value
MODEM [3] Generates Modem interrupt. 0
TXD [2] Generates Transmit interrupt. 0
ERROR [1] Generates Error interrupt. 0
RXD [0] Generates Receive interrupt. 0
If one of above 4 bits is logical high('1') , each UART channel generate interrupt.
This register must be cleared in the interrupt service routine after clearing interrupt pending register in Interrupt
Controller(INTC). Clear specific bits of UINTP register by writing 1's to the bits that you want to clear.