Samsung S5PC100, User Manual, Page: 911 / 1863

USB2.0 HS OTG S5PC100 USER’S MANUAL (REV1.0)
8.10 -68
8.2.48 Device Control OUT Endpoint 0 Control Register (DOEPCTL0, R/W, Address =0xED20_0B00)
This section describes the Control OUT Endpoint 0 Control register. Nonzero control endpoints use registers for
endpoints 1-15.
DOEPCTL0 Bit Description R/W Reset
Value
EPEna [31] Endpoint Enable
Indicates that the application has allocated the memory to
start receiving data from the USB. The core clears this bit
before setting any of the following interrupts on this endpoint.
•
SETUP Phase Done
•
Endpoint Disabled
•
Transfer Complete
Note: In DMA mode, this bit must be set for the core to
transfer SETUP data packets into memory.
R_WS_
SC
1'b0
EPDis [30] Endpoint Disable
The application cannot disable control OUT endpoint 0. R 1'b0
Reserved [29:28] - 2'b0
SetNAK [27] Set NAK
A write to this bit sets the NAK bit for the endpoint.
Using this bit, the application controls the transmission of NAK
handshakes on an endpoint. The core sets this bit on a
Transfer Completed interrupt, or after a SETUP is received on
the endpoint. W 1'b0
CNAK [26] Clear NAK
A write to this bit clears the NAK bit for the endpoint. W 1'b0
Reserved [25:22] - 4'h0
Stall [21] STALL Handshake
The application sets this bit, and the core clears it, if a SETUP
token is received for this endpoint. If a NAK bit or Global OUT
NAK is set along with this bit, the STALL bit takes priority.
Irrespective of this bit’s setting, the core always responds to
SETUP data packets with an ACK handshake. R_WS_
SC
1'b0
Snp [20] Snoop Mode
This bit configures the endpoint to Snoop mode. In Snoop
mode, the core does not check the correctness of OUT
packets before transferring them to application memory. R/W 1'b0
EPType [19:18] Endpoint Type
Hardcoded to 2'b00 for control.
R 2'h0