Samsung S5PC100, User Manual

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USB2.0 HS OTG S5PC100 USER’S MANUAL (REV1.0)
8.10 -46
8.2.24 Host All Channels Interrupt Register (HAINT, R, Address = 0xED20_0414)
If a significant event occurs on a channel, the Host All Channels Interrupt register interrupts the application using
the Host Channels Interrupt bit of the Core Interrupt register. There is one interrupt bit per channel, up to a
maximum of 16 bits. Bits in this register are set and cleared if the application sets and clears bits in the
corresponding Host Channel-n Interrupt register.
HAINT Bit Description R/W Reset
Value
Reserved [31:16] - 16'h0
HAINT [15:0] Channel Interrupts
One bit per channel: Bit 0 for Channel 0, bit 15 for Channel 15 R 16'h0
8.2.25 Host All Channels Interrupt Mask Register (HAINTMSK, R/W, Address = 0xED20_0418)
The Host All Channel Interrupt Mask register works with the Host All Channel Interrupt register to interrupt the
application if an event occurs on a channel. There is one interrupt mask bit per channel, up to a maximum of 16
bits.
•
Msk interrupt: 1'b0
•
Unmask interrupt: 1'b0
HAINTMSK Bit Description R/W Reset
Value
Reserved [31:16] - 16'h0
HAINTMsk [15:0] Channel Interrupt Mask
One bit per channel: Bit 0 for Channel 0, bit 15 for Channel 15
R/W 16'h0