Samsung S5PC100, User Manual

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S5PC100 USER’S MANUAL (REV1.0) Power Management
2.4-13
To exit STOP mode:
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Various types of wakeup sources are used. Wakeup sources referred in Section 5 WAKEUP SOURCES.
Then PMU performs the following sequence to exit STOP mode.
1. Enables the OSC pads if disabled and waits for the OSC stabilization (around 1ms).
2. Enables the PLLs and waits for locking (300us).
3. Unmasks clock input to clock-on blocks.
4. Make DRAMs exit self-refresh mode.
OSC stabilization time is determined by the external clock frequency and the counter value specified in the
OSC_STABLE register. PLL locking time is set in PLL_LOCK registers.
3.6 DEEP-STOP MODE
In DEEP-STOP mode, Cortex-A8 Core is power-off rather than clock-gated, and the remaining parts of the chip
are power-off except TOP, RTC, and ALIVE module. The TOP domain is either power-on or power-off by the
setting of TOP_LOGIC_ON field of STOP_CFG register before it enters into DEEP-STOP mode. Cortex-A8 L2
cache can be powered ON for memory retention, or power-off to save power.
•
TOP_LOGIC_ON = 1'b1, Top domain is power on.
•
TOP_LOGIC_ON = 1'b0, Top domain is power-off.
If TOP_LOGIC_ON_DIDLE = 1'b0, some IP modules in Top domain loses their states in F/F, and the other IP
modules keeps their states in F/F after wakeup. IP modules in Top domain shown in Table 2.4-4 have retention
F/Fs, and those modules will keep their states in F/F after wakeup. Therefore, IP modules that do not keep their
states in F/F in DEEP-STOP mode (Top domain off), the states of F/F should be saved into external memory, and
be restored after wakeup.
To enter DEEP-STOP mode:
1. Set ARM_LOGIC_ON field of STOP_CFG register to 1'b0.
2. Set CFG_STANDBYWFI field of PWR_CFG to 2'b10.
3. Set PMU_INT_DISABLE bit of OTHERS register to 1’b1 to prevent interrupts from occurring while entering
DEEP-STOP mode.
4. Execute Wait For Interrupt instruction (WFI).
PMU performs the following sequence to enter DEEP-STOP mode.
1. Completes all active bus transactions.
2. Completes all active memory controller transactions.
3. Initiates external DRAM enter self-refresh mode (to preserve DRAM contents).
4. Masks input clock using internal signal in PMU.
5. Disables all PLLs.
6. Selectively disables OSCs except 32.768kHz.
To exit DEEP-STOP mode:
•
Various types of wakeup sources are used. Wakeup sources referred in Section 5 WAKEUP SOURCES.