Samsung S5PC100, User Manual, Page: 473 / 1863

NAND FLASH CONTROLLER S5PC100 USER’S MANUAL (REV1.0)
5.4-8
5.4 1-BIT ECC PROGRAMMING GUIDE
1. To use SLC ECC in software mode, reset the ECCType to ‘0’ (enable SLC ECC)‘. ECC module generates
ECC parity code for all read/ write data if MainECCLock (NFCON[7]) and SpareECCLock (NFCON[6]) are
unlocked(‘0’). You must reset ECC value by writing the InitMECC (NFCONT[5]) and InitSECC (NFCON[4]) bit
as ‘1’ and clear the MainECCLock (NFCONT[7]) bit to ‘0’(Unlock) before read or write data.
MainECCLock (NFCONT[7]) and SpareECCLock(NFCONT[6]) bit controls the generation of ECC parity code.
2. The ECC module generates ECC parity code on register NFMECC0/1 whenever data is read or written.
3. After you complete read or write one page (does not include spare area data), Set the MainECCLock bit to ‘1’
(Lock). ECC Parity code is locked and the value of the ECC status register does not change.
4. To generate spare area ECC parity code, Clear SpareECCLock (NFCONT[6]) bit to ‘0’ (Unlock).
5. The spare area ECC module generates ECC parity code on register NFSECC whenever data is read or
written.
6. After you complete read or write spare area, set the SpareECCLock bit to ‘1’ (Lock). ECC Parity code is
locked and the value of the ECC status register does not change.
7. From now on, you can use these values to record to the spare area or check the bit error.
8. For example, to check the bit error of main data area on page read operation, you must move the ECC parity
codes (is stored to spare area) to NFMECCD0 and NFMECCD1 after ECC codes for main data area is
generated. From this point, the NFECCERR0 and NFECCERR1 have the valid error status values.
NOTE
NFSECCD is for ECC in the spare area (Usually, the user writes the ECC value generated from main
data area to Spare area and value is same as NFMECC0/1) and it is generated from the main data area.