Samsung S5PC100, User Manual

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I2S CONTROLLER(2CH) S5PC100 USER’S MANUAL (REV1.0)
10.3-2
3 BLOCK DIAGRAM
Figure 10.3-1 I2S-Bus Block Diagram
4 FUNCTIONAL DESCRIPTIONS
I2S interface consists of register bank, FIFOs, shift registers, clock control, DMA finite state machine, and channel
control block as shown in Figure 10.3-1. Note that each FIFO has 32-bit width and 16 depth structure, which
contains left/ right channel data. Therefore, FIFO access and data transfer are handled with left/ right pair unit.
Figure 10.3-1
shows the functional block diagram of I2S interface.
4.1 MASTER/SLAVE MODE
Set IMS bit of I2SMOD register to select master or slave mode. In master mode, I2SSCLK and I2SLRCLK are
generated internally and supplied to external device. Therefore a root clock is needed for generating I2SSCLK
and I2SLRCLK by dividing. The I2S pre-scaler (clock divider) generates a root clock with divided frequency from
internal system clock. In external master mode, the root clock is fed directly from external I2S. The I2SSCLK and
I2SLRCLK are supplied from the pin (GPIOs) in slave mode.
Master/Slave mode is different with TX/RX. Master/Slave mode presents the direction of I2SLRCLK and
I2SSCLK. The direction of I2SCDCLK (This is only auxiliary) is not a concern. If I2S bus interface transmits clock
signals to I2S codec, I2S bus is master mode. But if I2S bus interface receives clock signal from I2S codec, I2S
bus is slave mode. TX/RX mode indicates the direction of data flow. If I2S bus interface transmits data to I2S
codec, this is TX mode. Conversely, I2S bus interface receives data from I2S codec that is RX mode. Let us
distinguish Master/ Slave mode from TX/RX mode.