Samsung S5PC100, User Manual, Page: 1464 / 1863

MIXER S5PC100 USER’S MANUAL (REV1.0)
9.9-12
2.6 MIXER_LAYER_CFG REGISTER (MIXER_LAYER_CFG, R/W, ADDRESS = 0XF020_ 0010)
The priority value for video and each graphic layer can be set. The priority field is used to determine the priority of
a graphic layer. The graphic layer of higher value has the higher priority. This field is also used as on/off switch. If
one field is set to zero, the corresponding graphic layer is not displayed. If some layers have the same value, the
priority is like this: graphic layer 1 > graphic layer 0 > video. The priority is only determined by difference of
priority’s value. For example, case1 and case 2 have the same effect.
Case1 : GRP1 priority is 2 , GRP0 priority 3 , Video Priority 1
Case2 : GRP1 priority is 14 , GRP0 priority 15 , Video Priority 13
MIXER_LAYER_CFG Bit Description Reset Value
Reserved [31:12] Reserved, read as zero, do not modify 0
Graphic layer 1 priority [11:8]
15 ~ 1 = the priority value
0 = Hides the graphic layer 1
0
Graphic layer 0 priority [7:4]
15 ~ 1 = the priority value
0 = Hides the graphic layer 0
0
Video layer priority
[3:0]
15 ~ 1 = the priority value
0 = Hides the video layer 0
0
NOTE: All the changes of this register are valid on a vertical sync signal of next frame when SYNC_ENABLE flag is set to
one. And the “Hide” means that layer data is ready but is not displayed.
2.7 MIXER_VIDEO_CFG REGISTER (MIXER_VIDEO_CFG, R/W, ADDRESS = 0XF020_ 0014)
MIXER_VIDEO_CFG Bit Description Reset Value
Reserved [31:17] Reserved, read as zero, do not modify 0
REG_BLEND_EN [16] If set to 1, it enables the blending of all the video layer
onto the lower layer using the blending factor,
REG_ALPHA_VID.
0
Reserved [15:8] Reserved, read as zero, do not modify 0
REG_ALPHA_VID [7:0] Video layer blending factor. This factor is used over all
the pixels in the video layer to blend with lower layer.
α
* video_layer_pixel (1 –
α
) *
lower_layer_pixel_value
If REG_ALPHA_VID is 0,
α
is 0.
If REG_ALPHA_VID is not 0,
α
= (REG_ALP 1)/256.
0
NOTE: All changes to this register are valid on a vertical sync signal of next frame.