Samsung S5PC100, User Manual

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S5PC100 USER’S MANUAL (REV1.0) UART
8.1-1
8.1
UNIVERSAL ASYNCHRONOUS RECEIVER
AND TRANSMITTER
1 OVERVIEW
The S5PC100 Universal Asynchronous Receiver and Transmitter (UART) provide four independent asynchronous
serial Input/ Output (I/O) (SIO) ports. Both the ports operate in interrupt-based or DMA-based mode. In other
words, UART generates an interrupt or a DMA request to transfer data between CPU and the UART. The UART
ch0, ch2 supports bit rates up to 115.2K bps and UART ch1 and ch3 supports bit rates up to 3M bps. If an
external device provides the UART with UCLK, then the UART operates at a higher speed. Each UART channel
contains two 64-byte FIFOs to receive and transmit.
UART includes programmable baud rates, infrared (IR) transmit/receive, one or two stop bit insertion, 5-bit, 6-bit,
7-bit, or 8-bit data width and parity checking.
Each UART contains a baud-rate generator, a transmitter, a receiver and a control unit, as shown in Figure 8.1-1.
The baud-rate generator is clocked by PCLK or UCLK. The transmitter and the receiver contain 64-byte FIFOs
and data shifters. The data to be transmitted is written to FIFO, and copied to the transmit shifter. The data is then
shifted out by the transmit data pin (TxDn). The received data is shifted from the receive data pin (RxDn), and
copied to FIFO from the shifter.
2 FEATURES
•
RxD0, TxD0, RxD1, TxD1, RxD2, TxD2, RxD3 and TxD3 with DMA-based or interrupt-based operation
•
UART Ch 0, 1, 2 and 3 with IrDA 1.0 & 64-byte FIFO
•
UART Ch 0, 1 and 2 with nRTS0, nCTS0, nRTS1, nCTS1, nCTS2 and nRTS2 for Auto Flow Control
•
Supports high-speed operation in UART Ch1 and 3
•
Supports handshake transmit/receive