Samsung S5PC100, User Manual, Page: 458 / 1863

S5PC100 USER’S MANUAL (REV1.0) ONENAND CONTROLLER
5.3-21
4.19 TRANSFER SIZE REGISTER (TRANS_SPARE, R/W, ADDRESS = 0XE710_0140)
TRANS_SPARE Bit Description Reset Value
Reserved [31:1] Reserved
Tsfr_Spare [0]
If this bit is set, the data in the spare area of memory is
transferred to the asynchronous FIFO of the controller along
with the main data. Size of the spare area is part dependent
depending on the size of the sectors.
0 = Transfers main area or both main and spare areas,
1 = Increase transfer size. Always transfers main area and
spare area.
The main data area for the page is transferred first and then
the spare area.
If burst length is 3’b100, this bit dose not set.
0
4.20 PAGE COUNT REGISTER (PAGE_CNT, R, ADDRESS = 0XE710_0170)
PAGE_CNT Bit Description Reset Value
Reserved [31:8] Reserved
Page_Count [7:0]
Holds the page count of the multi-page command currently
being executed. Read-Only.
0
4.21 ERROR PAGE ADDRESS REGISTER (ERR_PAGE_ADDR, R, ADDRESS = 0XE710_0180)
ERR_PAGE_ADDR Bit Description Reset Value
Reserved [31:16] Reserved
CS [15:14] Chip Select. 0
DFS_DBS [13] DFS/DBS Bit. 0
FPA_Fail [5:0]
After a program, load or erase error interrupt, this register will
hold the page address of the failing operation. Read-Only.
0
4.22 BURST READ LATENCY REGISTER (BURST_RD_LAT, R, ADDRESS = 0XE710_0190)
BURST_RD_LAT Bit Description Reset Value
Reserved [31:3] Reserved
Burst_Rd_ Latency [2:0]
Sets the burst read latency in cycles. The default value is 0x7
This value is copied from the memory_configuration register
[14:12]. Read-Only.
0x7