Samsung S5PC100, User Manual

Page: 228 / 1863

S5PC100 USER’S MANUAL (REV1.0) Power Management
2.4-29
XusbXTI(XusbXTO)
This I/O is dedicated pin, and therefore its value is kept during power down mode.
4) Analog I/O, dedicated : Xadc*, Xdac*, Xhdmi*, Xmipi*, Xusb*, Xuh*, Xef*, Xrtc*, Xcg*
This I/O is dedicated pin, and therefore its value is kept during power down mode as long as analog
power is supplied.
2. RET_EN0 is automatically released by hardware logic. The release is done 1 XTI (main clock) cycle after
wakeup reset to top domain is released.
RET_EN0
(internal)
nSCALL_BLK_TOP
(internal)
By setting
IO_RET_RELEASE[31] in
OTHERS register
CPGI
(internal)
RET_EN1
(internal)
RET_LPA
(internal)
RET_SDMMC
(internal)
By setting
SDMMC_IO_RET_RELEASE[22]
in OTHERS register
GPIO setting is lost due to
power gating
GPIO setting should be done
before setting
IO_RET_RELEASE[31] and
SDMMC_IO_RET_RELEASE[22]
Automatically de-asserted by h/w
IO_RET
(internal)
Automatically cleared by h/w
SDMMC_IO_RET
(internal)
Automatically cleared by h/w
XnRSTOUT
2 XTI cycles
GPIO control register
GP*CON GP*CON GP*PDNCON
Figure 2.4-4 Retention I/O Control Timing Diagram