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S5PC100 USER’S MANUAL (REV1.0)
USB2.0 HS OTG
8.10-73
8.2.50 Device Endpoint-n Interrupt Register (DIEPINTn/DOEPINTn, R/W, Address = 0xED2n*20h,
0xED2n*20h)
Endpoint_number : 0
≤
n
≤
15
This register indicates the status of an endpoint with respect to USB- and AHB-related events. The application
must read this register if the OUT Endpoints Interrupt bit or IN Endpoints Interrupt bit of the Core Interrupt register
is set. Before the application reads this register, it must first read the Device All Endpoints Interrupt (DAINT)
register to get the exact endpoint number for the Device Endpoint-n Interrupt register. The application must clear
the appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers.
DIEPINTn/
DOEPINTn
Bit
Description
R/W
Reset Value
EPEna [31:7]
Reserved
25'h1
INEPNakEff
[6]
IN Endpoint NAK Effective
Applies to periodic IN endpoints only.
Indicates that the IN endpoint NAK bit set by the application
has taken effect in the core. This bit is cleared if the application
clears the IN endpoint NAK by writing to DIEPCTLn.CNAK.
This interrupt indicates that the core has sampled the NAK bit
set. This interrupt does not necessarily mean that a NAK
handshake is sent on the USB. A STALL bit takes priority over
a NAK bit.
R 1'b0
Back2Back
SETup
Back-to-Back SETUP Packets Received
Applies to Control OUT endpoints only.
This bit indicates that core has received more than three back-
to-back SETUP packets for this particular endpoint.
R/W
INTknEPMis
[5]
IN Token Received with EP Mismatch
Applies to periodic IN endpoints only.
Indicates that the data in the top of the non-periodic TxFIFO
belongs to an endpoint other than the one for which the IN
token was received. This interrupt is asserted on the endpoint
for which the IN token was received.
For OUT endpoints, this bit is reserved.
R_SS
_WC
1'b0
INTknTXFEmp
[4]
IN Token Received When TxFIFO is Empty
Applies to non-periodic IN endpoints only.
Indicates that an IN token was received when the associated
TxFIFO was empty. This interrupt is asserted on the endpoint
for which the IN token was received.
R_SS
_WC
1'b0
OUTTknEPdis
OUT Token Received When Endpoint Disabled
Applies only to control OUT endpoints.
Indicates that an OUT token is received if the endpoint is not
enabled. This interrupt is asserted on the endpoint for which
the OUT token was received.
TimeOUT
[3]
Timeout Condition
Applies to non-isochronous IN endpoints only.
Indicates that the core has detected a timeout condition on the
USB for the last IN token on this endpoint.
R_SS
_WC
1'b0
Summary of Contents for S5PC100
Page 21: ...MEMORY MAP S5PC100 USER S MANUAL REV1 0 1 2 2 ...
Page 34: ...S5PC100 USER S MANUAL REV1 0 BALL MAP SIZE POP 1 1 9 1 4 MCP CONNECTION ...
Page 49: ...IROM CODE S5PC100 USER S MANUAL REV1 0 2 6 4 12 Mhz 300 0 Mhz 100 0 Mhz 79 5 Mhz 20 6 Mhz ...
Page 174: ...CLOCK CONTROLLER S5PC100 USER S MANUAL REV1 0 2 3 24 Rs 0ohm Rf 1Mohm CL 10 35pF ...
Page 322: ...CORESIGHT S5PC100 USER S MANUAL REV1 0 3 2 4 Figure 3 2 2 S5PC100 Coresight Structure ...
Page 330: ...CORESIGHT S5PC100 USER S MANUAL REV1 0 3 2 12 Figure 3 2 7 ETB Block Diagram ...
Page 345: ...S5PC100 USER S MANUAL REV1 0 ASYNC BRIDGE 3 4 3 Figure 3 4 2 Asynchronous Bridge Components ...
Page 359: ...S5PC100 USER S MANUAL REV1 0 VECTORED INTERRUPT CONTROLLER 4 1 3 Figure 4 1 2 VIC Daisy Chain ...
Page 651: ...S5PC100 USER S MANUAL REV1 0 UART 8 1 27 Figure 8 1 10 UINTSP UINTP and UINTM block diagram ...
Page 652: ...UART S5PC100 USER S MANUAL REV1 0 8 1 28 NOTES ...
Page 743: ...S5PC100 USER S MANUAL REV1 0 MIPI HSI INTERFACE CONTROLLER 8 6 13 ...
Page 756: ...MIPI HSI INTERFACE CONTROLLER S5PC100 USER S MANUAL REV1 0 8 6 26 NOTES ...
Page 800: ...MIPI CSIS S5PC100 USER S MANUAL REV1 0 8 8 10 NOTES ...
Page 816: ...USB HOST CONTROLLER S5PC100 USER S MANUAL REV1 0 8 9 16 ...
Page 935: ...S5PC100 USER S MANUAL REV1 0 MODEM INTERFACE 8 11 13 NOTES ...
Page 1111: ...S5PC100 USER S MANUAL REV1 0 IMAGE ROTATOR 9 2 3 3 4 180 DEGREE ROTATION ...
Page 1112: ...IMAGE ROTATOR S5PC100 USER S MANUAL REV1 0 9 2 4 3 5 90 AND 270 DEGREE ROTATION ...
Page 1118: ...S5PC100 USER S MANUAL REV1 0 CAMERA INTERFACE 9 3 3 Figure 9 3 2 Camera Interface Overview ...
Page 1181: ...JPEG S5PC100 USER S MANUAL REV1 0 9 4 6 Figure 9 4 5 YCbCr4 2 2 Color Format ...
Page 1199: ...JPEG S5PC100 USER S MANUAL REV1 0 9 4 24 NOTES ...
Page 1245: ...3D ACCELERATOR S5PC100 USER S MANUAL REV1 0 9 6 18 ...
Page 1353: ...TVOUT VIDEO DAC S5PC100 USER S MANUAL REV1 0 9 7 32 ...
Page 1452: ...S5PC100 USER S MANUAL REV1 0 VIDEO PROCESSOR 9 8 43 NOTES ...
Page 1482: ...MIXER S5PC100 USER S MANUAL REV1 0 9 9 30 NOTES ...
Page 1664: ...S5PC100 USER S MANUAL REV1 0 I2S CONTROLLER 5 1CH 10 2 31 NOTES ...
Page 1701: ...AC97 CONTROLLER S5PC100 USER S MANUAL REV1 0 10 4 18 NOTES ...
Page 1731: ...SPDIF TRANSMITTER S5PC100 USER S MANUAL REV1 0 10 6 16 NOTES ...
Page 1744: ...S5PC100 USER S MANUAL REV1 0 ADC AND TOUCH SCREEN INTERFACE 10 7 13 NOTES ...
Page 1750: ...KEYPAD INTERFACE S5PC100 USER S MANUAL REV1 0 10 8 6 Figure 10 8 7 Keypad I F Block Diagram ...
Page 1755: ...S5PC100 USER S MANUAL REV1 0 KEYPAD INTERFACE 10 8 11 NOTES ...
Page 1779: ...SECURE DOMAIN MANAGER S5PC100 USER S MANUAL REV1 0 11 2 22 NOTES ...