Samsung S5PC100, User Manual

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S5PC100 USER’S MANUAL (REV1.0) I2S CONTROLLER(2CH)
10.3-7
5 PROGRAMMING GUIDE
The I2S bus interface is accessed either by the processor using programmed I/O instructions or by the DMA
controller.
5.1 INITIALIZATION
1. Before you use I2S bus interface, you must configure GPIOs to I2S mode and check signal's direction. The
I2SLRCLK, I2SSCLK and I2SCDCLK are inout-type. The each of I2SSDI and I2SSDO is input and output.
2. Select clock source. The S5PC100 has three clock sources namely PCLK, EPLL and external codec. For
more details refer to Figure 10.3-2.
5.2 PLAY MODE (TX MODE) WITH DMA
1. TXFIFO is flushed before operation. If you do not distinguish Master/ Slave mode from TX/RX mode, you
must study Master/ Slave mode and TX/RX mode. For more information refer to section Master/Slave.
2. To configure I2SMOD register and I2SPSR (I2S pre-scaler register) properly.
3. To operate system in stability, the internal TXFIFO should be almost full before transmission. First of all, DMA
starts because of that reason.
4. Basically, I2S bus does not support the interrupt. Therefore, check state by polling through accessing SFR.
5. If TXFIFO is full, now then you make I2SACTIVE be asserted.
5.3 RECORDING MODE (RX MODE) WITH DMA
1. RXFIFO is flushed before operation. If you do not distinguish between Master/ Slave mode and TX/RX mode,
you must study Master/Slave mode and TX/RX mode. For more information refer to “Section Master/Slave
chapter.
2. To configure I2SMOD register and I2SPSR (I2S pre-scaler register) properly.
3. To operate system in stability, the internal RXFIFO should have minimum one data before DMA operation.
Because of that reason, you make I2SACTIVE be asserted.
4. Check RXFIFO state by polling through accessing SFR.
5. If RXFIFO is not empty, start RXDMACTIVE.
6 EXAMPLE CODE
TX CHANNEL
The I2S TX channel provides a single stereo compliant output. The transmit channel operates in master or
slave mode. Data is transferred between the processor and the I2S controller via an APB access or a DMA
access.
The processor must write words in multiples of two (i.e. for left and right audio sample).The words are serially
shifted out timed with respect to the audio bitclk, BCLK and word select clock, LRCLK.
TX Channel has 16X32-bit wide FIFO where the processor or DMA writes upto 16 left/right data samples after
enabling the channel for transmission.
An Example sequence is as follows.
Ensure the PCLK and CODCLKI are coming correctly to the I2S controller and FLUSH the TX FIFO using the
TFLUSH bit in the Please ensure that I2S Controller is configured in one of the following modes.
•
TX only mode