
S5PC100 USER’S MANUAL (REV1.0)
NAND FLASH CONTROLLER
5.4-11
5.7 8-BIT ECC PROGRAMMING GUIDE (ENCODING)
1. To use 8-bit ECC in software mode, set the MsgLength to 0 (512-byte message length) and set the ECCType
to “01” (enable 8-bit ECC). The ECC module generates ECC parity code for 512-byte write data. Therefore
reset ECC value by writing the InitMECC (NFCONT[5]) bit as ‘1’ after clearing the MainECCLock
(NFCONT[7]) bit to ‘0’(Unlock) .
MainECCLock (NFCONT[7]) bit controls the generation of ECC parity code.
Note:
In 8-bit ECC, MainECCLock should be cleared before InitMECC.
2. The 8-bit ECC module generates ECC parity code internally whenever data is written.
3. After 512-byte data (not include spare area data) is written, the parity codes are automatically updated to
NF8MECC0, NFMECC1, NF8MECC2, and NF8MECC3 registers. Use 512-byte NAND flash memory to
program these values to spare area. However, if more than 512-byte page NAND flash memory is used, s/w
can’t program immediately. In this case, you must copy these parity codes to other memory like DRAM. After
writing all main data, write the copied ECC values to spare area.
The parity codes have self-correctable information include parity code itself.
4. To generate spare area ECC parity code, set the MsgLength to 1(24-byte message length), and set the
ECCType to “01”(enable 8bit ECC). The ECC module generates ECC parity code for 24-byte write data.
Therefore reset ECC value by writing the InitMECC (NFCONT[5]) bit as ‘1’ after clearing the MainECCLock
(NFCONT[7]) bit to ‘0’(Unlock.
MainECCLock (NFCONT[7]) bit controls the generation of ECC parity code.
Note:
In 8-bit ECC, MainECCLock should be cleared before InitMECC.
5. The 8-bit ECC module generates ECC parity code internally whenever data is written.
6. If you finish writing 24-byte meta or extra data, the parity codes are automatically updated to NF8MECC0,
NFMECC1, NF8MECC2, and NF8MECC3 registers. Program these parity codes to spare area.The parity
codes have self-correctable information including parity code itself.
Summary of Contents for S5PC100
Page 21: ...MEMORY MAP S5PC100 USER S MANUAL REV1 0 1 2 2 ...
Page 34: ...S5PC100 USER S MANUAL REV1 0 BALL MAP SIZE POP 1 1 9 1 4 MCP CONNECTION ...
Page 49: ...IROM CODE S5PC100 USER S MANUAL REV1 0 2 6 4 12 Mhz 300 0 Mhz 100 0 Mhz 79 5 Mhz 20 6 Mhz ...
Page 174: ...CLOCK CONTROLLER S5PC100 USER S MANUAL REV1 0 2 3 24 Rs 0ohm Rf 1Mohm CL 10 35pF ...
Page 322: ...CORESIGHT S5PC100 USER S MANUAL REV1 0 3 2 4 Figure 3 2 2 S5PC100 Coresight Structure ...
Page 330: ...CORESIGHT S5PC100 USER S MANUAL REV1 0 3 2 12 Figure 3 2 7 ETB Block Diagram ...
Page 345: ...S5PC100 USER S MANUAL REV1 0 ASYNC BRIDGE 3 4 3 Figure 3 4 2 Asynchronous Bridge Components ...
Page 359: ...S5PC100 USER S MANUAL REV1 0 VECTORED INTERRUPT CONTROLLER 4 1 3 Figure 4 1 2 VIC Daisy Chain ...
Page 651: ...S5PC100 USER S MANUAL REV1 0 UART 8 1 27 Figure 8 1 10 UINTSP UINTP and UINTM block diagram ...
Page 652: ...UART S5PC100 USER S MANUAL REV1 0 8 1 28 NOTES ...
Page 743: ...S5PC100 USER S MANUAL REV1 0 MIPI HSI INTERFACE CONTROLLER 8 6 13 ...
Page 756: ...MIPI HSI INTERFACE CONTROLLER S5PC100 USER S MANUAL REV1 0 8 6 26 NOTES ...
Page 800: ...MIPI CSIS S5PC100 USER S MANUAL REV1 0 8 8 10 NOTES ...
Page 816: ...USB HOST CONTROLLER S5PC100 USER S MANUAL REV1 0 8 9 16 ...
Page 935: ...S5PC100 USER S MANUAL REV1 0 MODEM INTERFACE 8 11 13 NOTES ...
Page 1111: ...S5PC100 USER S MANUAL REV1 0 IMAGE ROTATOR 9 2 3 3 4 180 DEGREE ROTATION ...
Page 1112: ...IMAGE ROTATOR S5PC100 USER S MANUAL REV1 0 9 2 4 3 5 90 AND 270 DEGREE ROTATION ...
Page 1118: ...S5PC100 USER S MANUAL REV1 0 CAMERA INTERFACE 9 3 3 Figure 9 3 2 Camera Interface Overview ...
Page 1181: ...JPEG S5PC100 USER S MANUAL REV1 0 9 4 6 Figure 9 4 5 YCbCr4 2 2 Color Format ...
Page 1199: ...JPEG S5PC100 USER S MANUAL REV1 0 9 4 24 NOTES ...
Page 1245: ...3D ACCELERATOR S5PC100 USER S MANUAL REV1 0 9 6 18 ...
Page 1353: ...TVOUT VIDEO DAC S5PC100 USER S MANUAL REV1 0 9 7 32 ...
Page 1452: ...S5PC100 USER S MANUAL REV1 0 VIDEO PROCESSOR 9 8 43 NOTES ...
Page 1482: ...MIXER S5PC100 USER S MANUAL REV1 0 9 9 30 NOTES ...
Page 1664: ...S5PC100 USER S MANUAL REV1 0 I2S CONTROLLER 5 1CH 10 2 31 NOTES ...
Page 1701: ...AC97 CONTROLLER S5PC100 USER S MANUAL REV1 0 10 4 18 NOTES ...
Page 1731: ...SPDIF TRANSMITTER S5PC100 USER S MANUAL REV1 0 10 6 16 NOTES ...
Page 1744: ...S5PC100 USER S MANUAL REV1 0 ADC AND TOUCH SCREEN INTERFACE 10 7 13 NOTES ...
Page 1750: ...KEYPAD INTERFACE S5PC100 USER S MANUAL REV1 0 10 8 6 Figure 10 8 7 Keypad I F Block Diagram ...
Page 1755: ...S5PC100 USER S MANUAL REV1 0 KEYPAD INTERFACE 10 8 11 NOTES ...
Page 1779: ...SECURE DOMAIN MANAGER S5PC100 USER S MANUAL REV1 0 11 2 22 NOTES ...