Samsung S5PC100, User Manual

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S5PC100 USER’S MANUAL (REV1.0) SD/MMC CONTROLLER
8.12-75
9.30 CONTROL REGISTER 2
Control register 2
•
CONTROL2_0, R/W, Address = 0xED80_0080
•
CONTROL2_1, R/W, Address = 0xED90_0080
•
CONTROL2_2, R/W, Address = 0xEDA0_0080
This register contains the SD Command Argument.
CONTROL2 Bit Description Reset Value
ENSTAASYN
CCLR
[31] Write Status Clear Async Mode Enable
This bit makes async-clear enable about Normal and Error interrupt
status bit. During the initialization procedure command operation, this
bit should be enabled.
'0' = Disable '1' = Enable 0
ENCMDCNF
MSK
[30] Command Conflict Mask Enable
This bit can mask enable the Command Conflict Status (bit [1:0] of the
"ERROR INTERRUPT STATUS REGISTER")
0 = Mask Disable, 1 = Mask Enable
Note: If the ENHIGHSPD field in the Host Control Register is set (High
Speed data transfer), this field should be enabled to prevent from
command conflict status alarm.
0
Reserved [29] Reserved (must be 1’b0) 0
SELCARDO
UT
[28] Card Removed Condition Selection
0= Card Removed condition is "Not Card Insert" State (When the
transition from "Card Inserted" state to "Debouncing" state in Figure
8.12-17)
1 = Card Removed state is "Card Out" State (If the transition from
"Debouncing" state to "No Card" state in Figure 8.12-17)
0
FLTCLKSEL [27:24] Filter Clock (iFLTCLK) Selection
Filter Clock period = 2^(Flt 5) x iSDCLK period
0000 = 25 x iSDCLK, 0001 = 26 x iSDCLK … 1111 = 220 x iSDCLK
0
LVLDAT [23:16] DAT line level
Bit[23]=DAT[7], BIT[22]=DAT[6], BIT[21]=DAT[5], BIT[20]=DAT[4],
Bit[19]=DAT[3], BIT[18]=DAT[2], BIT[17]=DAT[1], BIT[16]=DAT[0]
(Read Only)
Line state
ENFBCLKTX [15] Feedback Clock Enable for Tx Data/Command Clock
'0' = Disable, '1' = Enable 0
ENFBCLKRX [14] Feedback Clock Enable for Rx Data/Command Clock
'0' = Disable, '1' = Enable 0
Reserved [13] Reserved (must be 1’b0) 0
SDOPSIGPC [12] SD Output Signal Power Control Support
If set this field is enables output CMD and DAT referencing SD Bus
Power bit in the "PWRCON register".
'0' = CMD and DAT outputs are not controlled by SD Bus Power bit
'1' = CMD and DAT outputs are controlled(masked) by SD Bus Power
bit
0