Samsung S5PC100, User Manual

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S5PC100 USER’S MANUAL (REV1.0) MIPI DSIM
8.7-29
DSIM_INTMSK Bit Description R/W Reset Value
(For more information refer to standard d-phy
specification)
Reserved [5] Reserved - -
MskControl2 [4] Control Error lane2
(For more information refer to standard d-phy
specification)
R/W 1
MskControl1 [3] Control Error lane1
(For more information refer to standard d-phy
specification)
R/W 1
MskControl0 [2] Control Error lane0
(For more information refer to standard d-phy
specification)
R/W 1
MskContentLP0 [1] LP0 Contention Error
(For more information refer to standard d-phy
specification)
R/W 1
MskContentLP1 [0] LP1 Contention Error
(For more information refer to standard d-phy
specification)
R/W 1
3.2.14 Packet Header FIFO register (DSIM_PKTHDR, W, Address = 0xECB0_0x34)
This register is the FIFO for packet header to send DSI packets.
DSIM_PKTHDR Bit Description R/W Reset Value
Reserved [31:24] Reserved - -
PacketHeader [23:0] This register is to write the packet header of Tx packet.
[7:0] = DI
[15:8] = Dat0 (Word Count lower byte for long packet)
[23:16] = Dat1 (Word Count upper byte for long
packet)
W 0
3.2.15 Payload FIFO register (DSIM_PAYLOAD, W, Address = 0xECB0_0x38)
This register is the FIFO for payload to send DSI packets.
DSIM_PAYLOAD Bit Description R/W Reset Value
Payload [31:0] This register is to write the Payload of Tx packet. W 0