Samsung S5PC100, User Manual

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S5PC100 USER’S MANUAL (REV1.0) CLOCK CONTROLLER
2.3-19
7.8 USB PHY AND 48MHZ CLOCK
S5PC100 has an USB PHY for USB OTG. It has an internal PLL to generate clock for USB-OTG operation.
Internal PLL must get definite clock-frequency (OSC 12, 24, and 48MHz / crystal 12MHz) through XusbXTI and
XusbXTO.
An OTG PHY generates 48 MHz clock. SDMMC, SPI need 48MHz clock and IrDA, USB HOST1.1 needs exact
48MHz clock. S5PC100 supplies this clock from XusbXTI (when using 48MHz crystal or OSC) or output of OTG
PHY or PLL.
Figure 2.3-11 USB PHY and 48MHz clock
7.9 D2_SS CLOCK DOMAIN
For more information on Audio CMU in Figure 2.3-12, refer to “Section 7.2”.
Audio
CMU
Sync
Bridge
HCLKD2
AHB
I2S
V5.0
SRAM
PCLK_IIS0
from SYSCON
I2SCLKD2
D2_SS
HCLK_FIMC0
from SYSCON
HCLK_FIMC1
from SYSCON
HCLKD0
FOUT_EPLL
IISCDCLK0 PAD
(clock from external I2S master)
SCLK_AUDIO0 from
SYSCON
Figure 2.3-12 D2_SS Clock Domain