Samsung S5PC100, User Manual, Page: 453 / 1863

ONENAND CONTROLLER S5PC100 USER’S MANUAL (REV1.0)
5.3-16
4.4 INTERRUPT ERROR STATUS REGISTER (INT_ERR_STAT, R/W, ADDRESS = 0XE710_0030)
INT_ERR_STAT Bit Description Reset Value
Reserved [31:14] Reserved
Cache_Op_Err [13]
An error occurred during a cache read or write setup or
operation.
If the host does not send an appropriate sequence of MAP01
following a MAP10 pipeline command, then the controller
issues a Cache_Op_Err.
As an example, a MAP10 command is issued for an 8-way
interleaved read of 10 pages starting from address A. If the
next command is not a MAP01 command to the same
address, or if the order of MAP01 commands is inaccurate,
then the Controller issues this interrupt, send a core reset to
the device, clears all the pipeline registers and service the
request as a normal read. A similar example would hold for a
pipelined write command.
0
Rst_Cmp [12]
The controller has completed its reset and auto- initialization
process. (After auto-initialize complete and available
OneNAND Device, this bit is “1”)
0
Reserved [11] Reserved 0
INT_act [10] The memory device’s INT pin is actively transitioning. 0
Unsup_Cmd [9]
An unsupported command was received. This interrupt is set if
an invalid command is received, or if a command sequence is
broken.
0
Locked_Blk [8] The address to program or erase is in a protected block. 0
Blk_RW_Cmp [7]
This interrupt indicates one of the following have occurred:
- A copyback operation is complete.
- A pipeline transaction is complete.
- A lock, lock-tight or unlock command to a range of address
is complete.
- An Erase Verify operation is complete.
0
Ers_Cmp [6]
The erase operation is complete. This interrupt is
automatically reset at the beginning of an erase operation.
Default is 0.
0
Pgm_Cmp [5]
The program operation is complete. This interrupt is
automatically reset at the beginning of a program operation.
Default is 0.
0
Load_Cmp [4] The load operation is complete. Default is 0. 0
Ers_Fail [3] The erase operation was unsuccessful. 0
Pgm_Fail [2] The program operation was unsuccessful. 0
Int_T0 [1] Interrupt time-out. 0
Ld_Fail_Ecc_Err [0]
Dual purpose interrupt bit. The load operation was
unsuccessful or there was an ECC error.
0