Samsung S5PC100, User Manual

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S5PC100 USER’S MANUAL (REV1.0) PAD CONTRL
2.2-71
NWU_INT19[5] [14:8] Filtering width for NWU_INT19[5] 000
FLTEN19[4] [7] Digital Filter Enable for NWU_INT19[4] 0
NWU_INT19[4] [6:0] Filtering width for NWU_INT19[4] 000
5.5.60 Non wake-up Interrupt 20 Filter Configuration Register 0 (NWU_INT20_FLTCON0, R/W, Address =
0xE030_08A0) The Digital Filter Enable field means that 0 = disables, 1 = enables.
Field Bit Description Reset Value
FLTEN20[3] [31] Digital Filter Enable for NWU_INT20[3] 0
NWU_INT20[3] [30:24] Filtering width for NWU_INT20[3] 000
FLTEN20[2] [23] Digital Filter Enable for NWU_INT20[2] 0
NWU_INT20[2] [22:16] Filtering width for NWU_INT20[2] 000
FLTEN20[1] [15] Digital Filter Enable for NWU_INT20[1] 0
NWU_INT20[1] [14:8] Filtering width for NWU_INT20[1] 000
FLTEN20[0] [7] Digital Filter Enable for NWU_INT20[0] 0
NWU_INT20[0] [6:0] Filtering width for NWU_INT20[0] 000
5.5.61 Non wake-up Interrupt 0 Mask Register (NWU_INT0_MASK, R/W, Address = 0xE030_0900)
Field Bit Description Reset Value
Reserved [31:8] Reserved 0
NWU_INT0_MASK[n] [n] 0 = Enabled, 1 = Masked (n=0,..,7) 1
5.5.62 Non wake-up Interrupt 1 Mask Register (NWU_INT1_MASK, R/W, Address = 0xE030_0904)
Field Bit Description Reset Value
Reserved [31:5] Reserved 0
NWU_INT1_MASK[n] [n] 0 = Enabled, 1 = Masked (n=0,..,4) 1
5.5.63 Non wake-up Interrupt 2 Mask Register (NWU_INT2_MASK, R/W, Address = 0xE030_0908)
Field Bit Description Reset Value
Reserved [31:8] Reserved 0
NWU_INT2_MASK[n] [n] 0 = Enabled, 1 = Masked (n=0,..,7) 1
5.5.64 Non wake-up Interrupt 3 Mask Register (NWU_INT3_MASK, R/W, Address = 0xE030_090C)
Field Bit Description Reset Value
Reserved [31:5] Reserved 0
NWU_INT3_MASK[n] [n] 0 = Enabled, 1 = Masked (n=0,..,4) 1