Samsung S5PC100, User Manual

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USB HOST CONTROLLER S5PC100 USER’S MANUAL (REV1.0)
8.9-14
5.2.3 USB HcCommandStatus Register (UHCCONSTAT, Address = 0xED40_0008)
The USB host controller uses the USB HOST Command Status (UHCCONSTAT, shown in Table 8.9-4) register
to receive commands that the host controller driver issues, as well as reflecting the current status of the host
controller. To the host controller driver, it appears to be a write-to-set register. Bits written as 1 become set in the
register, while bits written as 0 remain unchanged in the register. In this way, the host controller driver issues
multiple distinct commands to the host controller without concern for corrupting previously issued commands. The
host controller driver has read access to all of these bits.
Table 8.9-3 UHCCONSTAT Bit Definitions
UHCCONSTAT Bit Description R/W Reset Value
Reserved [31:18] Reserved -
SOC [17:16] SchedulingOverrunCount
The SchedulingOverrunCount field indicates the number
of frames with which the host controller has detected the
scheduling overrun error, which occurs if the periodic list
does not complete before EOF. If a scheduling-overrun
error is detected, the host controller increments the
counter and sets the SchedulingOverrun field in the
UHC Interrupt Status register, UHCINTS. These bits are
incremented on each scheduling overrun error. It is
initialized to 0b00 and wraps around at 0b11. This is
incremented if a scheduling overrun is detected even if
SchedulingOverrun in HcInterruptStatus (Refer to
Section 20.8.4) has already been set. This bit field and
the scheduling overrun interrupt are used by the host
controller driver to monitor any persistent scheduling
problems. These bits are incremented on each
scheduling overrun error. R
Reserved [15:4] Reserved -
OCR [3] OwnershipChangeRequest
The host controller driver sets this bit to request a
change in UHC control If this bit is set, UHC sets
OwnershipChange in HcInterruptStatus (Refer to
Section 20.8.4). If read, this bit always returns 0. This
implementation of the OHCI host does not support SMI.
Therefore, software must never write 0b1 to this bit.
0 = No HCD request for a change in control of the UHC
is pending.
1 = HCD is requesting a change change in UHC control R/W