Samsung S5PC100, User Manual

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SD/MMC CONTROLLER S5PC100 USER’S MANUAL (REV1.0)
8.12-44
9.12 BLOCK GAP CONTROL REGISTER
Block Gap Control Register
•
BLKGAP0, R/W, 0xED80_002A
•
BLKGAP1, R/W, 0xED90_002A
•
BLKGAP2, R/W, 0xEDA0_002A
This register contains the SD Command Argument.
BLKGAP Bit Description Reset Value
Reserved [7:4] Reserved 0
ENINTB
GAP
[3] Interrupt At Block Gap
This bit is valid only in 4-bit mode of the SDIO card and selects a sample
point in the interrupt cycle. If set to 1, it enables interrupt detection at the
block gap for a multiple block transfer. If set to 0, it disables interrupt
detection during a multiple block transfer. If the SD card cannot signal an
interrupt during a multiple block transfer, this bit must be set to 0. If the Host
Driver detects an SD card insertion, it sets this bit according to the CCCR of
the SDIO card. (RW)
'1' = Enables, '0' = Disables
Note: Interrupt at Block Gap operation is not supported in S3C6410
controller, it should be fixed to 0.
0
ENRWAIT [2] Read Wait Control
The read wait function is optional for SDIO cards. If the card supports read
wait, set this bit to enable use of the read wait protocol to stop read data
using the DAT[2] line. Otherwise the Host Controller has to stop the SD
Clock to hold read data, which restricts commands generation. If the Host
Driver detects an SD card insertion, it sets this bit according to the CCCR of
the SDIO card. If the card does not support read wait, this bit will never be
set to 1 otherwise DAT line conflict might occur. If this bit is set to 0,
Suspend/ Resume cannot be supported. (RW)
'1' = Enables Read Wait Control, '0' = Disables Read Wait Control
0
CONTREQ [1] Continue Request
This bit is used to restart a transaction which was stopped using the Stop At
Block Gap Request. To cancel stop at the block gap, set Stop At Block Gap
Request to 0 and set this bit 1 to restart the transfer.
The Host Controller automatically clears this bit in either of the following
cases:
(1) If a read transaction, the DAT Line Active changes from 0 to 1 as a read
transaction restarts.
(2) If a write transaction, the Write Transfer Active changes from 0 to 1 as
the write transaction restarts.
Therefore it is not necessary for Host Driver to set this bit to 0. If Stop At
Block Gap Request is set to 1, any write to this bit is ignored. (RWAC)
'1' = Restart, '0' = Not affect
0
STOPB
GAP
[0] Stop At Block Gap Request
This bit is used to stop executing a transaction at the next block gap for both
0