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MIPI DSIM

S5PC100 USER’S MANUAL (REV1.0)

8.7-22

DSIM_CONFIG

Bit

Description

R/W

Reset Value

MainPixFormat

[14:12]

Pixel stream format for main display

000 = 3bpp for Command mode only

001 = 8bpp for Command mode only

010 = 12bpp for Command mode only

011 = 16bpp for Command mode only

100 = 16-bit RGB (565) for Video mode only

101 = 18-bit RGB (666 : packed pixel stream) for Video
mode only

110 = 18-bit RGB (666 : loosely packed pixel stream)
for Common

111 = 24-bit RGB (888) for common

R/W 0

Reserved [11]

Reserved

SubPixFormat [10:8]

Pixel

stream format for sub display

000 = 3bpp for Command mode only

001 = 8bpp for Command mode only

010 = 12bpp for Command mode only

011 = 16bpp for Command mode only

100 = 16-bit RGB (565) for Video mode only

101 = 18-bit RGB (666 : packed pixel stream) for Video
mode only

110 = 18-bit RGB (666 : loosely packed pixel stream)
for common

111 = 24-bit RGB (888) for Common

R/W 0

Reserved [7]

Reserved

NumOfDatLane

[6:5]

Set the using data lane number

00 = Data lane 0 ( 1 data lane)

01 = Data lane 0 ~ 1 (2 data lanes)

10 = Data lane 0 ~ 2 (3 data lanes)

11 = Reserved

R/W 0

Reserved [4]

Reserved

LaneEn[3:0] [3:0]

Lane

enabler.

If Lane_EN is disabled, lane ignores input and drive
initial value through output port.

0 = Lane is off.

1 = Lane is on.

LaneEn[0] = clock lane enabler

LaneEn[1] = data lane 0 enabler

LaneEn[2] = data lane 1 enabler

LaneEn[3] = data lane 2 enabler

R/W 0

Summary of Contents for S5PC100

Page 2: ...er applications intended to support or sustain life or for any other application in which the failure of the Samsung product could create a situation where personal injury or death may occur Should the Buyer purchase or use a Samsung product for any such unintended or unauthorized application the Buyer shall indemnify and hold Samsung and its officers employees subsidiaries affiliates and distribu...

Page 3: ...ller OneNAND controller NAND Flash controller DMA controller System timer MIPI DSIM MIPI CSIS USB HOST controller USB2 0 HS OTG Modem interface SD MMC controller Display controller Camera interface JPEG FIMG 3DSE TV Video DAC Video Processor Mixer HDMI Multi format codec Audio sub system ADC Touch screen interface Keypad interface Security system Advanced crypto engine AP design January 2009 0 20 ...

Page 4: ...00 has an optimized interface to external memory capable of sustaining the demanding memory bandwidths required in high end communication services The memory system has Flash ROM external memory ports for parallel access and DRAM port for high bandwidth DRAM port can be configured to support mobile DDR DDR2 or LPDDR2 Flash ROM Port supports NAND Flash NOR Flash OneNAND and ROM type external memory...

Page 5: ...CM I F 2ch S PDIF 1ch UART 4ch IrDA v1 1 I2C 2ch HS SPI 3ch MIPI HSI Modem I F USB Host 1 1 OTG 2 0 CAN I F 2ch HS MMC SD 3ch CFII ATA GPIO 32KB 32KB I D Cache 667MHz 1 20 V 256KB L2 Cache NEON Secure iRAM Secure iROM Crypto Accelerator Dynamic Voltage Frequency Scaling 24 18 bit TFT LCD 8 bit for Dual i80 1024x768 output 5 layer PIP 16 bit a blending Camera IF CSI 2 720p 30fps MFC Codec H 263 H 2...

Page 6: ... Divx video up to 720p 30fps JPEG codec support up to 0 5Mpixels MHz 3D Graphics Acceleration with programmable shader 2D Graphics Acceleration with BitBlit and Rotation 1 2 4 8 bpp Palletized or 8 16 24bpp Non Palletized Color TFT support up to 2048x2048 resolution TV out and HDMI interface support for NTSC and PAL mode with image enhancer MIPI HSI MIPI DSI and MIPI CSI interface AC 97 audio code...

Page 7: ...rements for power optimized mobile devices needing operation in less than 300mW and performance optimized consumer applications requiring 2000 Dhrystone MIPS ARM s first superscalar processor featuring technology for enhanced code density and performance NEONTM technology for multimedia and signal processing and Jazelle RCT technology for efficient support of ahead of time and just in time compila...

Page 8: ...ity support up to 32 Gb Muxed OneNAND Interface x16 data bus Supports byte and half word access Supports 2KB page mode Supports FlexOneNAND 4KB page mode Mobile DDR Interface x32 data bus with 333Mbps pin double data rate DDR 1 8V interface voltage Density support up to 1 Gb per 1 CS support upto 2 CS DDR2 Interface x32 data bus with 333Mbps pin double data rate DDR 1 8V interface voltage Density ...

Page 9: ...63 H 264 and decoding of MPEG 2 WMV9 Divx Xvid MPEG4 up to ASP 720p 30fps 1280x720 H 263 P3 720p 30fps 1280x720 H 264 up to HP 720p 30fps 1280x720 VC1 Decoding 720p 30fps 1280x720 Resolutions upto 1280x720 720p D1 VGA QVGA CIF QCIF Minimum size 32x16 16x32 for decoder 32x32 for encoder Supports single stream 720p 30fps encoding decoding Time multiplexed multi stream encoding decoding with fine gra...

Page 10: ... at decoding JPEG Codec Compression decompression up to 65536x65536 Support format of compression Input raw image YCbCr4 2 2 or RGB565 Output JPEG file Baseline JPEG of YCbCr4 2 2 or YCbCr4 2 0 Support format of decompression Refer to chapter 9 4 Input JPEG file Baseline JPEG of YCbCr4 4 4 YCbCr4 2 2 YCbCr4 2 0 gray Output raw image YCbCr4 2 2 or YCbCr4 2 0 Support general purpose color space conv...

Page 11: ...upport for 480p 576p 720p 1080i cannot support 480i Support for HDCP v1 1 Rotator Supported image format YCbCr422 interleave YCbCr420 non interleave RGB565 and RGB888 unpacked Supported rotate degree 90 180 270 flip vertical and flip horizontal Video processor Support BOB 2D IPC mode Produce YCbCr 4 4 4 outputs to help MIXER to blend video and graphics 1 4X to 16X vertical scaling with 4 tap 16 ph...

Page 12: ...n H W Crypto Accelerator Securely integrated DES TDES AES SHA 1 PRNG and PKA Access control Security Domain Manager with the ARM TrustZone HW Enabling enhanced secure platform for separate secure non secure execution environment for security sensitive application Secure JTAG Authentication of JTAG user Access control in JTAG mode 3 6 DISPLAY CONTROLLER TFT LCD Interface Support 24 18 16 bpp parall...

Page 13: ...PRODUCT OVERVIEW S5PC100 USER S MANUAL REV1 0 1 1 10 16 level alpha blending ITU BT601 656 format output ...

Page 14: ...Interface 2 ch IIS bus for the audio codec interface with DMA based operation Serial 8 16 24 bit per channel data transfers Supports IIS MSB justified and LSB justified data format Support PCM 5 1 channel Various bit clock frequency and codec clock frequency support 16 24 32 48 fs of bit clock frequency 256 384 512 768 fs of codec clock Support 1 5 1ch I2S in Audio Subsystem and 2 2ch I2S Modem In...

Page 15: ...n UCLK Programmable baud rate Supports IrDA 1 0 SIR 115 2Kbps mode Loop back mode for testing Non integer clock divides in Baud clock generation BRM USB OTG 2 0 Complies with the USB OTG 2 0 Supports high speed up to 480Mbps On chip USB transceiver USB Host 1 1 Complies with the USB Host 1 1 Supports full speed up to 12Mbps On chip USB transceiver CAN Interface Supports CAN protocol version 2 0 pa...

Page 16: ...rt 2xUART without flow control or 1xUART with flow control 1x IrDA GPB 8 in out port 2x SPI GPC 5 in out port I2S PCM AC97 GPD 7 in out port 2xI2C PWM External DMA request SPDIF GPE0 1 14 in out port Camera I F 0 MMC channel1 GPE0 support only 4 bit mode MMC if 8 bit mode is needed you can use GPE1 for another 4 bit data channel GPF0 1 2 3 28 in out port LCD I F GPG0 1 2 3 25 in out port 3xMMC cha...

Page 17: ...bit internal timer with interrupt based operation 3 ch 32 bit Timer with PWM Programmable duty cycle frequency and polarity Dead zone generation Support external clock source System timer Accurate timer providing exact 1ms tick at any power mode except sleep Changeable interrupt interval without stopping reference tick timer DMA Micro code programming based DMA The specific instruction set provide...

Page 18: ...es are available such as Idle Stop Deep Idle Deep Stop and Sleep mode Sleep mode s wake up sources are external interrupts RTC alarm Tick timer and the key interface Stop and Deep Stop mode s wake up sources are MMC Touch screen interface Modem interface MIPI HSI and the system timer as well all the wake up sources of Sleep mode Deep Idle mode s wake up sources are 5 1ch I2S as well all the wake u...

Page 19: ...3MHz ARM1 33V Internal 1 25V NOTES 1 S5PC100 has three system clock domains called D0 D1 and D2 D0 domain is for CPU system while D1 for multimedia D2 for low power audio Nominal 133 166MHz represents that D1 system frequency is 133MHz D0 system frequency is 166MHz at 1 2V power level 2 C100 supports only sync mode between CPU and D0 system 3 The voltage of the external Memory I O interface depend...

Page 20: ...Refer to 10 1 Audio subsystem 0xD000_0000 0xD000_8000 32KB IROM 0xD002_0000 0xD003_8000 96KB IRAM 0xD800_0000 0xE000_0000 128MB DMZ ROM 0xE000_0000 0x0000_0000 512MB SFR Region Start Addr Limit Addr Size Usage 0x0002_0000 0x0002_1000 4KB IROM s Stack 0x0002_1000 0x0002_4000 12KB User specific purpose 0x0002_4000 0x0003_4000 64KB Secure Domain Manager 0x0003_4000 0x0003_8000 16KB BL1 NOTE TZPCR0SIZ...

Page 21: ...MEMORY MAP S5PC100 USER S MANUAL REV1 0 1 2 2 ...

Page 22: ...IEC 0xE110_0000 0xE310_0000 TZIC1 0xE510_0000 IEM_APC 0xE100_0000 AXI_D0 bus 0xE300_0000 TZIC0 0xE500_0000 0xE0F0_0000 0xE2F0_0000 0xE4F0_0000 0xE0E0_0000 0xE2E0_0000 0xE4E0_0000 0xE0D0_0000 0xE2D0_0000 0xE4D0_0000 0xE0C0_0000 0xE2C0_0000 0xE4C0_0000 0xE0B0_0000 0xE2B0_0000 0xE4B0_0000 0xE0A0_0000 0xE2A0_0000 0xE4A0_0000 0xE090_0000 TZPC2 0xE290_0000 0xE490_0000 0xE080_0000 TZPC1 0xE280_0000 0xE48...

Page 23: ...troller 0xE710_0000 0xE910_0000 0xEB10_0000 SROM controller 0xE700_0000 PDMA0 0xE900_0000 0xEB00_0000 0xE6F0_0000 0xE8F0_0000 0xEAF0_0000 0xE6E0_0000 0xE8E0_0000 0xEAE0_0000 0xE6D0_0000 0xE8D0_0000 0xEAD0_0000 0xE6C0_0000 0xE8C0_0000 0xEAC0_0000 0xE6B0_0000 0xE8B0_0000 0xEAB0_0000 0xE6A0_0000 0xE8A0_0000 0xEAA0_0000 0xE690_0000 0xE890_0000 0xEA90_0000 0xE680_0000 0xE880_0000 0xEA80_0000 0xE670_000...

Page 24: ...0xEF00_0000 MFC 0xF100_0000 0xECF0_0000 0xEEF0_0000 0xF0F0_0000 0xECE0_0000 0xEEE0_0000 0xF0E0_0000 0xECD0_0000 0xEED0_0000 0xF0D0_0000 MIPI CSIS 0xECC0_0000 0xEEC0_0000 0xF0C0_0000 MIPI DSIM 0xECB0_0000 0xEEB0_0000 0xF0B0_0000 MIPI HSI RX 0xECA0_0000 0xEEA0_0000 0xF0A0_0000 MIPI HSI TX 0xEC90_0000 0xEE90_0000 0xF090_0000 CAN1 0xEC80_0000 FIMG 2D 0xEE80_0000 0xF080_0000 CAN0 0xEC70_0000 0xEE70_000...

Page 25: ...ger 0xF510_0000 0xF710_0000 ADC Touch screen 0xF300_0000 SECKEY 0xF500_0000 0xF700_0000 0xF2F0_0000 0xF4F0_0000 0xF6F0_0000 0xF2E0_0000 0xF4E0_0000 0xF6E0_0000 0xF2D0_0000 0xF4D0_0000 0xF6D0_0000 0xF2C0_0000 0xF4C0_0000 0xF6C0_0000 0xF2B0_0000 0xF4B0_0000 0xF6B0_0000 0xF2A0_0000 0xF4A0_0000 0xF6A0_0000 0xF290_0000 0xF490_0000 0xF690_0000 0xF280_0000 0xF480_0000 0xF680_0000 0xF270_0000 0xF470_0000 ...

Page 26: ...S5PC100 USER S MANUAL REV1 0 BALL MAP SIZE POP 1 1 1 1 3 BALL MAP SIZE 1 PIN ASSIGNMENT 1 1 PIN ASSIGNMENT DIAGRAM 580 BALL FCFBGA POP Figure 1 3 1 S5PC100 Pin Assignment 580 FCFBGA Bottom View ...

Page 27: ...TA 7 G8 Xm0ADDR 9 A17 VDDQ_B C3 VSS D19 Xi2c0SDA G9 Xm0FRnB 2 A18 Xm0INPACKn C4 Xm0DATA 3 D20 Xmmc1DATA 0 G10 Xm0WAITn A19 N C C5 Xm0DATA 4 D21 Xmmc1CLK G11 Xm0ADDR 2 A20 XjTCK C6 Xm0DATA 8 D25 XuTXD 2 G12 VDDQ_DDR A21 XjTDO C7 Xm0DATA 12 D26 XspiMOSI 0 G13 VDDQ_DDR A22 XuRXD 2 C8 Xm0DATA 15 D27 XuRXD 1 G14 VSS A23 XuTXD 1 C9 VSS E1 XvVD 9 G15 VSS A24 Xmmc0CMD C10 Xm0ADDR 5 E2 Xm0CSn 4 G16 Xm0ADDR...

Page 28: ... L3 XvHSYNC M24 XEINT 1 P24 XEINT 8 H26 XspiMISO 0 L4 VDDQ_CI M25 POP_DATA 2 P25 XEINT 20 H27 XjDBGSEL L6 XvVD 21 M26 VDD_DRAM P26 VSS J1 VDD_DRAM L7 XvVD 10 M27 POP_DATA 4 P27 VSS J2 XiemSPWI L8 XvVD 13 N1 Xmmc2DATA 0 R1 Xi2s1SCLK J3 VSS L10 Xm0BEn 1 N2 Xmmc2DATA 1 R2 VSS J4 VSS L11 VDD_INT N3 XciCLKenb R3 Xi2s0CDCLK J6 XvVD 2 L12 XvVD 0 N4 XciVSYNC R4 Xi2s0SDO 2 J7 XvVD 7 L13 VDD_INT N6 VDDQ_LCD...

Page 29: ...T Y17 VSS_MPLL AB9 VSS_HDMI T21 XEINT 23 V15 XusbDRVVBUS Y18 VDD33_UOTG AB10 XhdmiREXT T22 XEINT 27 V16 VSS Y19 XOM 1 AB11 VSS_MIPI_PLL18 T24 XEINT 4 V17 VDDQ_SYS5 Y20 XEINT 11 AB12 VSS_MIPI T25 XEINT 19 V20 XEINT 14 Y21 VSS AB13 VSS_MIPI T26 POP_DATA 5 V21 XEINT 29 Y22 XOM 4 AB14 VSS_USBHOST T27 POP_DM 0 V22 XEINT 28 Y24 VSS_ADC AB15 XuhDN U1 VCCQ_O V24 XEINT 31 Y25 VSS AB16 VSS_EPLL U2 VCCQ_O V2...

Page 30: ...1P AG12 POP_DATA 29 AD19 XusbDP AF4 VSS AG13 POP_DATA 28 AD20 XusbDM AF5 XhdmiTX0P AG14 POP_DATA 31 AD21 VSS AF6 XhdmiTXCP AG15 POP_DATA 30 AD25 XadcAIN 1 AF7 XmipiTXCN AG16 VDD_DRAM AD26 POP_DM 1 AF8 XmipiDP 2 AG17 POP_DATA 16 AD27 POP_INTB_A AF9 XmipiDN 4 AG18 POP_DATA 17 AE1 XhdmiTX2P AF10 N C AG19 POP_ADDR 0 AE2 XhdmiTX2N AF11 XmipiRXCN AG20 POP_RASN AE3 XmsmADDR 0 AF12 POP_DATA 26 AG21 POP_CL...

Page 31: ...D I O VDDQ_CI L4 CAMIF I O VDDQ_MMC R7 MMC2 I O VDDQ_AUD U3 Audio I O VDDQ_MSM W6 Y6 Host IF I O VDDQ_SYS0 L26 GPH Main xtal I O VDDQ_SYS2 V12 X tal I O VDDQ_SYS5 V17 Special clock I O VDDQ_CAN U18 CAN I O VDDQ_EXT M20 R21 JTAG I O MMC I O Digital I O VDDQ_UHOST Y16 USB Host I O VDD_RTC V25 RTC VDD_INT F8 H14 H15 H16 K15 L11 L13 L14 L15 T12 U12 U13 U14 U15 V13 V14 Y12 Internal logic VDD_ALIVE J26 ...

Page 32: ...SSQ_SYS0 VSSQ_SYS2 VSSQ_SYS5 VSSQ_CG VSSQ_CAN VSSQ_EXT Digital I O VSSQ_UH VSS_INT VSS_ALIVE Internal Logic VSS_ARM A1 A2 A26 A27 B1 B2 B26 B27 C3 C9 C15 C21 C25 D9 D15 F14 F25 G6 G14 G15 H10 H22 J3 J4 J22 K22 K24 K25 L16 L22 M13 M14 M15 M16 M17 M22 N7 N12 N16 N17 P12 P16 P17 P26 P27 R2 R12 R16 T13 T14 T15 T20 U16 V1 V2 V3 V16 Y11 Y21 Y25 Y26 AB14 AC3 AD15 AD21 AE4 AE11 AE15 AE21 AF1 AF4 AF26 AF27...

Page 33: ...BALL MAP SIZE POP S5PC100 USER S MANUAL REV1 0 1 1 8 VSS_HPLL AA12 VSSQ_UOTG AA19 VSS_UOTG AF21 VSS_ADC Y24 ...

Page 34: ...S5PC100 USER S MANUAL REV1 0 BALL MAP SIZE POP 1 1 9 1 4 MCP CONNECTION ...

Page 35: ...BALL MAP SIZE POP S5PC100 USER S MANUAL REV1 0 1 1 10 2 PACKAGE DIMENSION Figure 12 2 1 S5PC100 Package Dimension 580 FCFBGA Top View ...

Page 36: ...S5PC100 USER S MANUAL REV1 0 BALL MAP SIZE POP 1 1 11 Figure 12 2 2 S5PC100 Package Dimension 580 FCFBGA Side View ...

Page 37: ...C100 USER S MANUAL REV1 0 BALL MAP SIZE SingleChip 1 1 1 1 3 BALL MAP SIZE 1 PIN ASSIGNMENT 1 1 PIN ASSIGNMENT DIAGRAM 521 BALL FCFBGA SINGLE CHIP Figure 1 3 1 S5PC100 Pin Assignment 521 FCFBGA Bottom View ...

Page 38: ...DDR 4 C3 Xm0DATA 14 D20 VDDQ_DDR H7 XefFSOURCE_0 A18 Xm1ADDR 13 C4 Xm0DATA 12 D25 Xm1DQM 0 H8 Xm0RESET A19 Xm1ADDR 8 C5 Xm0DATA 11 D26 Xm1DATA 2 H9 Xm0CDn A20 Xm1DATA 13 C6 Xm0DATA 15 D27 Xm1DATA 3 H10 Xm0BEn 1 A21 Xm1DATA 12 C7 Xm0FRnB 2 E1 Xm0ADDR 0 H11 Xm1ADDR 11 A22 Xm1DATA 15 C8 VSS E2 Xm0ADDR 11 H12 Xm1CKE 1 A23 Xm1DQS 1 C9 Xm0IOWRn E3 VDDQ_M0 H13 Xm1CKE 0 A24 Xm1DQSn 1 C10 Xm1DATA 31 E25 Xp...

Page 39: ...K M4 Xm0CSn 5 P7 XvVD 13 T12 VDDQ_MMC J27 XspiCSn 0 M7 XvVD 17 P8 XciDATA 0 T13 VSS K1 XvVD 21 M8 XvVD 12 P9 VDDQ_LCD T14 VSS K2 Xm0ADDR 6 M9 XvVD 20 P11 XvVD 16 T15 VSS K3 VDDQ_M0 M11 VDD_INT P12 XvVD 11 T16 VSS K4 VSS M12 VDD_INT P16 VSS T17 VDD_INT K7 Xm0ADDR 7 M13 VDD_INT P17 VDD_INT T19 XEINT 24 K8 Xm0ADDR 17 M14 VDD_INT P19 XjTCK T20 XnRESET K9 Xm0ADDR 19 M15 VDD_INT P20 XEINT 16 T21 XEINT 5...

Page 40: ...XmsmDATA 11 AE18 VSS_EPLL V20 XEINT 9 Y14 XmsmADDR 8 AC25 XadcAIN 8 AE19 XuhDP V21 XOM 2 Y15 XEINT 30 AC26 VDD33_ADC AE20 XuhDN V24 XEINT 1 Y16 XEINT 10 AC27 XadcAIN 9 AE21 VDD_INT V25 XEINT 0 Y17 XEINT 13 AD1 XmsmDATA 8 AE22 VDD33_UOTG V26 XjDBGSEL Y18 XEINT 11 AD2 XmsmDATA 3 AE23 XusbVBUS V27 XEINT 4 Y19 XOM 1 AD3 XmsmADDR 12 AE24 XadcAIN 0 W1 Xi2s0SDO 2 Y20 XnBATF AD8 VSS12_HDMI AE25 XadcVref W...

Page 41: ...mipiDP 1 AG4 XdacOUT 2 AG19 XmipiRXCN AF17 XmipiDN 2 AG5 VSS30_DAC_D AG20 XmipiRXCP AF18 XmipiDP 2 AG6 XhdmiTX2N AG21 VSS_UHOST AF19 XmipiDN 4 AG7 XhdmiTX2P AG22 VDD_UHOST AF20 XmipiDP 4 AG8 XhdmiTX1N AG23 XusbDP AF21 XusbID AG9 XhdmiTX1P AG24 XusbDM AF22 VDD12_UOTG AG10 XhdmiTX0N AG25 VSS AF23 VSS12_UOTG AG11 XhdmiTX0P AG26 VSS AF24 XusbREXT AG12 XhdmiTXCN AG27 VSS AF25 XusbXTO AG13 XhdmiTXCP AF2...

Page 42: ...DQ_CAN U20 CAN I O VDDQ_EXT N17 R26 JTAG I O MMC0 1 I O Digital I O VDDQ_UHOST AG22 USB Host I O VDD_RTC AA25 RTC VDD_INT AD11 AE21 D15 D8 M11 M12 M13 M14 M15 N12 P17 R17 R9 T17 Internal logic VDD_ALIVE Y25 Alive logic Internal Logic VDD_ARM G17 G18 G19 G20 H21 J16 J17 J18 J19 J21 K19 L16 L17 M17 Cortex A8 core VDD30_DAC_A AE4 DAC analog part VDD30_DAC_D AF4 DAC digital part VDD12_HDMI AD9 AE9 HDM...

Page 43: ...VSSQ_EXT Digital I O VSSQ_UHOST VSS_INT VSS_ALIVE Internal Logic VSS_ARM A1 A2 A26 A27 AD10 AD20 AF1 AF27 AG1 AG2 AG26 AG27 B1 B27 C22 C8 D16 D19 D3 H16 H17 H18 H19 H20 J15 J20 K20 K4 L11 L12 L13 L14 L15 M16 N16 P16 R16 T13 T14 T15 T16 T26 Y4 VSS30_DAC_A AE2 VSS30_DAC_D AG5 VSS12_HDMI AD8 AF11 VSS12_MIPI AD12 AE15 VSS18_MIPI_PLL AE12 VSS_APLL AD16 VSS_MPLL AD19 VSS_EPLL AE18 VSS_HPLL AF12 VSS33_UO...

Page 44: ...BALL MAP SIZE SingleChip S5PC100 USER S MANUAL REV1 0 1 1 8 2 PACKAGE DIMENSION Figure 1 3 1 S5PC100 Package Dimension 521 FCFBGA Top View ...

Page 45: ...S5PC100 USER S MANUAL REV1 0 BALL MAP SIZE SingleChip 1 1 9 Figure 1 3 2 S5PC100 Package Dimension 521 FCFBGA Side View ...

Page 46: ... or SD Memory including Movi NAND and iNAND USB If there are more than one instance of the controller of the booting device only the first instance of the controller is used for booting S5PC100 has 32KB ROM iROM and 96KB SRAM iRAM inside the chip At the system reset the program execution starts at iROM Figure 2 6 1 Booting Block Diagram ...

Page 47: ...main on X X Wakeup from DEEP_IDLE Top domain off with retention X X Wakeup from DEEP_IDLE Top domain off O O On Hardware reset and watchdog reset the system has to do full booting including BL1 and OS image loading On ESLEEP case the set product does not ensure that DRAM memory s contents are preserved So full booting is also required These reset status which requires full booting is classified as...

Page 48: ...s then jump to 0x34010 First 4word is reserved 7 If integrity check fails then it stops NOTE1 In case of SD MMC iROM code load 9KB at 0x34000 from end of memory device NOTE2 In case of OneNAND and NAND iROM code load 16KB at 0x34000 from the beginning Block 0 of memory device block NOTE3 Bad Block Information is in 6th byte of Spare Area Block 0 in case of 512 byte Page NAND device And the rest of...

Page 49: ...IROM CODE S5PC100 USER S MANUAL REV1 0 2 6 4 12 Mhz 300 0 Mhz 100 0 Mhz 79 5 Mhz 20 6 Mhz ...

Page 50: ...is as follows 1 Check the integrity of the RSA public key on the booting device with the hash value of the RSA key which is stored on the e fuse ROM 128 bits of e fuse are used for this integrity check 2 Load BL1 to iRAM 3 Check the integrity of BL1 with the RSA public key Figure 2 6 2 shows the above sequence Second level Bootloader On SoC Off SoC memory device iROM 1st Bootloader RSA Public Key ...

Page 51: ...d boot loader in MMC 11 Reserved OM 0 APLL MPLL input selection 0 XXTI 1 XusbXTI XOM 4 0 Dedicated NFMOD 5 0 Input NFMOD 5 0 2nd booting from the device selected by OM 2 1 1 2nd booting from USB When OM 2 1 00 2nd boot loader in NAND Flash NFMOD 1 0 00 Small Block 512page 10 Large Block 2048page 11 Dlarge Block 4096page NFMOD 2 0 3 addr cycles for small block or 4 cycles for large block 1 4 addr c...

Page 52: ...er represents the revision number which does not need to change the SW while the main revision number represents the revision number need to change the SW NOTE PRO_ID register 7 0 depends on the e fuse ROM value Although the reset value of PRO_ID register 7 0 is 0xFF as power on sequence is progressing the e fuse ROM values are loaded to the registers Hence SW cannot read register reset value itse...

Page 53: ...3 28 in out pin LCD I F GPG0 1 2 3 25 in out pin 3xMMC channel Channel 0 supports 4 bit and 8 bit mode but channel 1 channel 2 supports only 4 bit mode SPI I2S PCM SPDIF GPH0 1 2 3 32 in out pin CAM IF channel Key pad External Wake up up to 32 bit GPI 8 in out pin Booting option PWI GPJ0 1 2 3 4 33 in out pin Modem IF HSI ATA GPK0 1 2 3 30 in out pin Control signals of EBI SMC NF CF OneNAND GPL 37...

Page 54: ...rtcXTI XrtcXTO OSC_B ETC4 0 X27mXTI X27mXTO ETC4 2 XXTI XXTO ETC4 4 XusbXTI XusbXTO 3 2 DC CURRENTS OF OUTPUT DRIVER TYPE A B OSC_A AND OSC_B VDD 3 3V 0 3V Driver Type VDD 3 00V T 125 VDD 3 30V T 25 VDD 3 60V T 40 1X 1 7mA 2 6mA 3 4mA 2X 3 4mA 5 2mA 6 9mA 3X 5 2mA 7 8mA 10 4mA A 4X 6 9mA 10 5mA 13 9mA 1X 3 4mA 5 2mA 6 9mA 2X 6 9mA 10 5mA 13 9mA 3X 10 4mA 15 7mA 20 9mA B 4X 13 9mA 21 0mA 27 9mA 1X ...

Page 55: ...VDD 2 50V T 25 VDD 2 70V T 40 1X 1 4mA 2 2mA 3 1mA 2X 2 8mA 4 4mA 6 2mA 3X 4 2mA 6 6mA 9 3mA A 4X 5 7mA 8 9mA 12 4mA 1X 2 8mA 4 4mA 6 2mA 2X 5 7mA 8 9mA 12 4mA 3X 8 5mA 13 3mA 18 6mA B 4X 11 4mA 17 8mA 24 8mA 1X 3 1uA 5 4uA 8 5uA OSC_A 2X 6 2uA 11 0uA 17 0uA 1X 65uA 95uA 120uA 2X 0 76mA 1 18mA 1 63mA 3X 1 6mA 2 4mA 3 3mA OSC_B 4X 4 7mA 7 3mA 10mA ...

Page 56: ...125 VDD 1 80V T 25 VDD 1 95V T 40 1X 1 1mA 1 6mA 2 4mA 2X 2 0mA 3 3mA 4 8mA 3X 3 0mA 4 9mA 7 3mA A 4X 4 0mA 6 6mA 9 7mA 1X 2 0mA 3 3mA 4 8mA 2X 4 0mA 6 6mA 9 7mA 3X 6 0mA 9 9mA 14 6mA B 4X 8 1mA 13 2mA 19 4mA 1X 2uA 3 7uA 6 2uA OSC_A 2X 4 1uA 7 5uA 12 0uA 1X 48uA 75uA 100uA 2X 0 55mA 0 89mA 1 29mA 3X 1 1mA 1 8mA 2 6mA OSC_B 4X 3 4mA 5 4mA 7 9mA ...

Page 57: ...rt it is not the same Therefore the registers in alive part keep their values during sleep mode Alive Part Pad control Interrupt Controller Pad control APB Bus APB Bus Interrupt Controller Wake up controller Register File Mux control APB Interface External Interrupt Control Async Interface Register File Mux control External Interrupt Control Figure 2 2 1 GPIO Block Diagram ...

Page 58: ... GPA0 4 UART1_RXD PD I A1 VDDQ_EXT XuTXD 1 GPA0 5 UART1_TXD PD I A1 VDDQ_EXT XuCTSn 1 GPA0 6 UART1_CTSn PD I A1 VDDQ_EXT XuRTSn 1 GPA0 7 UART1_RTSn PD I A1 VDDQ_EXT XuRXD 2 GPA1 0 UART2_RXD PD I A1 VDDQ_EXT XuTXD 2 GPA1 1 UART2_TXD PD I A1 VDDQ_EXT XuRXD 3 GPA1 2 UART3_RXD UART2_CTSn IrDA_RXD PD I A1 VDDQ_EXT XuTXD 3 GPA1 3 UART3_TXD UART2_RTSn IrDA_TXD PD I A1 VDDQ_EXT XuCLK GPA1 4 UARTCLK IrDA_S...

Page 59: ...1 1 CAM_A_D 6 SD1_D 6 PD I A1 VDDQ_CI XciD 7 GPE1 2 CAM_A_D 7 SD1_D 7 PD I A1 VDDQ_CI XciCLKenb GPE1 3 CAM_A_CLKOUT PD I A1 VDDQ_CI XciRESET GPE1 4 CAM_A_RESET PD I A1 VDDQ_CI XciFIELD GPE1 5 CAM_A_FIELD PD I A1 VDDQ_CI XvHSYNC GPF0 0 LCD_HSYNC SYS_CS0 VEN_HSYNC PD I A1 VDDQ_LCD XvVSYNC GPF0 1 LCD_VSYNC SYS_CS1 VEN_VSYNC PD I A1 VDDQ_LCD XvVDEN GPF0 2 LCD_VDEN SYS_RS VEN_HREF PD I A1 VDDQ_LCD XvVC...

Page 60: ...GPG0 1 SD0_CMD PD I A1 VDDQ_EXT Xmmc0D 0 GPG0 2 SD0_D 0 PD I A1 VDDQ_EXT Xmmc0D 1 GPG0 3 SD0_D 1 PD I A1 VDDQ_EXT Xmmc0D 2 GPG0 4 SD0_D 2 PD I A1 VDDQ_EXT Xmmc0D 3 GPG0 5 SD0_D 3 PD I A1 VDDQ_EXT Xmmc0D 4 GPG0 6 SD0_D 4 PD I A1 VDDQ_EXT Xmmc0D 5 GPG0 7 SD0_D 5 PD I A1 VDDQ_EXT Xmmc0D 6 GPG1 0 SD0_D 6 PD I A1 VDDQ_EXT Xmmc0D 7 GPG1 1 SD0_D 7 PD I A1 VDDQ_EXT Xmmc0CDn GPG1 2 SD0_CDn PD I A1 VDDQ_EXT...

Page 61: ...5 CG_GPO 3 PD I B VDDQ_SYS5 XEINT 16 GPH2 0 WKUP_INT 16 KP_COL 0 CAM_B_D 0 PD I B VDDQ_SYS0 XEINT 17 GPH2 1 WKUP_INT 17 KP_COL 1 CAM_B_D 1 PD I B VDDQ_SYS0 XEINT 18 GPH2 2 WKUP_INT 18 KP_COL 2 CAM_B_D 2 PD I B VDDQ_SYS0 XEINT 19 GPH2 3 WKUP_INT 19 KP_COL 3 CAM_B_D 3 PD I B VDDQ_SYS0 XEINT 20 GPH2 4 WKUP_INT 20 KP_COL 4 CAM_B_D 4 PD I B VDDQ_SYS0 XEINT 21 GPH2 5 WKUP_INT 21 KP_COL 5 CAM_B_D 5 PD I ...

Page 62: ...D I A1 VDDQ_MSM XmsmADDR 9 GPJ1 1 MSM_A 9 PD I A1 VDDQ_MSM XmsmADDR 10 GPJ1 2 MSM_A 10 PD I A1 VDDQ_MSM XmsmADDR 11 GPJ1 3 MSM_A 11 PD I A1 VDDQ_MSM XmsmADDR 12 GPJ1 4 MSM_A 12 PD I A1 VDDQ_MSM XmsmDATA 0 GPJ2 0 MSM_D 0 CF_D 0 PD I A1 VDDQ_MSM XmsmDATA 1 GPJ2 1 MSM_D 1 CF_D 1 PD I A1 VDDQ_MSM XmsmDATA 2 GPJ2 2 MSM_D 2 CF_D 2 PD I A1 VDDQ_MSM XmsmDATA 3 GPJ2 3 MSM_D 3 CF_D 3 PD I A1 VDDQ_MSM XmsmDA...

Page 63: ...n PU I A2 VDDQ_M0 Xm0DATA_RDn GPK1 3 EBI_DATA_RDn OH A2 VDDQ_M0 Xm0CFOEn GPK1 4 CF_OEn OH A2 VDDQ_M0 Xm0CFWEn GPK1 5 CF_WEn OH A2 VDDQ_M0 Xm0FCLE GPK2 0 NF_CLE OND_AVALID OL A2 VDDQ_M0 Xm0FALE GPK2 1 NF_ALE OND_SMCLK OL A2 VDDQ_M0 Xm0FWEn GPK2 2 NF_WEn OND_RPn OH A2 VDDQ_M0 Xm0FREn GPK2 3 NF_REn OH A2 VDDQ_M0 Xm0FRnB 0 GPK2 4 NF_RnB 0 OND_INT 0 PD I A2 VDDQ_M0 Xm0FRnB 1 GPK2 5 NF_RnB 1 OND_INT 1 P...

Page 64: ...ADDR 17 GPL2 1 EBI_A 17 OL A2 VDDQ_M0 Xm0ADDR 18 GPL2 2 EBI_A 18 OL A2 VDDQ_M0 Xm0ADDR 19 GPL2 3 EBI_A 19 OL A2 VDDQ_M0 Xm0ADDR 20 GPL2 4 EBI_A 20 OL A2 VDDQ_M0 Xm0DATA 0 GPL2 5 EBI_D 0 I A2 VDDQ_M0 Xm0DATA 1 GPL2 6 EBI_D 1 I A2 VDDQ_M0 Xm0DATA 2 GPL2 7 EBI_D 2 I A2 VDDQ_M0 Xm0DATA 3 GPL3 0 EBI_D 3 I A2 VDDQ_M0 Xm0DATA 4 GPL3 1 EBI_D 4 I A2 VDDQ_M0 Xm0DATA 5 GPL3 2 EBI_D 5 I A2 VDDQ_M0 Xm0DATA 6 G...

Page 65: ...F I B VDDQ_SYS0 XOM 0 OM 0 I B VDDQ_SYS0 XOM 1 OM 1 I B VDDQ_SYS0 XOM 2 OM 2 I B VDDQ_SYS0 XOM 3 OM 3 I B VDDQ_SYS0 XOM 4 OM 4 I B VDDQ_SYS0 XXTI XTI I VDDQ_SYS0 XXTO XTO OL VDDQ_SYS0 XrtcXTI RTC_XTI I VDD_RTC XrtcXTO RTC_XXTO OL VDD_RTC XusbXTI USB_XTI AI VDDQ_SYS2 XusbXTO USB_XTO AO VDDQ_SYS2 X27mXTI 27M_XTI I VDDQ_SYS2 X27mXTO 27M_XTO OL VDDQ_SYS2 XCLKOUT CLKOUT OL E1 VDDQ_SYS2 XnRSTOUT nRSTOUT...

Page 66: ...MIPI XmipiRXCN MIPI_RXCN OH VDD_MIPI XmipiDP 3 MIPI_DP 3 I VDD_MIPI XmipiDN 3 MIPI_DN 3 I VDD_MIPI XmipiDP 2 MIPI_DP 2 OH VDD_MIPI XmipiDPN 2 MIPI_DN 2 OH VDD_MIPI XmipiDP 1 MIPI_DP 1 OH VDD_MIPI XmipiDN 1 MIPI_DN 1 OH VDD_MIPI XmipiReg_cap MIPI_Reg_cap I VDD_MIPI XmipiTXCP MIPI_TXCP OH VDD_MIPI XmipiTXCN MIPI_TXCN OH VDD_MIPI XmipiDP 0 MIPI_DP 0 OH VDD_MIPI XmipiDN 0 MIPI_DN 0 OH VDD_MIPI XhdmiRE...

Page 67: ...OH A2 VDDQ_DDR Xm1SCLK DDR_SCLK OL A2 VDDQ_DDR Xm1nSCLK DDR_SCLKn OH A2 VDDQ_DDR Xm1CSn 0 DDR_CSn 0 OH A2 VDDQ_DDR Xm1CSn 1 DDR_CSn 1 OH A2 VDDQ_DDR Xm1ADDR 0 DDR_A 0 OL A2 VDDQ_DDR Xm1ADDR 1 DDR_A 1 OL A2 VDDQ_DDR Xm1ADDR 2 DDR_A 2 OL A2 VDDQ_DDR Xm1ADDR 3 DDR_A 3 OL A2 VDDQ_DDR Xm1ADDR 4 DDR_A 4 OL A2 VDDQ_DDR Xm1ADDR 5 DDR_A 5 OL A2 VDDQ_DDR Xm1ADDR 6 DDR_A 6 OL A2 VDDQ_DDR Xm1ADDR 7 DDR_A 7 OL...

Page 68: ...TA 13 DDR_D 13 I A2 VDDQ_DDR Xm1DATA 14 DDR_D 14 I A2 VDDQ_DDR Xm1DATA 15 DDR_D 15 I A2 VDDQ_DDR Xm1DATA 16 DDR_D 16 I A2 VDDQ_DDR Xm1DATA 17 DDR_D 17 I A2 VDDQ_DDR Xm1DATA 18 DDR_D 18 I A2 VDDQ_DDR Xm1DATA 19 DDR_D 19 I A2 VDDQ_DDR Xm1DATA 20 DDR_D 20 I A2 VDDQ_DDR Xm1DATA 21 DDR_D 21 I A2 VDDQ_DDR Xm1DATA 22 DDR_D 22 I A2 VDDQ_DDR Xm1DATA 23 DDR_D 23 I A2 VDDQ_DDR Xm1DATA 24 DDR_D 24 I A2 VDDQ_D...

Page 69: ...3 OL A2 VDDQ_DDR Xm1DATAQS 0 DDR_DQS 0 I A2 VDDQ_DDR Xm1DATAQS 1 DDR_DQS 1 I A2 VDDQ_DDR Xm1DATAQS 2 DDR_DQS 2 I A2 VDDQ_DDR Xm1DATAQS 3 DDR_DQS 3 I A2 VDDQ_DDR Xm1DATAQSn 0 DDR_DQSn 0 I A2 VDDQ_DDR Xm1DATAQSn 1 DDR_DQSn 1 I A2 VDDQ_DDR Xm1DATAQSn 2 DDR_DQSn 2 I A2 VDDQ_DDR Xm1DATAQSn 3 DDR_DQSn 3 I A2 VDDQ_DDR ...

Page 70: ...egister 0x0155 GPA1DRV 0xE030_002C R W Port Group GPA1 Drive strength control Register 0x0000 GPA1PDNCON 0xE030_0030 R W Port Group GPA1 Power down mode Configuration Register 0x00 GPA1PDNPULL 0xE030_0034 R W Port Group GPA1 Power down mode Pull up down Register 0x00 GPBCON 0xE030_0040 R W Port Group GPB Configuration Register 0x00000000 GPBDAT 0xE030_0044 R W Port Group GPB Data Register GPBPULL ...

Page 71: ...r GPE1PULL 0xE030_00C8 R W Port Group GPE1 Pull up down Register 0x0555 GPE1DRV 0xE030_00CC R W Port Group GPE1 Drive strength control Register 0x0000 GPE1PDNCON 0xE030_00D0 R W Port Group GPE1 Power down mode Configuration Register 0x00 GPE1PDNPULL 0xE030_00D4 R W Port Group GPE1 Power down mode Pull up down Register 0x00 GPF0CON 0xE030_00E0 R W Port Group GPF0 Configuration Register 0x00000000 G...

Page 72: ...000 GPG0DAT 0xE030_0164 R W Port Group GPG0 Data Register GPG0PULL 0xE030_0168 R W Port Group GPG0 Pull up down Register 0x5555 GPG0DRV 0xE030_016C R W Port Group GPG0 Drive strength control Register 0x0000 GPG0PDNCON 0xE030_0170 R W Port Group GPG0 Power down mode Configuration Register 0x00 GPG0PDNPULL 0xE030_0174 R W Port Group GPG0 Power down mode Pull up down Register 0x00 GPG1CON 0xE030_0180...

Page 73: ...control Register 0x0000 GPH2CON 0xE030_0C40 R W Port Group GPH2 Configuration Register 0x00000000 GPH2DAT 0xE030_0C44 R W Port Group GPH2 Data Register GPH2PULL 0xE030_0C48 R W Port Group GPH2 Pull up down Register 0x5555 GPH2DRV 0xE030_0C4C R W Port Group GPH2 Drive strength control Register 0x0000 GPH3CON 0xE030_0C60 R W Port Group GPH3 Configuration Register 0x00000000 GPH3DAT 0xE030_0C64 R W P...

Page 74: ...GPJ2 power down mode configuration register 0x00 GPJ2PDNPULL 0xE030_0254 R W Port Group GPJ2 power down mode pull up down register 0x00 GPJ3CON 0xE030_0260 R W Port Group GPJ3 Configuration Register 0x00000000 GPJ3DAT 0xE030_0264 R W Port Group GPJ3 Data Register GPJ3PUD 0xE030_0268 R W Port Group GPJ3 Pull up down Register 0x5555 GPJ3DRV 0xE030_026C R W Port Group GPJ3 Drive strength control Regi...

Page 75: ...e strength control Register 0xAAAA GPK2PDNCON 0xE030_02F0 R W Port Group GPK2 Power down mode Configuration Register 0x00 GPK2PDNPULL 0xE030_02F4 R W Port Group GPK2 Power down mode Pull up down Register 0x00 GPK3CON 0xE030_0300 R W Port Group GPK3 Configuration Register 0x22222222 GPK3DAT 0xE030_0304 R W Port Group GPK3 Data Register GPK3PUD 0xE030_0308 R W Port Group GPK3 Pull up down Register 0...

Page 76: ...3PDNCON 0xE030_0390 R W Port Group GPL3 Power down mode Configuration Register 0x00 GPL3PDNPULL 0xE030_0394 R W Port Group GPL3 Power down mode Pull up down Register 0x00 GPL4CON 0xE030_03A0 R W Port Group GPL4 Configuration Register 0x22222 GPL4DAT 0xE030_03A4 R W Port Group GPL4 Data Register GPL4PULL 0xE030_03A8 R W Port Group GPL4 Pull up down Register 0x0000 GPL4DRV 0xE030_03AC R W Port Group...

Page 77: ...INT6_CON 0xE030_0718 R W Non wake up Interrupt 6 Configuration Register 0x0 NWU_INT7_CON 0xE030_071C R W Non wake up Interrupt 7 Configuration Register 0x0 NWU_INT8_CON 0xE030_0720 R W Non wake up Interrupt 8 Configuration Register 0x0 NWU_INT9_CON 0xE030_0724 R W Non wake up Interrupt 9 Configuration Register 0x0 NWU_INT10_CON 0xE030_0728 R W Non wake up Interrupt 10 Configuration Register 0x0 NW...

Page 78: ...filter configuration register 1 0x0 NWU_INT10_FLTCON0 0xE030_0850 R W Non wake up Interrupt 10 filter configuration register 0 0x0 NWU_INT11_FLTCON0 0xE030_0858 R W Non wake up Interrupt 11 filter configuration register 0 0x0 NWU_INT11_FLTCON1 0xE030_085C R W Non wake up Interrupt 11 filter configuration register 1 0x0 NWU_INT12_FLTCON0 0xE030_0860 R W Non wake up Interrupt 12 filter configuration...

Page 79: ...030_0940 R W Non wake up Interrupt 16 Mask Register 0xff NWU_INT17_MASK 0xE030_0944 R W Non wake up Interrupt 17 Mask Register 0x1f NWU_INT18_MASK 0xE030_0948 R W Non wake up Interrupt 18 Mask Register 0xff NWU_INT19_MASK 0xE030_094C R W Non wake up Interrupt 19 Mask Register 0xff NWU_INT20_MASK 0xE030_0950 R W Non wake up Interrupt 20 Mask Register 0x0f NWU_INT0_PEND 0xE030_0A00 R W Non wake up I...

Page 80: ... Control Register 0x00 NWU_INT5_FIXPRI 0xE030_0B28 R W Non wake up Interrupt 5 Fixed Priority Control Register 0x00 NWU_INT6_FIXPRI 0xE030_0B2C R W Non wake up Interrupt 6 Fixed Priority Control Register 0x00 NWU_INT7_FIXPRI 0xE030_0B30 R W Non wake up Interrupt 7 Fixed Priority Control Register 0x00 NWU_INT8_FIXPRI 0xE030_0B34 R W Non wake up Interrupt 8 Fixed Priority Control Register 0x00 NWU_I...

Page 81: ...WKUP_INT_FLTCON16_19 0xE030_0E90 R W Wake up Interrupt Filter Configuration Register 16_19 0x0 WKUP_INT_FLTCON20_23 0xE030_0E94 R W Wake up Interrupt Filter Configuration Register 20_23 0x0 WKUP_INT_FLTCON24_27 0xE030_0E98 R W Wake up Interrupt Filter Configuration Register 24_27 0x0 WKUP_INT_FLTCON28_31 0xE030_0E9C R W Wake up Interrupt Filter Configuration Register 28_31 0x0 WKUP_INT_MASK0_7 0xE...

Page 82: ... NWU_INT0 6 0000 GPA0CON 7 31 28 0000 Input 0001 Output 0010 UART_1_RTSn 1111 NWU_INT0 7 0000 5 1 2 Port Group GPA1 Configuration Register GPA1CON R W Address 0xE030_0020 Field Bit Description Reset Value GPA1CON 0 3 0 0000 Input 0001 Output 0010 UART_2_RXD 1111 NWU_INT1 0 0000 GPA1CON 1 7 4 0000 Input 0001 Output 0010 UART_2_TXD 1111 NWU_INT1 1 0000 GPA1CON 2 11 8 0000 Input 0001 Output 0010 UART...

Page 83: ... 7 4 0000 Input 0001 Output 0010 I2S1_CDCLK 0011 PCM_1_EXTCLK 0100 AC97RESETn 1111 NWU_INT3 1 0000 GPCCON 2 11 8 0000 Input 0001 Output 0010 I2S1_LRCK 0011 PCM_1_FSYNC 0100 AC97SYNC 1111 NWU_INT3 2 0000 GPCCON 3 15 12 0000 Input 0001 Output 0010 I2S1_SDI 0011 PCM_1_SIN 0100 AC97SDI 1111 NWU_INT3 3 0000 GPCCON 4 19 16 0000 Input 0001 Output 0010 I2S1_SDO 0011 PCM_1_SOUT 0100 AC97SDO 1111 NWU_INT3 4...

Page 84: ...Output 0010 CAM_A_D 1 0011 SD_1_D 1 1111 NWU_INT5 4 0000 GPE0CON 5 23 20 0000 Input 0001 Output 0010 CAM_A_D 2 0011 SD_1_D 2 1111 NWU_INT5 5 0000 GPE0CON 6 27 24 0000 Input 0001 Output 0010 CAM_A_D 3 0011 SD_1_D 3 1111 NWU_INT5 6 0000 GPE0CON 7 31 28 0000 Input 0001 Output 0010 CAM_A_D 4 0011 SD_1_D 4 1111 NWU_INT5 7 0000 5 1 7 Port Group GPE1 Configuration Register GPE1CON R W Address 0xE030_00C0...

Page 85: ... 0001 Output 0010 LCD_VD 1 0011 SYS_VD 1 0100 VEN_D 1 1111 NWU_INT7 5 0000 GPF0CON 6 27 24 0000 Input 0001 Output 0010 LCD_VD 2 0011 SYS_VD 2 0100 VEN_D 2 1111 NWU_INT7 6 0000 GPF0CON 7 31 28 0000 Input 0001 Output 0010 LCD_VD 3 0011 SYS_VD 3 0100 VEN_D 3 1111 NWU_INT7 7 0000 5 1 9 Port Group GPF1 Configuration Register GPF1CON R W Address 0xE030_0100 Field Bit Description Reset Value GPF1CON 0 3 ...

Page 86: ...CON 2 11 8 0000 Input 0001 Output 0010 LCD_VD 14 0011 SYS_VD 14 0100 V656_D 6 1111 NWU_INT9 2 0000 GPF2CON 3 15 12 0000 Input 0001 Output 0010 LCD_VD 15 0011 SYS_VD 15 0100 V656_D 7 1111 NWU_INT9 3 0000 GPF2CON 4 19 16 0000 Input 0001 Output 0010 LCD_VD 16 0011 SYS_VD 16 1111 NWU_INT9 4 0000 GPF2CON 5 23 20 0000 Input 0001 Output 0010 LCD_VD 17 0011 SYS_VD 17 1111 NWU_INT9 5 0000 GPF2CON 6 27 24 0...

Page 87: ...0 Input 0001 Output 0010 SD_0_D 3 1111 NWU_INT11 5 0000 GPG0CON 6 27 24 0000 Input 0001 Output 0010 SD_0_D 4 1111 NWU_INT11 6 0000 GPG0CON 7 31 28 0000 Input 0001 Output 0010 SD_0_D 5 1111 NWU_INT11 7 0000 5 1 13 Port Group GPG1 Configuration Register GPG1CON R W Address 0xE030_0180 Field Bit Description Reset Value GPG1CON 0 3 0 0000 Input 0001 Output 0010 SD_0_D 6 1111 NWU_INT12 0 0000 GPG1CON 1...

Page 88: ... 2 0000 GPG3CON 3 15 12 0000 Input 0001 Output 0010 SD_2_D 1 0011 SPI_2_MOSI 0100 I2S2_SDI 0101 PCM_0_SIN 1111 NWU_INT14 3 0000 GPG3CON 4 19 16 0000 Input 0001 Output 0010 SD_2_D 2 0011 Reserved 0100 I2S2_SDO 0101 PCM_0_SOUT 1111 NWU_INT14 4 0000 GPG3CON 5 23 20 0000 Input 0001 Output 0010 SD_2_D 3 0011 Reserved 0100 Reserved 0101 SPDIF_0_OUT 1111 NWU_INT14 5 0000 GPG3CON 6 27 24 0000 Input 0001 O...

Page 89: ... 4 0000 Input 0001 Output 0010 WAKEUP_INT 9 0000 GPH1CON 0 3 0 0000 Input 0001 Output 0010 WAKEUP_INT 8 0000 Note WAKEUP_INT x are used for wake up source in Power down and Idle mode in Normal mode these are same as NWU_INTx 5 1 18 Port Group GPH2 Configuration Register GPH2CON R W Address 0xE030_0C40 GPH2CON Bit Description Reset Value GPH2CON 7 31 28 0000 Input 0001 Output 0010 WAKEUP_INT 23 001...

Page 90: ...CAM_B_FIELD 0000 GPH3CON 2 11 8 0000 Input 0001 Output 0010 WAKEUP_INT 26 0011 KEYPAD_ROW 2 0100 CAM_B_HREF 0000 GPH3CON 1 7 4 0000 Input 0001 Output 0010 WAKEUP_INT 25 0011 KEYPAD_ROW 1 0100 CAM_B_PVSYNC 0000 GPH3CON 0 3 0 0000 Input 0001 Output 0010 WAKEUP_INT 24 0011 KEYPAD_ROW 0 0100 CAM_B_PCLK 0000 Note WAKEUP_INT x are used for wake up source in Power down and Idle mode in Normal mode these ...

Page 91: ...0 Input 0001 Output 0010 MSM_A 4 0011 HSI_RXD 0100 CF_INTRQ 1111 NWU_INT16 4 0000 GPJ0CON 5 23 20 0000 Input 0001 Output 0010 MSM_A 5 0011 HSI_RX_FLAG 0100 CF_INPACKn 1111 NWU_INT16 5 0000 GPJ0CON 6 27 24 0000 Input 0001 Output 0010 MSM_A 6 0011 HSI_RX_WAKE 0100 CF_RESET 1111 NWU_INT16 6 0000 GPJ0CON 7 31 28 0000 Input 0001 Output 0010 MSM_A 7 0011 HSI_RX_READY 0100 CF_REG 1111 NWU_INT16 7 0000 5 ...

Page 92: ...001 Output 0010 MSM_D 5 0011 Reserved 0100 CF_D 5 1111 NWU_INT18 5 0000 GPJ2CON 6 27 24 0000 Input 0001 Output 0010 MSM_D 6 0011 Reserved 0100 CF_D 6 1111 NWU_INT18 6 0000 GPJ2CON 7 31 28 0000 Input 0001 Output 0010 MSM_D 7 0011 Reserved 0100 CF_D 7 1111 NWU_INT18 7 0000 5 1 24 Port Group GPJ3 Configuration Register GPJ3CON R W Address 0xE030_0260 Field Bit Description Reset Value GPJ3CON 0 3 0 00...

Page 93: ...11 8 0000 Input 0001 Output 0010 MSM_Rn 0011 Reserved 0100 CF_IORD_CFn 1111 NWU_INT20 2 0000 GPJ4CON 3 15 12 0000 Input 0001 Output 0010 MSM_IRQn 0011 Reserved 0100 CF_IOWR_CFn 1111 NWU_INT20 3 0000 5 1 26 Port Group GPK0 Configuration Register GPK0CON R W Address 0xE030_02A0 Field Bit Description Reset Value GPK0CON 0 3 0 0000 Input 0001 Output 0010 SMC_CSn 0 0010 GPK0CON 1 7 4 0000 Input 0001 Ou...

Page 94: ...11 8 0000 Input 0001 Output 0010 Reserved 0011 NF_FWEn 0100 Reserved 0101 OND_RPn 0101 GPK2CON 3 15 12 0000 Input 0001 Output 0010 Reserved 0011 NF_FREn 0011 GPK2CON 4 19 16 0000 Input 0001 Output 0010 NF_RnB 0 0011 0100 Reserved 0101 OND_INT 0 0101 GPK2CON 5 23 20 0000 Input 0001 Output 0010 NF_RnB 1 0011 0100 Reserved 0101 OND_INT 1 0101 GPK2CON 6 27 24 0000 Input 0001 Output 0010 NF_RnB 2 0011 ...

Page 95: ...t 0001 Output 0010 EBI_A 10 0010 GPL1CON 3 15 12 0000 Input 0001 Output 0010 EBI_A 11 0010 GPL1CON 4 19 16 0000 Input 0001 Output 0010 EBI_A 12 0010 GPL1CON 5 23 20 0000 Input 0001 Output 0010 EBI_A 13 0010 GPL1CON 6 27 24 0000 Input 0001 Output 0010 EBI_A 14 0010 GPL1CON 7 31 28 0000 Input 0001 Output 0010 EBI_A 15 0010 5 1 32 Port Group GPL2 Configuration Register GPL2CON R W Address 0xE030_0360...

Page 96: ...ut 0001 Output 0010 EBI_D 12 0010 GPL4CON 2 11 8 0000 Input 0001 Output 0010 EBI_D 13 0010 GPL4CON 3 15 12 0000 Input 0001 Output 0010 EBI_D 14 0010 GPL4CON 4 19 16 0000 Input 0001 Output 0010 EBI_D 15 0010 5 2 PORT DATA PULLING REGISTER 5 2 1 Port Data Registers GPA0DAT R W Address 0xE030_0004 GPA1DAT R W Address 0xE030_0024 GPBDAT R W Address 0xE030_0044 GPCDAT R W Address 0xE030_0064 GPDDAT R W...

Page 97: ...4 Field Bit Description Reset Value DAT n n 0 7 n If the bit is configured as input it represents the pin state If the bit is configured as output the pin state is the same as the value of the bit If the port is configured as functional pin an undefined value is read 5 2 2 Port Pull up down Register GPA0PULL R W Address 0xE030_0008 GPA1PULL R W Address 0xE030_0028 GPBPULL R W Address 0xE030_0048 G...

Page 98: ...UD R W Address 0xE030_0308 GPL0PULL R W Address 0xE030_0328 GPL1PULL R W Address 0xE030_0348 GPL2PULL R W Address 0xE030_0368 GPL3PUD R W Address 0xE030_0388 GPL4PULL R W Address 0xE030_03A8 Field Bit Description Reset Value PUD n n 0 7 2n 1 2n 00 Disables Pull up down 01 Enables Pull down 10 Enables Pull up 11 Reserved Refer to the Pin Summary table 5 2 3 Port Drive Strength Control Register GPA0...

Page 99: ...PK1DRV R W Address 0xE030_02CC GPK2DRV R W Address 0xE030_02EC GPK3DRV R W Address 0xE030_030C GPL0DRV R W Address 0xE030_032C GPL1DRV R W Address 0xE030_034C GPL2DRV R W Address 0xE030_036C GPL3DRV R W Address 0xE030_038C GPL4DRV R W Address 0xE030_03AC Field Bit Description Reset Value DRV n n 0 7 2n 1 2n Output Driver strength control register These registers are used in both Normal mode and Po...

Page 100: ...NCON R W Address 0xE030_02B0 GPK1PDNCON R W Address 0xE030_02E0 GPK2PDNCON R W Address 0xE030_02F0 GPK3PDNCON R W Address 0xE030_0310 GPL0PDNCON R W Address 0xE030_0330 GPL1PDNCON R W Address 0xE030_0350 GPL2PDNCON R W Address 0xE030_0370 GPL3PDNCON R W Address 0xE030_0390 GPL4PDNCON R W Address 0xE030_03B0 Field Bit Description Reset Value PDNCON n n 0 7 2n 1 2n 00 Output 0 01 Output 1 10 Input 1...

Page 101: ... W Address 0xE030_0234 GPJ2PDNPULL R W Address 0xE030_0254 GPJ3PDNPULL R W Address 0xE030_0274 GPJ4PDNPULL R W Address 0xE030_0294 GPK0PDNPULL R W Address 0xE030_02B4 GPK1PDNPULL R W Address 0xE030_02E4 GPK2PDNPULL R W Address 0xE030_02F4 GPK3PDNPULL R W Address 0xE030_0314 GPL0PDNPULL R W Address 0xE030_0334 GPL1PDNPULL R W Address 0xE030_0354 GPL2PDNPULL R W Address 0xE030_0374 GPL3PDNPULL R W A...

Page 102: ... 5 O MP1_5 5 DDR_D 20 IO MP1_1 4 DDR_A 6 O MP1_5 6 DDR_D 21 IO MP1_1 5 DDR_A 7 O MP1_5 7 DDR_D 22 IO MP1_1 6 DDR_A 8 O MP1_6 0 DDR_D 23 IO MP1_1 7 DDR_A 9 O MP1_6 1 DDR_D 24 IO MP1_2 0 DDR_A 10 O MP1_6 2 DDR_D 25 IO MP1_2 1 DDR_A 11 O MP1_6 3 DDR_D 26 IO MP1_2 2 DDR_A 12 O MP1_6 4 DDR_D 27 IO MP1_2 3 DDR_A 13 O MP1_6 5 DDR_D 28 IO MP1_2 4 DDR_A 14 O MP1_6 6 DDR_D 29 IO MP1_2 5 DDR_A 15 O MP1_6 7 D...

Page 103: ... MP1_8DRV R W Address 0xE030_04CC Reset Value 0x2AAA Field Bit Description Reset Value DRV n n 0 7 2n 1 2n In case of VDD_DDR 1 2V 00 2mA 01 4mA 10 6mA 11 8mA In case of VDD_DDR 1 8V 00 4mA 01 8mA 10 12mA 11 16mA 0xAAAA 5 4 PORT GROUP ETC CONTROL REGISTER Port Group ETCx controls 5 ports 5 4 1 Port Group ETC0 Pull up down Register ETC0PULL R W Address 0xE030_04E8 00 Disables Pull up down 01 Enable...

Page 104: ...scription Reset Value Reserved 9 0 Reserved 0x155 ETC1PULL 5 11 10 XDDR2_SEL pulling control register 0x1 Reserved 15 12 Reserved 0x8 5 4 4 Port Group ETC1 Drive strength control Register ETC1DRV R W Address 0xE030_050C 00 1x 01 2x 10 3x 11 4x Field Bit Description Reset Value Reseved 9 0 Reserved 0x000 ETC1DRV 5 11 10 XDDR2_SEL pin Drive strength control register 0x0 5 4 5 Port Group ETC2 Pull up...

Page 105: ...t Description Reset Value ETC3DRV 0 1 0 XI2S0LRCK pin Drive strength control register 0x0 ETC3DRV 1 3 2 XI2S0CDCLK pin Drive strength control register 0x0 ETC3DRV 2 5 4 XI2S0SCLK pin Drive strength control register 0x0 ETC3DRV 3 7 6 XI2S0SDI pin Drive strength control register 0x0 ETC3DRV 4 9 8 XI2S0SDO 0 pin Drive strength control register 0x0 ETC3DRV 5 11 10 XI2S0SDO 1 pin Drive strength control...

Page 106: ...detect all interrupt from successive interrupts Some interrupt detection will be missed Non wake up interrupt cannot use for wake up source If you need wake up interrupt source you can use Wake up interrupt and you need to set delay filter for the Wake up interrupt 5 5 1 Non wake up Interrupt 0 Configuration Register NWU_INT0_CON R W Address 0xE030_0700 Field Bit Description Reset Value NWU_INT0_C...

Page 107: ...s the signaling method for NWU_INT6 n n 0 5 000 Low level 001 High level 010 Falling edge 011 Rising edge 100 Both edge 000 5 5 8 Non wake up Interrupt 7 Configuration Register NWU_INT7_CON R W Address 0xE030_071C Field Bit Description Reset Value NWU_INT7_CON 7 n 4 2 n 4 Sets the signaling method for NWU_INT7 n n 0 7 000 Low level 001 High level 010 Falling edge 011 Rising edge 100 Both edge 000 ...

Page 108: ...s the signaling method for NWU_INT12 n n 0 2 000 Low level 001 High level 010 Falling edge 011 Rising edge 100 Both edge 000 5 5 14 Non wake up Interrupt 13 Configuration Register NWU_INT13_CON R W Address 0xE030_0734 Field Bit Description Reset Value NWU_INT13_CON 6 n 4 2 n 4 Sets the signaling method for NWU_INT13 n n 0 6 000 Low level 001 High level 010 Falling edge 011 Rising edge 100 Both edg...

Page 109: ...up Interrupt 18 Configuration Register NWU_INT18_CON R W Address 0xE030_0748 Field Bit Description Reset Value NWU_INT18_CON 7 n 4 2 n 4 Sets the signaling method for NWU_INT18 n n 0 7 000 Low level 001 High level 010 Falling edge 011 Rising edge 100 Both edge 000 5 5 20 Non wake up Interrupt 19 Configuration Register NWU_INT19_CON R W Address 0xE030_074C Field Bit Description Reset Value NWU_INT1...

Page 110: ...field means that 0 disables 1 enables Field Bit Description Reset Value FLTEN0 7 31 Digital Filter Enable for NWU_INT0 7 0 NWU_INT0 7 30 24 Filtering width for NWU_INT0 7 000 FLTEN0 6 23 Digital Filter Enable for NWU_INT0 6 0 NWU_INT0 6 22 16 Filtering width for NWU_INT0 6 000 FLTEN0 5 15 Digital Filter Enable for NWU_INT0 5 0 NWU_INT0 5 14 8 Filtering width for NWU_INT0 5 000 FLTEN0 4 7 Digital F...

Page 111: ...ltering width for NWU_INT2 3 000 FLTEN2 2 23 Digital Filter Enable for NWU_INT2 2 0 NWU_INT2 2 22 16 Filtering width for NWU_INT2 2 000 FLTEN2 1 15 Digital Filter Enable for NWU_INT2 1 0 NWU_INT2 1 14 8 Filtering width for NWU_INT2 1 000 FLTEN2 0 7 Digital Filter Enable for NWU_INT2 0 0 NWU_INT2 0 6 0 Filtering width for NWU_INT2 0 000 5 5 27 Non wake up Interrupt 2 Filter Configuration Register 1...

Page 112: ...Configuration Register 1 NWU_INT3_FLTCON1 R W Address 0xE030_081C The Digital Filter Enable field means that 0 disables 1 enables Field Bit Description Reset Value Reserved 31 8 Reserved 0 FLTEN3 4 7 Digital Filter Enable for NWU_INT3 4 0 NWU_INT3 4 6 0 Filtering width for NWU_INT3 4 000 5 5 30 Non wake up Interrupt 4 Filter Configuration Register 0 NWU_INT4_FLTCON0 R W Address 0xE030_0820 The Dig...

Page 113: ...Digital Filter Enable for NWU_INT5 3 0 NWU_INT5 3 30 24 Filtering width for NWU_INT5 3 000 FLTEN5 2 23 Digital Filter Enable for NWU_INT5 2 0 NWU_INT5 2 22 16 Filtering width for NWU_INT5 2 000 FLTEN5 1 15 Digital Filter Enable for NWU_INT5 1 0 NWU_INT5 1 14 8 Filtering width for NWU_INT5 1 000 FLTEN5 0 7 Digital Filter Enable for NWU_INT5 0 0 NWU_INT5 0 6 0 Filtering width for NWU_INT5 0 000 5 5 ...

Page 114: ... 0xE030_0834 The Digital Filter Enable field means that 0 disables 1 enables Field Bit Description Reset Value Reserved 31 16 Reserved 000 FLTEN6 5 15 Digital Filter Enable for NWU_INT6 5 0 NWU_INT6 5 14 8 Filtering width for NWU_INT6 5 000 FLTEN6 4 7 Digital Filter Enable for NWU_INT6 4 0 NWU_INT6 4 6 0 Filtering width for NWU_INT6 4 000 5 5 36 Non wake up Interrupt 7 Filter Configuration Registe...

Page 115: ...field means that 0 disables 1 enables Field Bit Description Reset Value FLTEN8 3 31 Digital Filter Enable for NWU_INT8 3 0 NWU_INT8 3 30 24 Filtering width for NWU_INT8 3 000 FLTEN8 2 23 Digital Filter Enable for NWU_INT8 2 0 NWU_INT8 2 22 16 Filtering width for NWU_INT8 2 000 FLTEN8 1 15 Digital Filter Enable for NWU_INT8 1 0 NWU_INT8 1 14 8 Filtering width for NWU_INT8 1 000 FLTEN8 0 7 Digital F...

Page 116: ...Non wake up Interrupt 9 Filter Configuration Register 1 NWU_INT9_FLTCON1 R W Address 0xE030_084C The Digital Filter Enable field means that 0 disables 1 enables Field Bit Description Reset Value FLTEN9 7 31 Digital Filter Enable for NWU_INT9 7 0 NWU_INT9 7 30 24 Filtering width for NWU_INT9 7 000 FLTEN9 6 23 Digital Filter Enable for NWU_INT9 6 0 NWU_INT9 6 22 16 Filtering width for NWU_INT9 6 000...

Page 117: ...11 2 22 16 Filtering width for NWU_INT11 2 000 FLTEN11 1 15 Digital Filter Enable for NWU_INT11 1 0 NWU_INT11 1 14 8 Filtering width for NWU_INT11 1 000 FLTEN11 0 7 Digital Filter Enable for NWU_INT11 0 0 NWU_INT11 0 6 0 Filtering width for NWU_INT11 0 000 5 5 44 Non wake up Interrupt 11 Filter Configuration Register 1 NWU_INT11_FLTCON1 R W Address 0xE030_085C The Digital Filter Enable field means...

Page 118: ...tal Filter Enable for NWU_INT13 3 0 NWU_INT13 3 30 24 Filtering width for NWU_INT13 3 000 FLTEN13 2 23 Digital Filter Enable for NWU_INT13 2 0 NWU_INT13 2 22 16 Filtering width for NWU_INT13 2 000 FLTEN13 1 15 Digital Filter Enable for NWU_INT13 1 0 NWU_INT13 1 14 8 Filtering width for NWU_INT13 1 000 FLTEN13 0 7 Digital Filter Enable for NWU_INT13 0 0 NWU_INT13 0 6 0 Filtering width for NWU_INT13...

Page 119: ... disables 1 enables Field Bit Description Reset Value Reserved 31 24 Reserved 000 FLTEN14 6 23 Digital Filter Enable for NWU_INT14 6 0 NWU_INT14 6 22 16 Filtering width for NWU_INT14 6 000 FLTEN14 5 15 Digital Filter Enable for NWU_INT14 5 0 NWU_INT14 5 14 8 Filtering width for NWU_INT14 5 000 FLTEN14 4 7 Digital Filter Enable for NWU_INT14 4 0 NWU_INT14 4 6 0 Filtering width for NWU_INT14 4 000 5...

Page 120: ... means that 0 disables 1 enables Field Bit Description Reset Value FLTEN16 3 31 Digital Filter Enable for NWU_INT16 3 0 NWU_INT16 3 30 24 Filtering width for NWU_INT16 3 000 FLTEN16 2 23 Digital Filter Enable for NWU_INT16 2 0 NWU_INT16 2 22 16 Filtering width for NWU_INT16 2 000 FLTEN16 1 15 Digital Filter Enable for NWU_INT16 1 0 NWU_INT16 1 14 8 Filtering width for NWU_INT16 1 000 FLTEN16 0 7 D...

Page 121: ...17 0 000 5 5 55 Non wake up Interrupt 17 Filter Configuration Register 1 NWU_INT17_FLTCON1 R W Address 0xE030_088C The Digital Filter Enable field means that 0 disables 1 enables Field Bit Description Reset Value Reserved 31 8 Reserved 000 FLTEN17 4 7 Digital Filter Enable for NWU_INT17 4 0 NWU_INT17 4 6 0 Filtering width for NWU_INT17 4 000 5 5 56 Non wake up Interrupt 18 Filter Configuration Reg...

Page 122: ...Digital Filter Enable field means that 0 disables 1 enables Field Bit Description Reset Value FLTEN19 3 31 Digital Filter Enable for NWU_INT19 3 0 NWU_INT19 3 30 24 Filtering width for NWU_INT19 3 000 FLTEN19 2 23 Digital Filter Enable for NWU_INT19 2 0 NWU_INT19 2 22 16 Filtering width for NWU_INT19 2 000 FLTEN19 1 15 Digital Filter Enable for NWU_INT19 1 0 NWU_INT19 1 14 8 Filtering width for NW...

Page 123: ... 8 Filtering width for NWU_INT20 1 000 FLTEN20 0 7 Digital Filter Enable for NWU_INT20 0 0 NWU_INT20 0 6 0 Filtering width for NWU_INT20 0 000 5 5 61 Non wake up Interrupt 0 Mask Register NWU_INT0_MASK R W Address 0xE030_0900 Field Bit Description Reset Value Reserved 31 8 Reserved 0 NWU_INT0_MASK n n 0 Enabled 1 Masked n 0 7 1 5 5 62 Non wake up Interrupt 1 Mask Register NWU_INT1_MASK R W Address...

Page 124: ... n 0 Enabled 1 Masked n 0 5 1 5 5 68 Non wake up Interrupt 7 Mask Register NWU_INT7_MASK R W Address 0xE030_091C Field Bit Description Reset Value Reserved 31 8 Reserved 0 NWU_INT7_MASK n n 0 Enabled 1 Masked n 0 7 1 5 5 69 Non wake up Interrupt 8 Mask Register NWU_INT8_MASK R W Address 0xE030_0920 Field Bit Description Reset Value Reserved 31 8 Reserved 0 NWU_INT8_MASK n n 0 Enabled 1 Masked n 0 ...

Page 125: ... n 0 Enabled 1 Masked n 0 6 1 5 5 75 Non wake up Interrupt 14 Mask Register NWU_INT14_MASK R W Address 0xE030_0938 Field Bit Description Reset Value Reserved 31 7 Reserved 0 NWU_INT14_MASK n n 0 Enabled 1 Masked n 0 6 1 5 5 76 Non wake up Interrupt 15 Mask Register NWU_INT15_MASK R W Address 0xE030_093C Field Bit Description Reset Value Reserved 31 8 Reserved 0 NWU_INT15_MASK n n 0 Enabled 1 Maske...

Page 126: ...bled 1 Masked n 0 3 1 5 5 82 Non wake up Interrupt 0 Pending Register NWU_INT0_PEND R W Address 0xE030_0A00 Field Bit Description Reset Value Reserved 31 8 Reserved 0 NWU_INT0_PEND n n 1 Interrupt occurred n 0 7 0 5 5 83 5 5 84 Non wake up Interrupt 1 Pending Register NWU_INT1_PEND R W Address 0xE030_0A04 Field Bit Description Reset Value Reserved 31 5 Reserved 0 NWU_INT1_PEND n n 1 Interrupt occu...

Page 127: ...Interrupt occurred n 0 5 0 5 5 90 Non wake up Interrupt 7 Pending Register NWU_INT7_PEND R W Address 0xE030_0A1C Field Bit Description Reset Value Reserved 31 8 Reserved 0 NWU_INT7_PEND n n 1 Interrupt occurred n 0 7 0 5 5 91 Non wake up Interrupt 8 Pending Register NWU_INT8_PEND R W Address 0xE030_0A20 Field Bit Description Reset Value Reserved 31 8 Reserved 0 NWU_INT8_PEND n n 1 Interrupt occurr...

Page 128: ...Interrupt occurred n 0 6 0 5 5 97 Non wake up Interrupt 14 Pending Register NWU_INT14_PEND R W Address 0xE030_0A38 Field Bit Description Reset Value Reserved 31 7 Reserved 0 NWU_INT14_PEND n n 1 Interrupt occurred n 0 6 0 5 5 98 Non wake up Interrupt 15 Pending Register NWU_INT15_PEND R W Address 0xE030_0A3C Field Bit Description Reset Value Reserved 31 8 Reserved 0 NWU_INT15_PEND n n 1 Interrupt ...

Page 129: ...cription Reset Value Reserved 31 8 Reserved 0 NWU_INT19_PEND n n 1 Interrupt occurred n 0 7 0 5 5 103 Non wake up Interrupt 20 Pending Register NWU_INT20_PEND R W Address 0xE030_0A50 Field Bit Description Reset Value Reserved 31 4 Reserved 0 NWU_INT20_PEND n n 1 Interrupt occurred n 0 3 0 5 5 104 Non wake up Interrupt Group Priority Control Register NWU_INT_GRPPRI R W Address 0xE030_0B00 Field Bit...

Page 130: ...INT group 10 priority rotate enable 0 NWU_INT9_PRI 9 NWU_INT group 9 priority rotate enable 0 NWU_INT8_PRI 8 NWU_INT group 8 priority rotate enable 0 NWU_INT7_PRI 7 NWU_INT group 7 priority rotate enable 0 NWU_INT6_PRI 6 NWU_INT group 6 priority rotate enable 0 NWU_INT5_PRI 5 NWU_INT group 5 priority rotate enable 0 NWU_INT4_PRI 4 NWU_INT group 4 priority rotate enable 0 NWU_INT3_PRI 3 NWU_INT gro...

Page 131: ...s 0xE030_0B10 Field Bit Description Reset Value Reserved 31 5 Reserved 0 Highest_GRP_NUM 4 0 Group number of the highest priority if fixed group priority mode 1 25 0 5 5 108 Non wake up Interrupt 0 Fixed Priority Control Register NWU_INT0_FIXPRI R W Address 0xE030_0B14 Field Bit Description Reset Value Reserved 31 3 Reserved 0 Highest_EINT_NUM 2 0 Interrupt number of the highest priority in Non wa...

Page 132: ...errupt Group 3 if fixed priority mode 0 7 0 5 5 112 Non wake up Interrupt 4 Fixed Priority Control Register NWU_INT4_FIXPRI R W Address 0xE030_0B24 Field Bit Description Reset Value Reserved 31 3 Reserved 0 Highest_EINT_NUM 2 0 Interrupt number of the highest priority in Non wake up Interrupt Group 4 if fixed priority mode 0 7 0 5 5 113 Non wake up Interrupt 5 Fixed Priority Control Register NWU_I...

Page 133: ...terrupt 9 Fixed Priority Control Register NWU_INT9_FIXPRI R W Address 0xE030_0B38 Field Bit Description Reset Value Reserved 31 3 Reserved 0 Highest_EINT_NUM 2 0 Interrupt number of the highest priority in Non wake up Interrupt Group 9 if fixed priority mode 0 7 0 5 5 118 Non wake up Interrupt 10 Fixed Priority Control Register NWU_INT10_FIXPRI R W Address 0xE030_0B3C Field Bit Description Reset V...

Page 134: ...Interrupt 14 Fixed Priority Control Register NWU_INT14_FIXPRI R W Address 0xE030_0B4C Field Bit Description Reset Value Reserved 31 3 Reserved 0 Highest_EINT_NUM 2 0 Interrupt number of the highest priority in Non wake up Interrupt Group 14 if fixed priority mode 0 7 0 5 5 123 Non wake up Interrupt 15 Fixed Priority Control Register NWU_INT15_FIXPRI R W Address 0xE030_0B50 Field Bit Description Re...

Page 135: ...Highest_EINT_NUM 2 0 Interrupt number of the highest priority in Non wake up Interrupt Group 18 if fixed priority mode 0 7 0 5 5 127 Non wake up Interrupt 19 Fixed Priority Control Register NWU_INT19_FIXPRI R W Address 0xE030_0B60 Field Bit Description Reset Value Reserved 31 3 Reserved 0 Highest_EINT_NUM 2 0 Interrupt number of the highest priority in Non wake up Interrupt Group 19 if fixed prior...

Page 136: ...g edge triggered 011 Rising edge triggered 100 Both edge triggered 101 111 Reserved Field Bit Description Reset Value Reserved 31 Reserved 0 WKUP_INT_CON0_7 7 30 28 Sets the signaling method for WKUP_INT 7 000 Reserved 27 Reserved 0 WKUP_INT_CON0_7 6 26 24 Sets the signaling method for WKUP_INT 6 000 Reserved 23 Reserved 0 WKUP_INT_CON0_7 5 22 20 Sets the signaling method for WKUP_INT 5 000 Reserv...

Page 137: ...erved 27 Reserved 0 WKUP_INT_CON8_15 6 26 24 Sets the signaling method for WKUP_INT 14 000 Reserved 23 Reserved 0 WKUP_INT_CON8_15 5 22 20 Sets the signaling method for WKUP_INT 13 000 Reserved 19 Reserved 0 WKUP_INT_CON8_15 4 18 16 Sets the signaling method for WKUP_INT 12 000 Reserved 15 Reserved 0 WKUP_INT_CON8_15 3 14 12 Sets the signaling method for WKUP_INT 11 000 Reserved 11 Reserved 0 WKUP...

Page 138: ...rved 27 Reserved 0 WKUP_INT_CON16_23 6 26 24 Sets the signaling method for WKUP_INT 22 000 Reserved 23 Reserved 0 WKUP_INT_CON16_23 5 22 20 Sets the signaling method for WKUP_INT 21 000 Reserved 19 Reserved 0 WKUP_INT_CON16_23 4 18 16 Sets the signaling method for WKUP_INT 20 000 Reserved 15 Reserved 0 WKUP_INT_CON16_23 3 14 12 Sets the signaling method for WKUP_INT 19 000 Reserved 11 Reserved 0 W...

Page 139: ...ved 27 Reserved 0 WKUP_INT_CON24_31 6 26 24 Sets the signaling method for WKUP_INT 30 000 Reserved 23 Reserved 0 WKUP_INT_CON24_31 5 22 20 Sets the signaling method for WKUP_INT 29 000 Reserved 19 Reserved 0 WKUP_INT_CON24_31 4 18 16 Sets the signaling method for WKUP_INT 28 000 Reserved 15 Reserved 0 WKUP_INT_CON24_31 3 14 12 Sets the signaling method for WKUP_INT 27 000 Reserved 11 Reserved 0 WK...

Page 140: ...es 1 enables 0 FLTSEL0_3 2 22 Filter Selection for WKUP_INT 2 0 delay filter 1 digital filter clock count 0 EINT0_3 2 21 16 Filtering width for WKUP_INT 2 This value is valid if FLTSEL0 is 1 000 FLTEN0_3 1 15 Filter Enable for WKUP_INT 1 0 disables 1 enables 0 FLTSEL0_3 1 14 Filter Selection for WKUP_INT 1 0 delay filter 1 digital filter clock count 0 EINT0_3 1 13 8 Filtering width for WKUP_INT 1 ...

Page 141: ...s 1 enables 0 FLTSEL4_7 6 22 Filter Selection for WKUP_INT 6 0 delay filter 1 digital filter clock count 0 EINT4_7 6 21 16 Filtering width for WKUP_INT 6 This value is valid if FLTSEL0 is 1 000 FLTEN4_7 5 15 Filter Enable for WKUP_INT 5 0 disables 1 enables 0 FLTSEL4_7 5 14 Filter Selection for WKUP_INT 5 0 delay filter 1 digital filter clock count 0 EINT4_7 5 13 8 Filtering width for WKUP_INT 5 T...

Page 142: ...es 1 enables 0 FLTSEL8_11 2 22 Filter Selection for WKUP_INT 10 0 delay filter 1 digital filter clock count 0 EINT8_11 2 21 16 Filtering width for WKUP_INT 10 This value is valid if FLTSEL1 is 1 000 FLTEN8_11 1 15 Filter Enable for WKUP_INT 9 0 disables 1 enables 0 FLTSEL8_11 1 14 Filter Selection for WKUP_INT 9 0 delay filter 1 digital filter clock count 0 EINT8_11 1 13 8 Filtering width for WKUP...

Page 143: ... enables 0 FLTSEL12_15 6 22 Filter Selection for WKUP_INT 14 0 delay filter 1 digital filter clock count 0 EINT12_15 6 21 16 Filtering width for WKUP_INT 14 This value is valid if FLTSEL1 is1 000 FLTEN12_15 5 15 Filter Enable for WKUP_INT 13 0 disables 1 enables 0 FLTSEL12_15 5 14 Filter Selection for WKUP_INT 13 0 delay filter 1 digital filter clock count 0 EINT12_15 5 13 8 Filtering width for WK...

Page 144: ...1 enables 0 FLTSEL16_19 2 22 Filter Selection for WKUP_INT 18 0 delay filter 1 digital filter clock count 0 EINT16_19 2 21 16 Filtering width for WKUP_INT 18 This value is valid if FLTSEL2 is1 000 FLTEN16_19 1 15 Filter Enable for WKUP_INT 17 0 disables 1 enables 0 FLTSEL16_19 1 14 Filter Selection for WKUP_INT 17 0 delay filter 1 digital filter clock count 0 EINT16_19 1 13 8 Filtering width for W...

Page 145: ...1 enables 0 FLTSEL20_23 6 22 Filter Selection for WKUP_INT 22 0 delay filter 1 digital filter clock count 0 EINT20_23 6 21 16 Filtering width for WKUP_INT 22 This value is valid if FLTSEL2 is1 000 FLTEN20_23 5 15 Filter Enable for WKUP_INT 21 0 disables 1 enables 0 FLTSEL20_23 5 14 Filter Selection for WKUP_INT 21 0 delay filter 1 digital filter clock count 0 EINT20_23 5 13 8 Filtering width for W...

Page 146: ...1 enables 0 FLTSEL24_27 2 22 Filter Selection for WKUP_INT 26 0 delay filter 1 digital filter clock count 0 EINT24_27 2 21 16 Filtering width for WKUP_INT 26 This value is valid if FLTSEL3 is1 000 FLTEN24_27 1 15 Filter Enable for WKUP_INT 25 0 disables 1 enables 0 FLTSEL24_27 1 14 Filter Selection for WKUP_INT 25 0 delay filter 1 digital filter clock count 0 EINT24_27 1 13 8 Filtering width for W...

Page 147: ...1 enables 0 FLTSEL28_31 6 22 Filter Selection for WKUP_INT 30 0 delay filter 1 digital filter clock count 0 EINT28_31 6 21 16 Filtering width for WKUP_INT 30 This value is valid if FLTSEL3 is1 000 FLTEN28_31 5 15 Filter Enable for WKUP_INT 29 0 disables 1 enables 0 FLTSEL28_31 5 14 Filter Selection for WKUP_INT 29 0 delay filter 1 digital filter clock count 0 EINT28_31 5 13 8 Filtering width for W...

Page 148: ...nabled 1 Masked n 0 7 1 5 6 16 Wake up Interrupt Mask Register24_31 WKUP_INT_MASK24_31 R W Address 0xE030_0F0C Field Bit Description Reset Value Reserved 31 8 Reserved 0 WKUP_INT_MASK24_31 n n Mask register for WKUP_INT n 24 0 Enabled 1 Masked n 0 7 1 5 6 17 Wake up Interrupt Pending Register0_7 WKUP_INT_PEND0_7 R W Address 0xE030_0F40 Field Bit Description Reset Value Reserved 31 8 Reserved 0 WKU...

Page 149: ...e Even though WKUP_INT_MASK24_31 n is masked this register can be pended 5 7 EXTERN PIN CONFIGURATION REGISTERS IN POWER DOWN MODE This registers keep their values during power down mode 5 7 1 Power Down Mode Pad Configure Register PDNEN R W Address 0xE030_0F80 Field Bit Description Reset Value Reserved 7 2 Reserved 0 PDNEN_CFG 1 0 Automatically by power down mode 1 by PDNEN bit 0 PDNEN 0 Power do...

Page 150: ...nables 0 USB_PUSW2 2 USB Pull up 2 switch2 control 0 off 1 on 0 USB_PUSW1 1 USB Pull up 1 switch1 control 0 off 1 on 0 USB_SUSPND 0 Make USB Tranceiver PAD to enter suspend mode 0 Normal mode 1 Suspend mode 0 NOTES 1 Pull up resistance is 1 2kohm Refer to figure 2 2 2 2 Pull up resistance is 0 5kohm Refer to figure 2 2 2 3 Pull down resistance is 20kohm Refer to figure 2 2 2 USB 1 0 Tranceiver Xus...

Page 151: ...and D1_BUS attached modules Final part D2 domain is for low power audio play D0 domain operates at up to 166MHz clock D1 domain operates at up to 133MHz D1 domain has many multimedia IPs which can be synthesized under 133MHz D2 domain operates at up to 80MHz All 3 parts communicate asynchronously Cortex A 8 DMA SECSS D0_BUS Memory File system D 0 domain up to 166MHz Muti media IPs D1_BUS APBs Asyn...

Page 152: ...PHY For more information on USB PHY clock refer to Section 7 8 Input frequency range 12 48MHz for supplying clock to USB PHY OSC_IN Clock from a crystal pad with XXTI and XXTO pins If USB is not used at commercial set CMU and PLL use this clock to generate clocks to modules Input frequency range 12 20MHz OSC27_IN Cock from 27MHz a crystal pad with XXTI27 and XXTO27 pins Clock doubler in CMU HPLL a...

Page 153: ..._XI A M E PLL HPLL HREF_ SEL SFR SYSTEM TIMER M U X SFR at system timer SYSTEM TIMER RTC clock CellGuide TSADC GPIO CHIPID TSADC KEYIF GPIO PADS D2_SS EPLL_ CLK to D2_SS EPLL_CLK ARMCLK HCLKD 0 PCLKD 0 HCLK PCLK SCLK_HDMI Clock Dobuler SCLK_27M SCLK_54M M U X CLK48M_ SEL SFR SCLK_48M IISCDCLK 0 1 2 PCMCDCLK 0 1 CAMCLK OUT AC97 PWM AC97 clock PAD ac_bit_clk PWM clock PAD pwm_eclk Figure 2 3 2 S5PC1...

Page 154: ...TV MIXER LCD and FIMC 2 2 CLOCKS FROM CMU CMU generates internal clocks with a various intermediate frequencies using clocks from the clock pads i e XXTI XXTI27 XrtcXTI and XusbXTI four PLLs i e APLL MPLL EPLL and HPLL and USB_OTG PHY clock Some of them are selected pre scaled and provided to the corresponding modules Products of AP typically use 12MHz as an input clock source of APLL MPLL and EPL...

Page 155: ...wing relationship D0 bus domain freq APLLCLK n x freq ARMCLK where n 2 8 10 12 14 16 Two cascaded divider DIV_APLL divide up to 2 DIV_ARM divide up to 8 freq ARMCLK n x freq HCLKD0 where n 1 8 freq PCLKD0 freq HCLKD0 n where n 1 8 freq HCLKD0_SECSS freq HCLKD0 n where n 1 8 freq SCLK_ONENAND freq HCLKD0 n where n 1 4 sync with D0 bus mode freq SCLK_ONENAND2 freq ONENANDCLK 2 sync with D0 bus mode ...

Page 156: ... HDMI clock 74 176MHz and 74 25MHz 4 1 EXAMPLE PLL PMS VALUE FOR PLL6522X APLL Table 2 3 1 APLL PMS Value FIN MHz Target FOUT MHz P M S VCOOUT FOUT MHz 12 133 3 266 3 1064 133 00 12 267 3 267 2 1068 267 00 12 400 3 400 2 1600 400 00 12 533 4 355 1 1065 532 50 12 667 3 333 1 1332 666 00 12 800 3 400 1 1600 800 00 12 933 4 622 1 1866 933 00 12 1066 3 267 0 1068 1068 00 12 1200 3 300 0 1200 1200 00 1...

Page 157: ...0 400 12 83 3 83 2 83 12 167 6 167 1 167 12 250 3 125 1 250 12 333 4 111 0 333 12 417 4 139 0 417 166 MHz 12 500 3 125 0 500 4 3 EXAMPLE PLL PMS VALUE FOR PLL6545A EPLL Table 2 3 3 EPLL PMS Value FIN MHz Target FOUT MHz P M S FOUT 12 48 0000 3 96 3 48 12 96 0000 3 96 2 96 12 144 0000 3 144 2 144 48M 12 192 0000 3 96 1 192 12 32 7680 3 131 4 32 75 12 45 1580 3 90 3 45 12 49 1520 4 131 3 49 125 12 6...

Page 158: ... 5 27 222 5275 6 99 1 222 75 27 296 7033 6 132 1 297 27 370 8791 11 151 0 370 636 27 445 0549 6 99 0 445 5 Video Clock for 74 25M or 74 176M 27 519 2308 9 173 0 519 27 146 2500 6 130 2 146 25 27 147 7500 9 197 2 147 25 5 CLOCK GENERATION Figure 2 3 3 shows a block diagram of the clock generation logic An external crystal clock is connected to the oscillation amplifier and the PLL converts the low ...

Page 159: ...S5PC100 USER S MANUAL REV1 0 CLOCK CONTROLLER 2 3 9 Figure 2 3 3 S5PC100 Clock Generation Circuit1 ...

Page 160: ... 4 S5PC100 Clock Generation Circuit2 Table 2 3 5 Bus Clock Domain for Each Module Bus clock domain Module D0 ARM DRAMC VIC0 VIC1 VIC2 TZIC0 TZIC1 TZIC2 M2M DMA G2D CFCON CS Core sight System SEC Security SS AES DES TDES SHA1 PRNG Secure JTAG and PKA IntMem Con SROMC ONENANDC NFCON EBI TZPC0 CHIPID D1 Peripheral DMA SDMMC0 SDMMC1 SDMMC2 USBHOST1 1 USB OTG MODEMIF LCD sub system CAMIF0 CAMIF1 CAMIF2...

Page 161: ... 2 Turn off a PLL A M E H PLL_SEL 0 De select the output of a PLL A M E H PLL_CON 31 0 Power off the PLL Must follow above procedure 1 2 3 Change PLL s PMS values Set PMS values Set PDIV MDIV and SDIV values Refer A M E H PLL_CON SFR 4 Change the system clock divider values CLK_DIV0 31 0 target value0 5 Change the divider values for special clocks CLK_DIV1 31 0 target value1 CLK_DIV2 31 0 target v...

Page 162: ..._D0_0 5 SCLK_ONENAND SCLK_ONENAND2 CLK_GATE_SCLK_0 2 HCLK CLK_GATE_D1_0 CLK_GATE_D1_1 CLK_GATE_D1_2 PCLK CLK_GATE_D1_3 CLK_GATE_D1_4 CLK_GATE_D1_5 Caution ARM clock setting Clock to ARM ARMCLK must be divided when using APLL It means that at least one of the ARM clock dividers DIVAPLL and DIVARM must be set to more than 1 Possible ARM clock division value 2 3 8 10 12 14 16 As shown in Figure 2 3 5...

Page 163: ...ection 7 10 Clock source of I2S is dependent to I2S mode If S5PC100 is operated as I2S master mode EPLL supplies I2S clock If S5PC100 is operated as I2S slave mode external I2S master supplies I2S clock Bus clocks HCLKD2 and PCLKD2 are asynchronous to I2S clock So you can freely select clock source for bus When LP Low Power Audio mode with top off is used SCLK_AUDIO0 must not be selected for I2SCL...

Page 164: ...Same as above SCLK_AUDIO2 I2S2 operation clock Same as above Same as above SCLK_SPDIF SPDIF operation clock Same as above SCLK_AUDIO 0 1 2 SCLK_SPIx SCLK_SPIx_48 SPI operation reference clock 50MHz 100MHz 2 SPI divides input clock CPAD E M H PLL SCLK_SPIx USB_48 SCLK_SPIx_48 Uart_eclk SCLK_UART UART operation reference clock 133MHz From UART PAD E M H PLL SCLK_UART SCLK_MMC 0 1 SCLK_MMC 0 1 _48 SD...

Page 165: ...OTG PHY CAM means Camera including CIS or CCD 7 4 MEMORY CLOCK Memory subsystem needs special clocks just for an OneNAND controller SCLK_ONENAND SCLK_ONENAND2 SCLK_ONENAND and SCLK_ONAND2 are OneNAND operational clocks These special clocks are synchronous to HCLKD0 when clock source of SCLK_ONENAND and SCLK_ONENAND2 is HCLKD0 If selected pin of MUX1nand is 0 OneNAND operates HCLKD0 synchronously I...

Page 166: ...00 gets 27MHz clock source to make 54MHz clock for SDTV out Internal clock doubler doubles 27MHz clock and then passes 54MHz clock to VDAC and TV out module HDMI needs 27 74 176 and 74 25 MHz clock 74 176 and 74 25MHz are usually made by HPLL HDMI PLL Figure 2 3 8 TV Clock ...

Page 167: ...t EPLLout SCLK_FIMC1 FIMC1 DCLK SCLK_FIMC2 FIMC2 DCLK HCLKD1 HCLKD1 HCLKD1 CLK54M HPLLout MPLLout EPLLout CLK54M HPLLout MPLLout EPLLout CLK54M HPLLout MPLLout EPLLout Figure 2 3 9 FIMD and FIMC clock FIMD LCD controller and three FIMCs Camera interface have many clock sources Figure 2 3 109 shows overall clock path and registers to set SCLK_FIMCn is the local interface clock between FIMCn and FIM...

Page 168: ...CLK_FIMC1 CLK_GATE_SCLK_1 2 SCLK_FIMC2 CLK_GATE_SCLK_1 3 SCLK_LCD CLK_GATE_SCLK_1 0 7 7 SECURE SUB SYSTEM CLOCK Modules in Secure Sub System Clock SECSS have long combinational paths because secure algorithm needs intensive computation Those modules use divided clock HCLKD0_SECSS derived from HCLKD0 for that long path HCLKD0_SECSS must not be higher than 83MHz AES DES TDES SHA1 PRNG Secure JTAG PK...

Page 169: ...48MHz clock and IrDA USB HOST1 1 needs exact 48MHz clock S5PC100 supplies this clock from XusbXTI when using 48MHz crystal or OSC or output of OTG PHY or PLL Figure 2 3 11 USB PHY and 48MHz clock 7 9 D2_SS CLOCK DOMAIN For more information on Audio CMU in Figure 2 3 12 refer to Section 7 2 Audio CMU Sync Bridge HCLKD2 AHB I2S V5 0 SRAM PCLK_IIS0 from SYSCON I2SCLKD2 D2_SS HCLK_FIMC0 from SYSCON HC...

Page 170: ...z MUXHPLL 1 0 MUXHREF 0 1 MOUTHPLL CLK_SRC0 0 CLK_DIV1 2 0 CLK_SRC0 4 CLK_SRC0 16 CLK_SRC0 20 CLK_SRC0 12 CLK_DIV1 5 4 CLK_SRC0 8 MUXAUDIO0 CLK_SRC3 14 12 MUXAUDIO1 CLK_SRC3 18 16 MUXAUDIO2 CLK_SRC3 22 20 MUXSPDIF CLK_SRC3 25 24 DIVAUDIO0 CLK_DIV4 15 12 DIVAUDIO1 CLK_DIV4 19 16 DIVAUDIO2 CLK_DIV4 23 20 SCLK_AUDIO1 SCLK_AUDIO0 SCLK_AUDIO2 Figure 2 3 13 Clock source for audio peripherals SCLK_AUDIO0...

Page 171: ...clock for high speed transmission with meeting tight jitter spec Input clock for that PLL is TV reference clock 27MHz 7 12 PERIPHERAL S5PC100x has many kinds of peripherals to communicate with external device such as USB MMC UART and etc Figure 2 3 14 shows clock control path of peripherals Figure 2 3 14 Peripheral Clock ...

Page 172: ..._GATE_SCLK_0 5 CLK_GATE_SCLK_0 6 SCLK_UART CLK_GATE_SCLK_0 3 SCLK_MMC0 SCLK_MMC1 SCLK_MMC2 CLK_GATE_SCLK_0 12 CLK_GATE_SCLK_0 13 CLK_GATE_SCLK_0 14 SCLK_IRDA CLK_GATE_SCLK_0 10 SCLK_PWI CLK_GATE_SCLK_0 1 SCLK_USBHOST CLK_GATE_SCLK_0 11 SCLK_MMC0_48 SCLK_MMC1_48 SCLK_MMC2_48 CLK_GATE_SCLK_0 15 CLK_GATE_SCLK_0 16 CLK_GATE_SCLK_0 17 SCLK_SPI0_48 SCLK_SPI1_48 SCLK_SPI2_48 CLK_GATE_SCLK_0 7 CLK_GATE_SC...

Page 173: ...ER STRENGTH OF OSCILLATOR PAD Driver strength of oscillation pads XT XT_USB and XT_27M must be set rightly according to input frequency DRV value Output Freq 2 b00 Driver X1 32kHz 1MHz 2 b01 Driver X2 1MHz 15MHz 2 b10 Driver X3 15MHz 30MHz 2 b11 Driver X4 30MHz 50MHz To get more information refer to ETC4DRV SFR in 02 02 S5PC100_GPIO 8 2 CRYSTAL OSCILLATOR DESIGN CONSIDERATION The external componen...

Page 174: ...CLOCK CONTROLLER S5PC100 USER S MANUAL REV1 0 2 3 24 Rs 0ohm Rf 1Mohm CL 10 35pF ...

Page 175: ...trol PLL output frequency for MPLL 0x0085_0302 EPLL_CON 0xE010_0108 R W Control PLL output frequency for EPLL 0x0085_0302 HPLL_CON 0xE010_010C R W Control PLL output frequency for HPLL 0x0085_0302 Reserved 0xE010_0110 0xE010_01FC Reserved 0x0000_0000 1 3 Clock source 0xE010_0200 CLK_SRC0 0xE010_0200 R W Select clock source 0 Main 0x0000_0000 CLK_SRC1 0xE010_0204 R W Select clock source 1 Connectiv...

Page 176: ...e 0x0000_00FF CLK_GATE_D1_1 0xE010_0524 R W Control HCLKD1 PCLKD1 clock gating 1 Multimedia1 0x0000_01FF CLK_GATE_D1_2 0xE010_0528 R W Control HCLKD1 PCLKD1 clock gating 2 Multimedia2 0x0000_001F CLK_GATE_D1_3 0xE010_052C R W Control HCLKD1 PCLKD1 clock gating 1 System 0x0000_03FF CLK_GATE_D1_4 0xE010_0530 R W Control HCLKD1 PCLKD1 clock gating 2 Connectivity 0x0000_3FFF CLK_GATE_D1_5 0xE010_0534 ...

Page 177: ...xE020_0300 R W Camera mapping to FIMC selection 0x0000_0000 MIXER_OUT_SEL 0xE020_0304 R W Video Mixer output to TVENC HDMI selection 0x0000_0000 LPMP3_MODE_SEL 0xE020_0308 R W Low power MP3 mode selection 0x0000_0000 Reserved 0xE020_030C 0xE020_03FC R W Reserved 0x0000_0000 2 5 Test registers 0xE020_0400 MIPI_PHY_CON0 0xE020_0400 R W MIPI D PHY control register0 0x0000_0000 Reserved 0xE020_0404 0x...

Page 178: ...ess 0xE010_000C RESERVED RESERVED Address 0xE010_0010 0xE010_00FC A PLL requires locking period if input frequency is changed or frequency division multiplication values are changed PLL_LOCK register specifies this locking period which is based on PLL s source clock During this period PLL output will be masked with 0 APLL_LOCK MPLL_LOCK EPLL_LOCK HPLL_LOCK Bit Description Reset Value Reserved 31 1...

Page 179: ...time locking time is set at PLL_LOCK SFR 0 Reserved 29 26 Reserved 0 MDIV 25 16 PLL M divide value 0x190 Reserved 15 14 Reserved 0 PDIV 13 8 PLL P divide value 0x3 Reserved 7 3 Reserved 0 SDIV 2 0 PLL S divide value 0x2 The reset value of APLL_CON generates 400MHz output clock respectively if the input clock frequency is 12MHz NOTE The output frequency is calculated by the following equation FOUT ...

Page 180: ...er locking time locking time is set at PLL_LOCK SFR 0 RESERVED 29 24 Do not change 0 MDIV 23 16 PLL M divide value 0x85 Reserved 15 14 Reserved 0 PDIV 13 8 PLL P divide value 0x3 Reserved 7 3 Reserved 0 SDIV 2 0 PLL S divide value 0x2 The reset value of MPLL_CON EPLL_CON and HPLL_CON generates 133MHz output clock respectively if the input clock frequency is 12MHz NOTE The output frequency is calcu...

Page 181: ...clock source register CLK_SRC0 Bit Description Reset Value Reserved 31 25 Reserved ONENAND_SEL 24 Control MUX1NAND 0 HCLKD0 1 HCLKD1 0x0 Reserved 23 21 Reserved HREF_SEL 20 Control MUXHREF 0 FIN27M 1 SRCLK 0 Reserved 19 17 Reserved AMMUX_SEL 16 Control MUXAM 0 MOUTMPLL 1 DOUTAPLL2 0x0 Reserved 15 13 Reserved HPLLSEL 12 Control MUXHPLL 0 CLK27M 1 FOUTHPLL 0x0 Reserved 11 9 Reserved EPLL_SEL 8 Contr...

Page 182: ... 0x0 Reserved 19 18 Reserved IRDA_SEL 17 16 Control MUXIRDA which is the source clock of IRDA 00 MOUTEPLL 01 DOUTMPLL 10 MOUTHPLL 11 48MHz 0x0 Reserved 15 14 Reserved SPI2_SEL 13 12 Control MUXSPI2 which is the source clock of SPI2 00 MOUTEPLL 01 DOUTMPLL2 10 FINEPLL 11 MOUTHPLL 0x0 Reserved 11 10 Reserved SPI1_SEL 9 8 Control MUXSPI1 which is the source clock of SPI1 00 MOUTEPLL 01 DOUTMPLL2 10 F...

Page 183: ...UTMPLL 10 MOUTHPLL 11 VCLK_54 0x0 Reserved 19 18 Reserved FIMC0_SEL 17 16 Control MUXFIMC0 which is the source clock of FIMC0 00 MOUTEPLL 01 DOUTMPLL 10 MOUTHPLL 11 VCLK_54 0x0 Reserved 15 14 Reserved LCD_SEL 13 12 Control MUXLCD which is the source clock of LCD 00 MOUTEPLL 01 DOUTMPLL 10 MOUTHPLL 11 VCLK_54 0x0 Reserved 11 10 Reserved MMC2_SEL 9 8 Control MUXMMC2 which is the source clock of MMC2...

Page 184: ...h is the source clock of I2S1 PCM1 000 MOUTEPLL 001 DOUTMPLL 010 FINEPLL 011 I2SCDCLK1 100 PCMCDCLK1 101 MOUTHPLL 0x0 Reserved 15 Reserved AUDIO0_SEL 14 12 Control MUXAUDIO0 which is the source clock of I2S0 PCM0 000 MOUTEPLL 001 DOUTMPLL 010 FINEPLL 011 I2SCDCLK0 100 PCMCDCLK0 101 MOUTHPLL 0x0 Reserved 11 10 Reserved I2S_D2_SEL 9 8 Control MUXI2S_D2 00 FOUTEPLL 01 I2SCDCLK0 10 SCLK_AUDIO0 When LP...

Page 185: ...main divider CLK_DIV0 Bit Description Reset Value Reserved 31 19 Reserved SECSS_RATIO 18 16 DIVSECSS clock divider ratio HCLKD0_SECSS DOUTD0_BUS RATIO RATIO SECSS_RATIO 1 SECSS Secure Sub System operating clock cannot exceed 83MHz 0x1 Reserved 15 Reserved PCLKD0_RATIO 14 12 DIVPCLKD0 clock divider ratio PCLKD0 HCLKD0 RATIO RATIO PCLKD0_RATIO 1 0x1 Reserved 11 Reserved DO_BUS_RATIO 10 8 DIVD0_BUS c...

Page 186: ...IO RATIO ONENAND_RATIO 1 0x0 Reserved 19 Reserved PCLKD1_RATIO 18 16 DIVPCLK clock divider ratio PCLK DOUTD1_BUS RATIO RATIO PCLK_RATIO 1 0x1 Reserved 15 Reserved D1_BUS_RATIO 14 12 DIVD1_BUS clock divider ratio DOUTD1_BUS MOUTAMPLL RATIO RATIO D1_BUS_RATIO 1 0x0 Reserved 11 9 Reserved MPLL2_RATIO 8 DIVMPLL2 clock divider ratio DOUTMPLL2 MOUTAMPLL RATIO RATIO MPLL2_RATIO 1 0x0 Reserved 7 6 Reserve...

Page 187: ...N RATIO RATIO UART_RATIO 1 0x0 10 3 4 Set Clock Divider Ratio 3 Multimedia and Connectivity CLK_DIV3 R W Address 0xE010_030C Multimedia and connectivity divider CLK_DIV3 Bit Description Reset Value HDMI_RATIO 31 28 DIVHDMI clock divider ratio CLKHDMI CLKHDMIIN RATIO RATIO HDMI_RATIO 1 0x0 FIMC2_RATIO 27 24 DIVFIMC2 clock divider ratio CLKFIMC2 CLKFIMC2IN RATIO RATIO FIMC2_RATIO 1 0x0 FIMC1_RATIO 2...

Page 188: ...UDIO1_RATIO 19 16 DIVAUDIO1 clock divider ratio CLKAUDIO1 CLKAUDIO1IN RATIO RATIO AUDIO1_RATIO 1 0x0 AUDIO0_RATIO 15 12 DIVAUDIO0 clock divider ratio CLKAUDIO0 CLKAUDIO0IN RATIO RATIO AUDIO0_RATIO 1 0x0 I2S_D2_RATIO 11 8 DIVI2S_D2 clock divider ratio CLKI2SD2 I2SD2MUX RATIO RATIO I2S_D2_RATIO 1 0x0 Reserved 7 Reserved 0x0 HCLK_D2_RATIO 6 4 DIVHCLK_D2 clock divider ratio HCLKD2 HCLKD2MUX RATIO RATI...

Page 189: ... 1 0x0 Reserved 19 17 Reserved 0x000 00000 FOUTAPLL 4 0x0 00001 FOUTMPLL 00010 FOUTEPLL 00011 FOUTHPLL 00100 HCLKD1 00101 HCLKD0 00110 PCLKD1 00111 PCLKD0 01000 HCLKD2 01001 ARMCLK 4 01010 RTC clock from PAD 01011 RTC tick 01100 CLK48M 01101 CLK27M 01110 CLK30M 01111 VCLK_54 CLKSEL 16 12 10000 DOUT DCLKCMP 11 8 This field changes the clock duty of DCLK Thus it must be smaller than DCLKDIV It is va...

Page 190: ...HCLK for G2D 0 Mask 1 Pass 1 CLK_MDMA 3 Gating HCLK PCLKEN for MDMA 0 Mask 1 Pass 1 CLK_CFCON 2 Gating HCLK for CFCON 0 Mask 1 Pass 1 CLK_TZIC 1 Gating HCLK for trust interrupt controller 0 Mask 1 Pass 1 CLK_INTC 0 Gating HCLK for vectored interrupt controller 0 Mask 1 Pass 1 10 5 2 Control HCLKD0 PCLKD0 Clock Gating 1 Memory CLK_GATE_D0_1 R W Address 0xE010_0504 D0 domain memory clock gating CLK_...

Page 191: ...C0 0 Mask 1 Pass 1 CLK_MODEMIF 4 Gating HCLK for MODEM interface 0 Mask 1 Pass 1 CLK_USBOTG 3 Gating HCLK for USB OTG 0 Mask 1 Pass 1 CLK_USBHOST 2 Gating HCLK for UHOST 1 1 0 Mask 1 Pass 1 CLK_PDMA1 1 Gating HCLK PCLKEN for PDMA1 0 Mask 1 Pass 1 CLK_PDMA0 0 Gating HCLK PCLKEN for PDMA0 0 Mask 1 Pass 1 10 5 6 Control HCLKD1 PCLKD1 Clock Gating 1 Multimedia1 CLK_GATE_D1_1 R W Address 0xE010_0524 D1...

Page 192: ...k 1 Pass 1 10 5 8 Control HCLKD1 PCLKD1 Clock Gating 1 System CLK_GATE_D1_3 R W Address 0xE010_052C D1 domain system control clock gating CLK_GATE_D1_3 Bit Description Reset Value Reserved 31 10 Reserved 0 CLK_RTC 9 Gating PCLK for RTC 0 Mask 1 Pass 1 CLK_WDT 8 Gating PCLK for watch dog timer 0 Mask 1 Pass 1 CLK_SYSTIMER 7 Gating PCLK for system timer 0 Mask 1 Pass 1 CLK_PWM 6 Gating PCLK for PWM ...

Page 193: ...CAN1 11 Gating PCLK for CCAN1 0 mask 1 pass 1 CLK_CCAN0 10 Gating PCLK for CCAN0 0 mask 1 pass 1 CLK_IRDA 9 Gating PCLK for IRDA 0 mask 1 pass 1 CLK_SPI2 8 Gating PCLK for SPI2 0 mask 1 pass 1 CLK_SPI1 7 Gating PCLK for SPI1 0 mask 1 pass 1 CLK_SPI0 6 Gating PCLK for SPI0 0 mask 1 pass 1 CLK_HDMI_IIC 5 Gating PCLK for IIC for HDMI 0 mask 1 pass 1 CLK_IIC 4 Gating PCLK for IIC 0 mask 1 pass 1 CLK_U...

Page 194: ... mask 1 pass 1 CLK_PCM0 4 Gating PCLK for PCM0 0 mask 1 pass 1 CLK_AC97 3 Gating PCLK for AC97 0 mask 1 pass 1 CLK_I2S2 2 Gating PCLK for I2S2 0 mask 1 pass 1 CLK_I2S1 1 Gating PCLK for I2S1 0 mask 1 pass 1 CLK_I2S0 0 Gating PCLK for I2S0 in D2_SS 0 mask 1 pass 1 10 5 11 Reserved Reserved Address 0xE010_0538 0xE010_053C 10 5 12 Control HCLKD2 Clock Gating 0 Audio CLK_GATE_D2_0 R W Address 0xE010_0...

Page 195: ...special clock for MMC0 0 mask 1 pass 1 SCLK_USBHOST 11 Gating special clock for UHOST1 1 0 mask 1 pass 1 SCLK_IRDA 10 Gating special clock for IRDA 0 mask 1 pass 1 SCLK_SPI2_48 9 Gating special clock 48MHz for SPI2 0 mask 1 pass 1 SCLK_SPI1_48 8 Gating special clock 48MHz for SPI1 0 mask 1 pass 1 SCLK_SPI0_48 7 Gating special clock 48MHz for SPI0 0 mask 1 pass 1 SCLK_SPI2 6 Gating special clock fo...

Page 196: ... mask 1 pass 1 SCLK_TV54 4 Gating special clock for TV encoder 0 mask 1 pass 1 SCLK_FIMC2 3 Gating special clock for FIMC2 0 mask 1 pass 1 SCLK_FIMC1 2 Gating special clock for FIMC1 0 mask 1 pass 1 SCLK_FIMC0 1 Gating special clock for FIMC0 0 mask 1 pass 1 SCLK_LCD 0 Gating special clock for LCD controller 0 mask 1 pass 1 10 6 OTHER SFRS 10 6 1 Generate Software Reset SWRESET R W Address 0xE020_...

Page 197: ...r not in standby mode 1 Processor in standby mode 1 b0 Reserved 0 Do not change this value 1 b0 10 6 5 ENDIAN EBI Configuration MEM_SYS_CFG R W Address 0xE020_0200 MEM_SYS_CFG Bit Description Reset Value Reserved 31 9 Reserved 0 EBI_PRI 8 Set EBI priority scheme 0 Fixed priority scheme 1 Circular priority scheme 0 Reserved 7 6 Reserved EBI_FIX_PRI 5 4 Set EBI fixed priority setting 0 SROMC OneNAND...

Page 198: ... 0 TVENC 1 HDMI 0x0 10 6 8 Low Power MP3 Mode Selection LPMP3_MODE_SEL R W Address 0xE020_0308 LPMP3_MODE_SEL Bit Description Reset Value Reserved 31 2 Reserved 0x0 I2S0_FIFO_CLK_SEL 1 I2S0 in D2_SS operation clock selection 0 I2S0 bit clock from AUDIO CMU in D2_SS 1 PCLK from D1_SS 0x0 LPMP3_MODE_SEL 0 Rotator memory demuxing selection 0 FIMC 1 LPAUDIO 0x0 10 6 9 MIPI D PHY Control Register0 MIPI...

Page 199: ...ccording to M_DPDN_SWAP S_DPDN_SWAP 0x0 Reserved 26 Do not change this value 0x0 M_DPDN_SWAP 25 This is to prevent crossing PCB trace lines of DP DN if the master lane is connected to a slave lane on PCB board If it is set to HIGH all the Master s DP DN signals are swapped This is used for MIPI DSI 0x0 S_DPDN_SWAP 24 Slave PPI I F signal This is to prevent crossing PCB trace lines of DP DN if the ...

Page 200: ...for low power MP3 playback STOP All the blocks including the CPU core are clock off except the RTC and Alive domain The state of sub power domain power off domain in NORMAL mode is still power off in STOP mode The Stop mode should be used for test purpose only DEEP STOP CPU core is power off and the remaining parts of the chip except RTC and ALIVE can have different configurations according to Top...

Page 201: ...e of SRAM ROM PLL TS ADC and I O The power mode of hard macros except SRAM ROM PLL TS ADC and I O should be controlled by corresponding control module Note that in addition to Power Management Unit PMU below Clock Controller CLKCON below also controls the PLL According to application scenario above mentioned proper system power mode should be applied and hard macro should be controlled ...

Page 202: ...roller is used to disable clock to a specific IP module These clock gating cells are controlled by setting registers CLK_GATE_D0_0 2 CLK_GATE_D1_0 5 and CLK_GATE_SCLK_0 1 in Clock Controller If clock off is applied power to logic gate is still supplied and therefore the states of Normal F F Flip Flop and Retention F F are maintained Retention F F is developed to meet special purpose to keep its st...

Page 203: ...tes and memory in SUB domains except System Timer domain are turned ON at the same time But to prevent wakeup noise from occurring the power to switches is supplied in two steps in similar with first technique Power to about 10 switches of all is supplied first and the power of remaining 90 switched is supplied after some time goes This is automatically done by hardware logic The power up time is ...

Page 204: ... PLL TS ADC and I O are controlled by power management The power mode of hard macros except SRAM ROM PLL TS ADC and I O should be controlled by corresponding control module Note that in addition to PMU CLKCON also controls the PLL Table 2 4 2 S5PC100 Power Domains Power Domain Included Modules 1 CPU Cortex A8 Core L2 Cache ETM NEON 2 MFC MFC 3 G3D G3D 4 Audio Sub system Audio related modules I2S0 ...

Page 205: ...nimized There are two options in DEEP IDLE mode One option is that the remaining parts of the chip keep their states in NORMAL mode Second option is that for low power MP3 playback Top domain is power off and Sub domain except Audio domain is power off whereas Audio domain is still power on Set TOP_LOGIC_ON_DIDLE field of PWR_CFG register in PMU to select the above mentioned options i e TOP domain...

Page 206: ...ctively Disabled XXTI enabled XXTI 10 cycles 7 XXTI 6 cycles XXTI 1424 cycles 8 XXTI 30 cycles 300 us 9 XXTI 926 cycles 300 us or XXTI 1688 cycles10 Typical wakeup time 6 XXTI disabled N A N A N A 1 3 ms12 XXTI 896 cycles 1 3ms or XXTI 1688 cycles 1ms13 XXTI 138 cycles 5ms 11 1 IEM means Intelligent Energy Management introduced by ARM IEM is explained in detail separately in IEM related TRM Techni...

Page 207: ...disabled by hardware and OSCs are selectively disabled by setting OSC_EN field of STOP_CFG and SLEEP_CFG register in PMU 3 2 NORMAL MODE In NORMAL mode clock off power off and frequency scaling are used for power saving Clock off is done in module by module basis Disable the clock of one or more modules by setting the corresponding bits in the clock on off control registers CLK_GATE_D0_0 2 CLK_GAT...

Page 208: ...ered off modules are still power off To enter IDLE mode 1 Set CFG_STANDBYWFI field of PWR_CFG to 2 b01 2 Set DEEP field register in CFG_DEEP_IDLE field of PWR_CFG to 1 b0 3 Set PMU_INT_DISABLE bit of OTHERS register to 1 b1 to prevent interrupts from occurring while entering IDLE mode 4 Execute Wait For Interrupt instruction WFI To exit IDLE mode 1 Various types of wakeup sources are used Wakeup s...

Page 209: ...ile entering DEEP IDLE mode 4 Execute Wait for Interrupt instruction WFI PMU performs the following sequence on entering the DEEP IDLE mode TOP_LOGIC_ON_DIDLE 1 b0 This sequence is automatically done by hardware logic 1 Completes all active bus transactions 2 Completes all active memory controller transactions 3 Initiates external DRAM to enter self refresh mode to preserve DRAM contents 4 Mask cl...

Page 210: ...PB_D0 0xE300_0000 MIPI HSI TX 0xEC90_0000 APB_B0 0xE310_0000 MIPI HSI RX 0xECA0_0000 APB_C0 0xE320_0000 MIPI DSI 0xECB0_0000 APB_MEM 0xE330_0000 MIPI CSI 0xECC0_0000 APB_ASYNCBR 0xE340_0000 Modem Interface 0xED50_0000 TZPC0 0xE380_0000 SPDIF 0xF260_0000 VIC0 0xE400_0000 ADC Touch 0xF300_0000 VIC1 0xE410_0000 Key Pad 0xF310_0000 VIC2 0xE420_0000 AHB_RX 0xF400_0000 TZIC0 0xE500_0000 AHB_TX 0xF410_00...

Page 211: ... mode clock to modules except RTC and ALIVE module is disabled PLLs are disabled and unnecessary oscillators are selectively disabled so that dynamic power consumption is minimized In this mode Cortex A8 Core enters into Standby mode Therefore current application program that was running in NORMAL mode stops in STOP mode and waits for wakeup event to resume To enter STOP mode 1 Set CFG_STANDBYWFI ...

Page 212: ...n TOP_LOGIC_ON 1 b0 Top domain is power off If TOP_LOGIC_ON_DIDLE 1 b0 some IP modules in Top domain loses their states in F F and the other IP modules keeps their states in F F after wakeup IP modules in Top domain shown in Table 2 4 4 have retention F Fs and those modules will keep their states in F F after wakeup Therefore IP modules that do not keep their states in F F in DEEP STOP mode Top do...

Page 213: ...are selectively disabled Since the external regulator becomes off using control signal from S5PC100 you should consider waiting time for the regulator stabilization in the SLEEP mode wake up using PWR_STABLE register To enter SLEEP mode 1 Set NORMAL_CFG 5 to 1 b0 so that Audio domain becomes power off to prevent current leakage from occurring in I2S0 related I O pad Xi2s0CDCLK Xi2s0LRCK Xi2s0SCLK ...

Page 214: ...gister setting since normal F F lost information due to power gating 2 S W sets IO_RET_RELEASE bit of OTHERS register to 1 b1 to release retention for I O pad 3 S W sets PLL initial setting P M S value 4 S W sets to Enable the PLLs and wait for locking about 300us 5 S W sets initialization configurations in LPCON DRAM controller to access to from DRAM Since all modules are powered off and their st...

Page 215: ...SER S MANUAL REV1 0 2 4 16 4 SYSTEM POWER MODE TRANSITION Figure 2 4 2 shows the power mode transition diagram Figure 2 4 2 Power Mode Transition Diagram The wakeup sources described in Figure 2 4 2 are summarized in Table 2 4 6 ...

Page 216: ... PWR_CFG 1 b1 4 PMU_INT_DISABLE in OTHERS 1 b1 5 ARM Command WFI 1 All interrupt sources DEEP IDLE Top domain off 1 CFG_STANDBYWFI in PWR_CFG 2 b01 2 CFG_DEEP_IDLE in PWR_CFG 1 b1 3 TOP_LOGIC_ON_DIDLE in PWR_CFG 1 b0 4 PMU_INT_DISABLE in OTHERS 1 b1 5 ARM Command WFI 1 nBATF 1 2 External Interrupt 3 RTC Alarm 4 RTC TICK 5 Key Pad Press event 6 HSI interface RX 7 Modem I F Wake up event 8 MMC0 2 9 ...

Page 217: ...m 3 RTC TICK 4 Key Pad Press event 1 nBATF Low Battery Interrupt from XnBATF pad 2 Basically E SLEEP mode is the same as SLEEP mode but we distinguish E SLEEP mode from SLEEP mode in that entering condition and wakeup sources are different The Wake up Event Source for E SLEEP mode can be optionally limited to be just none or it can be any of those listed in the above table See PWR_CFG register s C...

Page 218: ...NAL INTERRUPTS All internal interrupts are wakeup sources in IDLE or DEEP_IDLE Top domain on mode 5 2 EXTERNAL INTERRUPTS External interrupts are the common wake up source of all power down modes The logic for external interrupt configuration such as polarity edge level sensitivity and masking resides in the GPIO and can be modified through GPIO register setting before entering one of power down m...

Page 219: ...often If the PWM timer generates an interrupt at various interval using one shot mode but it accumulates the timing inaccuracy since it cannot count time during manual setting and therefore it cannot generate accurate 1ms timing tick to be used for OS operation In DEEP IDLE STOP and DEEP STOP mode there is no system clock if Top domain is power off Therefore RTC is used for generating timing tick ...

Page 220: ...nal power off 6 PLL 6 PMU CLKCON Run Power down Keep power state in NORMAL Power down External power off 7 DAC 6 TV Encoder logic Run Power down Keep power state in NORMAL Power down External power off 8 TS ADC 6 PMU Run Stand by Stand by External power off Internal power off 9 Digital I O PMU Power on Power on Power on Power on 1 External power to USB OTG phy HDMI phy MIPI D phy and DAC can be of...

Page 221: ...retention or power down mode Before entry to this mode you must set the TOP_MEMORY_ON_DIDLE and TOP_MEMORY_RET_ON_DIDLE field PWR_CFG in PMU In STOP mode and DEEP STOP mode stand by retention and power down mode can be entered Before entry to STOP mode you must set the TOP_MEMORY_ON and TOP_MEMORY_RET field of STOP_CFG register in PMU to determine which power mode SRAM enters during STOP mode And ...

Page 222: ...gure 2 4 3 Power Up Sequence of USB OTG Phy USB OTG phy has three power modes Run IDLE and Suspend mode In Run mode USB OTG phy sends and receives data normally In IDLE mode there is no data transaction to and from USB OTG phy But the clock is still supplied to USB OTG phy In Suspend mode USB OTG phy clock is off to save power ...

Page 223: ...s and receives data normally In Power down mode all power to HDMI phy is off internally In NORMAL mode both the power modes can be used If HDMI phy is in use then it is in Run mode If HDMI phy is not in use it can enter into Power down mode to save static power by setting register in HDMI link In IDLE mode and DEEP IDLE mode top domain on HDMI phy keeps its operation or power state in NORMAL Befor...

Page 224: ...ogic power Therefore power down mode of PLL in SLEEP mode has no meaning 6 6 1 Status of PLL after Wake Up Event The behaviors of PLLs APLL MPLL HPLL EPLL after wakeup from various power down modes are different Table 2 4 9 shows the states of PLLs and HCLK after wake up from the power saving modes During IDLE mode and DEEP IDLE mode top domain on PLLs APLL MPLL HPLL are running normally by the sa...

Page 225: ...changed PLL Output DEEP IDLE Top domain on unchanged unchanged PLL Output DEEP IDLE Top domain off off off unchanged PLL reference clock STOP off on by H W off on by H W PLL Output DEEP STOP Top domain on off on by H W off on by H W PLL Output DEEP STOP Top domain off off off off off PLL reference clock SLEEP off off off off PLL reference clock 6 7 DAC DAC has two power modes Run and Power down mo...

Page 226: ...ain off all normal I Os do not work In SLEEP mode normal I O does not work since internal power to normal I O is off but alive I O always works since power to alive I O is always on Nontheless I O power to normal I O should be supplied such as VDDQ_DDR VDDQ_M0 VDDQ_LCD VDDQ_CI VDDQ_MMC VDDQ_AUD VDDQ_MSM VDDQ_SYS0 VDDQ_SYS2 VDDQ_SYS5 VDDQ_CAN VDDQ_EXT VDDQ_RTC VDDQ_UH Table 2 4 10 List of Alive I O...

Page 227: ... by hardware to access to from memory GPIO setting should be done before the other retention signals are released RET_EN1 and RET_LPA are released by setting IO_RET_RELEASE 31 in OTHERS register to 1 b1 and RET_SDMMC are released by setting SDMMC_IO_RET_RELEASE 22 in OTHERS register to 1 b1 Table 2 4 11 Retention control signals and Related Digital I O 1 Retention Control Signal Released by Relate...

Page 228: ... after wakeup reset to top domain is released RET_EN0 internal nSCALL_BLK_TOP internal By setting IO_RET_RELEASE 31 in OTHERS register CPGI internal RET_EN1 internal RET_LPA internal RET_SDMMC internal By setting SDMMC_IO_RET_RELEASE 22 in OTHERS register GPIO setting is lost due to power gating GPIO setting should be done before setting IO_RET_RELEASE 31 and SDMMC_IO_RET_RELEASE 22 Automatically ...

Page 229: ...enough power level to the S5PC100 Internal PLLs become disabled after power turns on XnRESET signal should be released after the fully settle down of the power supply level For the proper system operation the S5PC100 requires a hazard free system clock ARMCLK HCLK and PCLK when the system reset is released XnRESET However since PLLs are disabled Fin the direct external oscillator clock is fed dire...

Page 230: ...LIVE to VDD_INT ARM PLL 1 us tLP VDD_INT ARM PLL to VDD_IO 1 ns tOSC VDD_INT VDD_ARM to Oscillator stabilization 10 cycle 1 tOR Oscillator stabilization to nRESET nTRST high 1 us tPLL PLL locking time 300 us NOTE 1 The user should be aware that the crystal oscillator settle down time is not explicitly added by the hardware during the power on sequence The S5PC100 assumes that the crystal oscillati...

Page 231: ...T VDD_ARM to Oscillator stabilization tOSC 10 cycle Oscillator stabilization to nRESET nTRST high tOR 1 us External clock input high level pulse width tEXTHIGH 25 ns External clock to HCLK without PLL tEX2HC 5 10 ns HCLK internal to CLKOUT tHC2CK 4 10 ns HCLK internal to SCLK tHC2SCLK 2 8 ns Reset assert time after clock stabilization tRESW 4 XTIpll or EXTCLK APLL MPLL Lock Time tPLL 300 us EPLL L...

Page 232: ...lways applicable Upon assertion of XnRESET S5PC100 enters into reset state regardless of the previous state For hardware reset to be asserted actually XnRESET must be held long enough to allow internal stabilization and propagation of the reset state Table 2 4 14 lists up pin names that should be supplied during reset Table 2 4 14 List of Power Pin Names supplied during reset Power Pin Names suppl...

Page 233: ...tware reset If Software reset is asserted the following sequence occurs 1 PMU requests AXI masters and AHB to AXI bridges to finish current transactions 2 Bus controller send acknowledge to PMU after completed bus transactions 3 PMU request memory controller to enter self refresh mode 4 PMU waits for self refresh acknowledge from memory controller 5 Internal reset signals and XnRSTOUT are asserted...

Page 234: ...s asserted during watchdog reset Watchdog reset is activated in NORMAL IDLE DEEP IDLE Top domain on mode because watchdog timer expires with clock Watchdog reset is asserted when watchdog timer and reset are enabled WTCON 5 1 WTCON 0 1 and watchdog timer is expired Watchdog reset is asserted then the following sequence occurs 1 Watchdog Timer WDT generates time out signal 2 PMU invokes reset signa...

Page 235: ...a sub domain that becomes power on after exiting from DEEP IDLE and DEEP STOP mode Finally wakeup reset is asserted when the system is waked up from sleep mode by wakeup event The exact timing diagram for wakeup reset is shown in Figure 2 4 11 for DEEP IDLE mode top domain off Figure 2 4 14 for DEEP STOP mode top domain off and Figure 2 4 15 for SLEEP mode In these cases XnRSTOUT is asserted when ...

Page 236: ...3_PAD_OUT GPH0_PAD_EN GPH1_PAD_EN GPH2_PAD_EN GPH3_PAD_EN GPH0_PAD_CPU GPH1_PAD_CPU GPH2_PAD_CPU GPH3_PAD_CPU GPH0_PAD_CPD GPH1_PAD_CPD GPH2_PAD_CPD GPH3_PAD_CPD GPH0_PAD_DRV GPH1_PAD_DRV GPH2_PAD_DRV GPH3_PAD_DRV O X O O Others O O O O 1 Unlike INFORM0 3 registers INFORM4 7 registers keep their values as long as alive power is supplied ...

Page 237: ...bled for reducing dynamic power in ARM CPU When wakeup event is asserted ARMCLK_OFF signal is released and then ARMCLK is supplied for ARM CPU within XXTI 6 cycles After ARMCLK is supplied CPU operation begins normally APLL clock out ARMCLK _ OFF internal ARMCLK internal XXTI IDLE _ MODE internal XEINT 0 wakup event APLL MPLL HPLL EPLL internal XXTI 6 cycles ARMCLK is the same as those before IDLE...

Page 238: ...de but in Figure 2 4 11 ARMCLK is the same as XXTI after wakeup and APLL should be enabled to supply high frequency for ARM CPU ARM_ARESETn is released within XXTI 1424 cycles after wakeup source is asserted MODE APLL clock out ARM _ ARESETn internal ARMCLK _ OFF internal ARMCLK internal XXTI DEEP _ IDLE _ internal XEINT 0 wakup event APLL MPLL HPLL EPLL internal XXTI 6 cycles ARMCLK is the same a...

Page 239: ...ternal XXTI DEEP _IDLE _MODE internal XEINT 0 wakup event XnRSTOUT SFR_ OTHER 1 0 APLL MPLL HPLL internal EPLL XXTI 51 cycles XXTI 123 cycles XXTI 1424 cycles PLL locking time 300 us XXTI 6 cycles ARMCLK is the same as XXTI S W sets P M S value and enable APLL APLL clock out internal Figure 2 4 11 DEEP IDLE Mode Top Domain Off Wakeup Timing ...

Page 240: ... operation begins normally APLL clock out Note 1 Note 2 Note 1 oscillator stabilization time Note 2 APLL locking time Note 2 oscillator stabilization time 1 OSC _ EN_ STOP 1 b1 XXTI 30 cycles 2 OSC _ EN_ STOP 1 b0 this interval is determined by OSC _ STABLE register ARMCLK _OFF internal STOP _ MODE internal ARMCLK internal XXTI XEINT 0 wakup event APLL MPLL HPLL EPLL internal ARMCLK is the same as...

Page 241: ...al Enabled by H W automatically PLL locking time 300 us XXTI 896 cycles ARMCLK is the same as those before DEEP STOP mode Figure 2 4 13 DEEP STOP Mode TOP Domain on Wakeup Timing When wakeup event is asserted ARMCLK is supplied for ARM CPU within some interval refer to comment on Figure 2 4 13 and ARM_ARESETn is released within XXTI 896 cycles after ARMCLK is supplied in case of OSC_EN_STOP bit 1 ...

Page 242: ..._ OFF internal ARMCLK internal XXTI DEEP _ STOP _ internal XEINT 0 wakup event XnRSTOUT SFR _ OTHER 1 0 APLL MPLL HPLL EPLL internal APLL clock out 2 b 10 XXTI 51 cycles PLL locking time 300 us APLL clock out S W sets P M S value and enable APLL ARMCLK is the same as XXTI Figure 2 4 14 DEEP STOP Mode TOP Domain Off Wakeup Timing 8 5 SLEEP MODE WAKEUP Figure 2 4 5 shows wakeup timing from SLEEP mod...

Page 243: ...on time should be included in PWR_STABLE register VDD_IO VDDALIVE XPWRRGTON VDD VDD VDDINT ARM PLL This interval can be adjusted by PWR_STABLE register ARM_ARESETn NOTE 1 ARMCLK is the same as XXTI ARMCLK XXTI XXTI 16 cycles SLEEP_MODE internal XEINT 0 wakup event APLL clock out XnRSTOUT SFR_OTHER 1 0 2 b10 XXTI 5 cycles APLL clock out PLL locking time 300us S W sets P M S value and enable APLL AP...

Page 244: ...al OSC can be used for main clock Note that when crystal is used for main clock oscillator stabilization time for XXTI or XusbXTI pad should be considered by using PWR_STABLE register in case that oscillation pad is disabled in SLEEP mode OSC VCO Output Clock Disable HCLK Several slow clock cycles OSC or EXTCLK Sleep mode is initiated tOSC2 EXTCLK Wake up from sleep mode Figure 2 4 16 Sleep Mode R...

Page 245: ...not used and therefore XnWRESET should be connected to VDD 10REGISTER DESCRIPTION Register Address R W Description Reset Value PWR_CFG 0xE010_8000 R W Configure power manager 0x2900_0001 EINT_WAKEUP_M ASK 0xE010_8004 R W Configure EINT external interrupt mask 0x0000_0000 Reserved 0xE010_8008 DO NOT CHANGE 0x0000_0000 Reserved 0xE010_800C Reserved 0x0000_0000 NORMAL_CFG 0xE010_8010 R W Configure po...

Page 246: ...C Reserved DCGIDX_MAP0 0xE010_8500 R W DCG Index Map 0 0xFFFF_FFFF DCGIDX_MAP1 0xE010_8504 R W DCG Index Map 1 0xFFFF_FFFF DCGIDX_MAP2 0xE010_8508 R W DCG Index Map 2 0xFFFF_FFFF DCGPERF_MAP0 0xE010_850C R W DCG Performance Map 0 0xFFFF_FFFF DCGPERF_MAP1 0xE010_8510 R W DCG Performance Map 1 0xFFFF_FFFF DVCIDX_MAP 0xE010_8514 R W DVC Index Map 0x00FF_FFFF FREQ_CPU 0xE010_8518 R W Maximum Frequency...

Page 247: ... 7 0x0000_0002 CLKDIV_IEM_L6 0xE010_8708 R W Clock Divider for IEM Performance Level 6 0x0000_0002 CLKDIV_IEM_L5 0xE010_870C R W Clock Divider for IEM Performance Level 5 0x0000_0002 CLKDIV_IEM_L4 0xE010_8710 R W Clock Divider for IEM Performance Level 4 0x0000_0002 CLKDIV_IEM_L3 0xE010_8714 R W Clock Divider for IEM Performance Level 3 0x0000_0002 CLKDIV_IEM_L2 0xE010_8718 R W Clock Divider for I...

Page 248: ...es TOP Memory Retention in DEEP IDLE mode 0 OFF 1 RET 1 Reserved 26 25 DO NOT CHANGE 00 OSCUSB_EN 24 Controls USB X tal oscillator pad XusbXTI in NORMAL mode The state is kept in power down modes Note Do not disable if XusbXTI is used main clock source 0 Disable 1 Enable 1 Reserved 23 19 DO NOT CHANGE 0x0 ST_WAKEUP_MASK 18 System Timer ST wake up mask 0 ST is used as a wakeup source 1 ST cannot be...

Page 249: ... be used as a wakeup source 0 KEY_WAKEUP_MASK 8 Key pad wake up mask 0 Key Pad is used as a wakeup source 1 Key Pad cannot be used as a wakeup source 0 BATF_WAKEUP _MASK 7 BATF wake up source 0 Disables 1 Use as a wakeup source and only use if CFG_BATFLT field has 2 b01 0 CFG_STANDBYWFI 6 5 Configures CORTEX A8 STADNBYWFI Determines the actions taken if the STANDBYWFI signal is activated by the CO...

Page 250: ...e three bits are configured in DEEP IDLE mode CFG_DEEP_IDLE 1 b1 as follows TOP_LOGIC_ON_DIDLE 1 b1 TOP_MEMORY_RET_DIDLE 1 b0 TOP_MEMORY_RET_DIDLE 1 b1 TOP_MEMORY_ON_DIDLE 1 b0 TOP memory power down TOP memory retention TOP_MEMORY_ON_DIDLE 1 b1 TOP memory on TOP_LOGIC_ON_DIDLE 1 b0 TOP_MEMORY_RET_DIDLE 1 b0 TOP_MEMORY_RET_DIDLE 1 b1 TOP_MEMORY_ON_DIDLE 1 b0 TOP_MEMORY_ON_DIDLE 1 b1 TOP memory powe...

Page 251: ... in LPMP3_MODE_SEL in Chapter 2 3 Clock Controller is recommended to be set to 1 in order to minimize the internal current 10 1 4 Configure Power Manager at STOP mode STOP_CFG R W Address 0xE010_8014 STOP_CFG Bit Description Reset Value TOP_MEMORY_ON 1 31 If TOP_LOGIC_ON 0 you should set this bit to 0 0 RET or OFF 1 ON 0 Reserved 30 DO NOT CHANGE 0 ARM_L2CACHE_RET 2 29 0 No Retention On or OFF 1 R...

Page 252: ...s called DEEP STOP mode The available configurations of other bits of STOP_CFG register in each mode are shown below Note n bit offset of corresponding field in STOP_CFG register TL Top domain TM Top memory AL ARM Logic AM ARM L2Cache O available configuration X unavailable configuration the constraint or reason why that configuration is not supported 1 STOP_mode ARM_LOGIC_ON 17 1 b1 TL 8 TM 31 AL...

Page 253: ... 0 1 1 1 1 X AL 1 AL should be 0 4 27M Oscillator XXTI27 and USB Oscillator XusbXTI Enable is also controlled by this bit The relationships among OSCUSB_EN PWR_CFG 24 OSC27_EN PWR_CFG 0 OSC_EN STOP_CFG 0 and OSC_EN SLEEP_CFG 0 are summarized as follows 1 XXTI This pad is not affected by OSCUSB_EN PWR_CFG 24 and OSC27_EN PWR_CFG 0 OSC_EN_STOP STOP_CFG 0 1 b0 OSC_EN_STOP STOP_CFG 0 1 b1 OSC_EN_SLEEP...

Page 254: ...y OSC27_EN PWR_CFG 0 OSCUSB_EN PWR_CFG 24 1 b0 OSCUSB_EN PWR_CFG 24 1 b1 OSC_EN_STOP 1 b0 OSC_EN_STOP 1 b1 OSC_EN_STOP 1 b0 OSC_EN_STOP 1 b1 OSC_EN _SLEEP 1 b1 OSC_EN _SLEEP 1 b0 OSC_EN _SLEEP 1 b1 OSC_EN _SLEEP 1 b0 OSC_EN _SLEEP 1 b1 OSC_EN _SLEEP 1 b0 OSC_EN _SLEEP 1 b1 OSC_EN _SLEEP 1 b0 NORMAL mode Disable Enable IDLE and DEEP IDLE mode Disable Enable STOP and DEEP STOP mode Disable Disable E...

Page 255: ...f 1 Retention 1 IRAMC0 1 IRAMC0 32KB memory control 0 Off 1 Retention 1 Reserved 0 DO NOT CHANGE 1 Each bit is available if TOP_MEMORY_ON field of STOP_CFG is 0 Therefore if TOP_MEMORY_ON filed of STOP_CFG is 1 then each bit has no effect Memory corresponding to each bit means SRAM inside corresponding IP module of Top domain and used by that module 10 2 SYSTEM STABILIZATION COUNTER 10 2 1 Oscilla...

Page 256: ...it takes some amount of time for the pad to generate stable clock OSC_STABLE register is applied to wait for this oscillation stabilization time when OSC_EN 0 of STOP_CFG is 1 b0 in STOP and DEEP STOP mode Oscillation stabilization time is calculated as follows Oscillation stabilization time OSC_Stabilization_Counter_Value x Ocillator_period XTI where OSC_Stabilizaton_Counter_Value can be set by t...

Page 257: ...izaton_Counter_Value can be set by two ways as below you can select one by using STABLE_COUNTER TYPE 23 in OTHERS register 1 Exponential Scale The cycle value mapped by PWR_CNT_VALUE 3 0 is used e g if PWR_CNT_VALUE 3 0 0x1 then PWR_Stabilization_Counter_Value 2 12 4096 2 Set by SFR PWR_Stabilization_Coutner_Value PWR_CNT_VALUE 19 4 And PWR_CNT_VALUE 3 0 should be kept as the reset value 10 2 4 MT...

Page 258: ... REGISTER 10 3 1 Miscellaneous Control Register OTHERS R W Address 0xE010_8200 OTHERS Bit Description Reset Value IO_RET_RELEASE 31 IO_RET_RELEASE IO_RET is retention control signal to I O pad except SDMMC I O SDMMC I O should be controlled separately Refer to SDMMC_IO_RET_RELEASE 22 field in OTHERS register Set this bit to 1 to release IO_RET After IO_RET is released this bit will be cleared to 0...

Page 259: ...tents are reset by hardware 1 L2 valid RAM contents are not reset by hardware 0 PMU_INT_DISABLE 24 Interrupt disabling by PMU Auto clear by H W Usage Before entry to power down mode you should set this bit to 1 before issuing WFI command Interrupt to Cortex A8 after issuing WFI command should be masked since interrupt after issuing WFI command malfunctions due to conflict with power down process p...

Page 260: ...Clear DBGACK signal if this field has 1 Cortex A8 asserts DBGACK signal to indicate the system has entered Debug state If DBGACK is asserted this state is stored in PMU until software clears it using this field 0 CLEAR_BATF_INT 2 12 If this bit is set it clears interrupt caused by battery fault when this bit is set 0 Reserved 11 5 DO NOT CHANGE 0x0 Reserved 4 DO NOT CHANGE 1 Reserved 3 2 DO NOT CH...

Page 261: ... ST 13 Wake up by System Timer Write 1 to clear 0 I2S 12 Wake up by I2S in Audio Block Write 1 to clear 0 MMC2 11 Wake up by MMC2 Write 1 to clear 0 MMC1 10 Wake up by MMC1 Write 1 to clear 0 MMC0 9 Wake up by MMC0 Write 1 to clear 0 HSI 8 Wake up by HSI Write 1 to clear 0 Reserved 7 DO NOT CHANGE 0 BATFLT 6 Wake up by battery fault Write 1 to clear 0 MODEM 5 Wake up by MODEM Write 1 to clear 0 KE...

Page 262: ...6 R W Address 0xE010_8418 Information Register 7 INFORM7 R W Address 0xE010_841C Field Bit Description Reset Value INFORM 31 0 INFORM4 7 registers are not cleared when the XnRESET pin is asserted NOTE INFORM4 7 registers are not cleared when the XnRESET pin is asserted 10 5 1 DCGIDX_MAP0 Register DCGIDX_MAP0 R W Address 0xE010_8500 This register is related to IECCFGDCGIDXMAP 31 0 of IEM_IEC input ...

Page 263: ...s related to IECCFGDCGPERFMAP 63 32 of IEM_IEC input port DCGPERF_MAP1 Bit Description Reset Value dcgperf_map1 31 0 IEC configuration for DCG performance map 63 32 0xFFFF_FFFF dcgperf_map1 31 0 is mapped to IECCFGDCGPERFMAP 63 32 of IEM_IEC input port 10 5 6 DVCIDX_MAP Register DVCIDX_MAP R W Address 0xE010_8514 The register correspond to IECCFGDVCIDXMAP 23 0 of IEM_IEC input port DVCIDX_MAP Bit ...

Page 264: ...nd gives the rate that the DPM is accumulating in kHz Table 2 4 17 lists three examples Table 2 4 17 IECCFGFREQDPM Examples IECCFGFREQDPM 23 0 Verilog expression Processor frequency 0x004E20 24 d020_000 20000kHz 20MHz 0x002710 24 d010_000 10000kHz 10MHz 0x0003E8 24 d001_000 1000kHz 1MHz 10 5 9 DVSEMCLK_EN Register DVSEMCLK_EN R W Address 0xE010_8520 The register related to IECDVSEMCLKEN of IEM_IEC...

Page 265: ... Level 7 APLL_CON_L7 R W Address 0xE010_8604 ARM PLL Control Performance Level 6 APLL_CON_L6 R W Address 0xE010_8608 ARM PLL Control Performance Level 5 APLL_CON_L5 R W Address 0xE010_860C ARM PLL Control Performance Level 4 APLL_CON_L4 R W Address 0xE010_8610 ARM PLL Control Performance Level 3 APLL_CON_L3 R W Address 0xE010_8614 ARM PLL Control Performance Level 2 APLL_CON_L2 R W Address 0xE010_...

Page 266: ...1 b1 0x0 Reserved 7 4 Reserved 0x0 Reserved 3 Reserved 0 Reserved 2 1 DO NOT CHANGE 00 iem_enable 0 IEM function enable bit 0 Disables IEM function 1 Enables IEM function 0 10 5 13 CLKDIV_IEM_L8 Register CLKDIV_IEM_L8 R W Address 0xE010_8700 The register configures clock divider values for ARM and HPM clocks at IEM performance level of 8 CLKDIV_IEM_L8 Bit Description Reset Value Reserved 31 16 DO ...

Page 267: ...TARM DOUTAPLL RATIO RATIO arm_div_val_l8 1 and DIVARM_HPM clock divider ratio DOUTARM_HPM DOUTAPLL_HPM RATIO RATIO arm_div_val_l8 1 at IEM performance level of 8 000 Reserved 3 DO NOT CHANGE 0 bus_div_val_l8 2 0 DIVD0_BUS clock divider ratio HCLKD0 DOUTARM RATIO RATIO bus_div_val_l8 1 at IEM performance level of 8 010 DIVAPLL DIVAPLL_HPM DIVARM DIVARM_HPM DIVHPM and DIVD0_BUS clock divider are sho...

Page 268: ...et Value Reserved 31 16 Reserved 0x0000 Reserved 15 13 Reserved 000 pll_div_val_l1 7 12 This field is used to set dividing value in both DIVAPLL and DIVAPLL_HPM DIVAPLL clock divider ratio DOUTAPLL MOUTAPLL RATIO RATIO pll_div_val_l1 7 1 and DIVAPLL_HPM clock divider ratio DOUTAPLL_HPM MOUTAPLL RATIO RATIO pll_div_val_l1 7 1 at IEM performance level from 1 to 7 0 Reserved 11 DO NOT CHANGE 0 hpm_di...

Page 269: ...IEM_HPMCLK_DIV Register IEM_HPMCLK_DIV R Address 0xE010_8724 The register reads the current IEM HPMCLK divider value IEM_HPMCLK_DIV Bit Description Reset Value Reserved 31 4 Reserved 0x0000_000 Reserved 3 Reserved 0 iem_hpmclk_div 2 0 IEM HPMCLK Divider Value 000 ...

Page 270: ...ower on Power gating ALIVE Power on Keep states Run or power gating in NORMAL mode Low power MP3 playback application can be run according to the following sequence 1 Loading MP3 file from NAND to input buffer in external DRAM 2 Memory copy data to input buffer 3 Cache line fill for MP3 code and data 4 Read input stream from input buffer in DRAM 5 MP3 decoding Include parsing 6 Write output data t...

Page 271: ... system Power on TV Sub system Power on Power gating TOP Power on ALIVE Power on Keep states Run or power gating in NORMAL mode 11 3 CAMCORDER RECODING Power Mode NORMAL IDLE DEEP IDLE CPU RUN STANDBY L2RETENTION POWER OFF MFC Power on G3D Power gating Audio Sub system Power on LCD Sub system Power on Power gating TV Sub system Power gating TOP Power on ALIVE Power on Keep states Run or power gati...

Page 272: ...CLK_EN The detailed descriptions are given in next section Table 2 4 58 Registers for IEM Clock Change Performance Level IEM configuration PLL P M S value Clock Divider value 8 level APLL_CON_L8 CLKDIV_IEM_L8 7 level APLL_CON_L7 CLKDIV_IEM_L7 6 level APLL_CON_L6 CLKDIV_IEM_L6 5 level APLL_CON_L5 CLKDIV_IEM_L5 4 level APLL_CON_L4 CLKDIV_IEM_L4 3 level APLL_CON_L3 CLKDIV_IEM_L3 2 level APLL_CON_L2 C...

Page 273: ...ws a high level block diagram of a complete IEM solution System on Chip SoC Power Supply Unit Off chip ARM processor Applications OS Intelligent Energy Manager Software Intelligent Energy Controller Advanced Power Controller Hardware Performance Monitor Clock Management Unit Performance Communication Interface Vdd HPM clock ARM Core clock Power Management Unit Figure 2 5 1 Intelligent Energy Manag...

Page 274: ...t does so whenever a system event occurs that might influence the optimum performance level The IEM software records information about the events that occur and the tasks related to them The policies that are a part of the IEM software analyze this information to determine the optimum performance level Whenever the optimum performance level changes the IEM software uses the performance scaling har...

Page 275: ...re clock Power Management Unit AMBA APB Bus Current Voltage Index Target Voltage Index Power request Hardware Performance Monitor Configuration Information Current Voltage Index Target Voltage Index Power Request Maximum performance request Interrupts Acknowledge Current Frequency Index Target Frequency Index Current Frequency Index Target Frequency Index Interrupts Figure 2 5 2 IEM Block Diagram ...

Page 276: ...pecific and product platform scaling hardware can be controlled to bring the system to that performance point Battery life is extended by lowering the operating frequency and voltage of SoC components such as the processor and consequently reducing energy consumption The IEC provides an abstracted view of the SoC specific performance scaling hardware It is responsible for translating the performan...

Page 277: ...API interface for efficient control and monitoring implementation independent fractional performance setting interface to support performance prediction algorithms without hard coded frequencies implementation independent interrogation of performance level quantization mapping levels to enable performance prediction software to adapt to the processor clock frequencies provided SoC specific configu...

Page 278: ...ive target performance level requirements and to send out current performance level updates indicating voltage readiness Together with the HPM the APC1 tracks the system timing in real time and sends out voltage commands to the EMU to request the adjustment of voltage level The flowchart in Figure 2 5 4 shows how the adaptive voltage control is processed to find optimum voltage level Figure 2 5 3 ...

Page 279: ...evel indication then the APC1 can also determine this through the PWI 2 1 3 Hardware Performance Monitor The Hardware Performance Monitor HPM is designed for reuse and easy implementation Although it is a separate entity in physical partition the HPM is an integral part of the APC1 for an AVS power management system The HPM is not a memory mapped device An HPM is required for closed loop control b...

Page 280: ... the necessary clocks for the CPU for example processor clock peripheral clocks AMBA clock Additionally for a more efficient design the CMU must be capable of generating the different performance levels as indicated by the IEC The CMU can also be a memory mapped AMBA peripheral and can contain both control and status registers The design of the CMU must meet the requirements set by the IEC and the...

Page 281: ... the IEM kernel When the IEM kernel receives the corresponding control message it 1 Allocates memory for the event queue and initializes it 2 Allocates memory for the IEM blocks and initializes them 3 Registers the kernel hooks that the OS calls whenever a system event occurs 2 2 1 Handling system events When an event occurs that might influence the optimum performance level the OS calls the appro...

Page 282: ...ng user input If necessary the fast event handler can get further information about the task by making calls to the OS layer API Storing policy specific information about the current state of the task or the system for later processing by the standard event handler of the same policy The fast event handler might get this information by making calls to the IEM HAL or OS layer APIs It typically stor...

Page 283: ...handler of the same policy This is because the standard event handler is working on historical data Also the standard event handler is pre emptable and so can spend longer analyzing the data without impacting system responsiveness It can therefore use more complex algorithms such as decaying weighted averages When the final outstanding event in the queue is processed the standard event handlers ca...

Page 284: ...LL Output MHz ARM Core Clock Frequency MHz HPM Clock Frequency MHz AXI Bus Clock Frequency MHz ARM Clock Ratio fPLL fARM HPM Clock Ratio fARM fHPM AXI Bus Clock Ratio fPLL fAXI Performance mapping 800 0 100 0 2 100 0 533 3 66 7 3 66 7 400 0 50 0 4 50 0 320 0 40 0 5 40 0 266 7 33 3 6 33 3 228 6 28 6 7 28 6 200 0 25 0 8 25 0 177 8 22 2 9 22 2 1600 160 0 20 0 160 0 10 8 10 20 0 There are divider valu...

Page 285: ...E Minimum A B 1_1111 sd_low 1 0 vdd_stable A B slack_reg 5 0 ext_slack 15 0 Sign extender A 5 2 4 hF A 5 2 4 h0 APC_SS_GAIN_EN vdd_stable loop_gain APC_GAIN_SEL APC_SAT_GAIN_EN sd_saturation step_upward APC_IGAIN3 APC_UP_GAIN_EN step_upward APC_IGAIN2 APC_LOW_GAIN_EN sd_low APC_IGAIN4 Default APC_IGAIN1 Sign extender integral integral_reg integral Shifter tgained_slack 22 0 rst_filterq integral 22...

Page 286: ...r supplied Integral is less than or equal to noise_limit_int 4 0 2 Above reference Integral is negative Voltage over supplied Absolute value of Integral is less than APC_OVSHT_LMT 7 0 Low_VDD_timeout Too much time taken to increase voltage step_upward 1 when Integral is positive and step_int_dir 1 APC_UNSHT_NOISE 5 4 00 5 h00 01 5 h10 10 5 h04 11 5 h1F noise_limit_int Undershoot condition 1 Positi...

Page 287: ...oltage level while voltage values in open loop mode Calibration code stands for critical path delay of ARM core In S5PC100X 14 th tap output of HPM has the nearly same delay to the critical path of ARM core when HPM clock ratio is equal to 1 which can be encoded to the delay code 5 hE 3 3INITIALIZATION SEQUENCE 1 Initialize the index map all other IEM APC mapping values 2 If IEM will use overdrive...

Page 288: ...ly when data is being transferred Otherwise the SCLK signal line is at logic low voltage Minimum pulse width of the clock signal is 26ns The PWI data line is bi directional Data is written on the falling edge of the SCLK and read on the rising edge of the SCLK 4 I O DESCRIPTION Function Signal I O Description Pad type IEM_SCLK Bidirectional PWI clock XiemSCLK dedicated IEM_SPWI Bidirectional PWI s...

Page 289: ...0044 RO Configuration Fractional Index Map32 From PMU IECCFGDCGIDXMAP6 4 0xE110_0048 RO Configuration Fractional Index Map64 From PMU IECCFGDVCIDXMAP 0xE110_004C RO Configuration DVC Index Map Register From PMU IECCFGDCGPERFMA P0 0xE110_0060 RO Configuration Performance Map 0 From PMU IECCFGDCGPERFMA P4 0xE110_0064 RO Configuration Performance Map 4 From PMU IECDPMCR 0xE110_0100 R W DPM Command Re...

Page 290: ...er 0 0x50 IECPeriphID1 0xE110_0FE4 RO Peripheral Identification Register 1 0x17 IECPeriphID2 0xE110_0FE8 RO Peripheral Identification Register 2 0x04 IECPeriphID3 0xE110_0FEC RO Peripheral Identification Register 3 0x08 IECID0 0xE110_0FF0 RO IEC Identification Register 0 0x0D IECID1 0xE110_0FF4 RO IEC Identification Register 1 0xF0 IECID2 0xE110_0FF8 RO IEC Identification Register 2 0x05 IECID3 0x...

Page 291: ...er 0x00 APC_CLKDIV_PWICL K 0xE100_0040 R W PWI Clock Division Register 0x00 APC_OVSHT_LMT 0xE100_0050 R W APC Overshoot Limit Register 0x00 APC_CLP_CTRL 0xE100_0054 R W APC Closed loop Control 0x00 APC_SS_SRATE 0xE100_0058 R W APC Steady State Slew Rate Register 0x00 APC_IGAIN4 0xE100_005C R W Integrator s Gain 4 Register 0x00 APC_IGAIN1 0xE100_0060 R W Integrator s Gain 1 Register 0x00 APC_IGAIN2...

Page 292: ...re Register 6 0x7F APC_PL7_COREVDD 0xE100_00B8 R W Open loop VDD Core Register 7 0x7F APC_PL8_COREVDD 0xE100_00BC R W Open loop VDD Core Register 8 0x7F APC_RET_VDD 0xE100_00C0 R W Retention VDD Register 0x00 APC_ITSTOP3 0xE100_00C4 R W Integration Test Output Read or Set Register 3 0x00 APC_DBG_DLYCODE 0xE100_00E0 RO Debug Performance Register 0x00 APC_REV 0xE100_00FC RO Revision Number Register ...

Page 293: ...ed 0 IEC Software Debug Emulation 3 Control to debug performance scaling 0 IEC performance scaling software debug disabled also the reset value 1 IEC performance scaling software debug enabled When this bit is seta the performance level driven out of the IECTGTDVCIDX is set to maximum regardless of the software request The performance level changes are only visible on IECTGTDCGIDX 0 IEC Max Perf E...

Page 294: ...the target fractional performance level At system reset the value 0x80 100 0x80 NOTE This register is read as 0x00 5 2 4 DPC Current Performance Register IECDPCCRNTPERF R Address 0xE110_000C IECDPCCRNTPERF Bits Description Reset Value Reserved 31 8 Reserved read undefined do not modify 0 IECDPCCRNTPERF 7 0 Returns the current performance level as indicated to the IEC by the DCG on the IECCRNTDCGID...

Page 295: ... Sleep Masked Interrupt Status CSMIS 1 Gives the masked interrupt state after masking of the IECCPUSLPINT interrupt The reset value is 0 0 CPU Wake up Masked Interrupt Status CWMIS 0 Gives the masked interrupt state after masking of the IECCPUWUINT interrupt The reset value is 0 0 5 2 8 Interrupt Clear Register IECICR W Address 0xE110_001C IECICR Bits Description Reset Value Reserved 31 2 Reserved...

Page 296: ...CCFGDCGIDXMAP 63 32 From PMU 5 2 13 Configuration Fractional Index Map32 Register IECCFGDCGIDXMAP64 R Address 0xE110_0048 IECCFGDCGIDXMAP64 Bits Description Reset Value IECCFGDCGIDXMAP64 31 0 State of IECCFGDCGIDXMAP 95 64 From PMU 5 2 14 Configuration DVC Index Map Register IECCFRDVCIDXMAP R Address 0xE110_004C IECCFGDVCIDXMAP Bits Description Reset Value 31 24 Reserved read undefined do not modi...

Page 297: ...E Bits Description Reset Value 31 8 Reserved read undefined do not modify 0 IECDPM2RATE 7 0 The fractional rate that DPM channel 2 counts The reset value of this register is 0x80 that is 100 0x80 5 2 19 DPM Channel Rate Registers IECDPM3RATE R W Address 0xE110_010C IECDPM3RATE Bits Description Reset Value 31 8 Reserved read undefined do not modify 0 IECDPM3RATE 7 0 The fractional rate that DPM cha...

Page 298: ...100_018C IECDPM2HI Bits Description Reset Value IECDPM2HI 31 0 High 32 bits of DPM channel 2 The reset value is 0x00000000 0x00000000 5 2 24 DPM Channel Registers IECDPM3LO R Address 0xE1100_0190 IECDPM3LO Bits Description Reset Value IECDPM3LO 31 0 Low 32 bits of DPM channel 3 The reset value is 0x00000000 0x00000000 5 2 25 DPM Channel Registers IECDPM3HI R Address 0xE1100_0194 IECDPM3HI Bits Des...

Page 299: ...ify X Revision 7 4 These bits read back as 0x0 0x0 Designer1 3 0 These bits read back as 0x04 0x04 5 2 29 Peripheral Identification Register 3 IECPeriphID3 R Address 0xE110_0FEC IECPeriphID3 Bits Description Reset Value Reserved 31 8 Reserved read undefined do not modify X Configuration 1 7 0 Number of DPC levels These bits read back as 0x08 0x08 5 2 30 Peripheral Identification Register 4 IECPeri...

Page 300: ...ter 0 IECID0 R Address 0xE110_0FF0 IECID0 Bits Description Reset Value 31 8 Reserved read undefined do not modify X IECID0 7 0 These bits read back as 0x0D 0x0D 5 2 35 IEC Identification Register 1 IECID1 R Address 0xE110_0FF4 IECID1 Bits Description Reset Value Reserved 31 8 Reserved read undefined do not modify X IECID1 7 0 These bits read back as 0xF0 0xF0 5 2 36 IEC Identification Register 2 I...

Page 301: ...001 authenticate 4 b0010 register read 4 b0011 register write 4 b0100 wakeup 4 b0101 sleep 4 b0110 shutdown 4 b1001 synchronize Unused command patterns result in a No OPeration NOP at the PWI interface 0x0 5 3 2 PWI Write Data Register APC_PWIDATAWR R W Address 0xE100_0004 APC_PWIDATAWR Bits Description Reset Value PWI Slave Write Data 7 0 Data is written to the PWI slave 0x00 5 3 3 PWI Read Data ...

Page 302: ...d 2 Read undefined Write as zero 0 APC_LOOP_MODE 1 Enable bit for the closed loop or the open loop mode defaults to the open loop mode setting this bit enables the closed loop mode The voltage scaling in the open loop or the closed loop mode is enabled only after setting the APC_VDD_UD bit of the APC_CONTROL Register 0 APC_VDD_UD 0 Enables voltage scaling feature in the APC1 defaults to the fixed ...

Page 303: ...bit vddchkd counter 0x00 5 3 9 VDD Pre delay Select Register APC_PREDYSEL R W Address 0xE100_0024 APC_PREDYSEL Bits Description Reset Value Reserved 7 3 Read undefined Write as zero 0 Pre delay 2 0 Selects the predelay value for the HPM 0x7 5 3 10 APC Interrupt Mask Register APC_IMASK R W Address 0xE100_0028 APC_IMASK Bits Description Reset Value Reserved 7 Read undefined Write as zero 0 APB Write...

Page 304: ...in the closed loop mode indicating that the dynamic compensator is not able to increase the voltage to the required level for the new higher performance level within the maximum time period set by the hardware 0 Undershoot Interrupt 0 In the closed loop AVS operation for a performance level change after reaching the optimum voltage the APC1 asserts an interrupt if the voltage correction continues ...

Page 305: ... the optimum core voltage for the safe SoC operation 0x0 5 3 14 Wakeup Delay Register APC_WKUP_DLY R W Address 0xE100_0038 APC_WKUP_DLY Bits Description Reset Value Wakeup Delay 7 0 Count for the wakeup delay 0x00 5 3 15 Slack Sample Count Register APC_SLK_SMP R W Address 0xE100_003C APC_SLK_SMP Bits Description Reset Value Reserved 7 6 Read undefined Write as zero 0 Slack Sample Count 5 0 The tim...

Page 306: ...compensator This gain term is selected when the slack or eHPM value is between 3 to 3 0 APC_SAT_GAIN_EN 0 Enables the APC_GAIN3 term for the dynamic compensator This gain term is selected when the PC value is saturated and the voltage is stepping up This gain term has higher priority over the gain term 2 0 5 3 19 APC Steady State Slew Rate Register APC_SS_SRATE R W Address 0xE100_0058 APC_SS_SRATE...

Page 307: ...is gain term are one to ten Rest of the values are treated as zero in the closed loop AVS operations 0x0 5 3 22 Integrator s Gain Registers APC_IGAIN3 R W Address 0xE100_0068 APC_IGAIN3 Bits Description Reset Value Reserved 7 4 Read undefined Write as zero 0 Gain 3 3 0 Dynamic compensator uses this gain term for the saturated HPM output when enabled The programmable values for this gain term are o...

Page 308: ...n Code Registers are eight 5 bit registers Their names are APC_PL1_CALCODE APC_PL8_CALCODE They give delay information target for closed loop operation APC_PL _CALCODE Bits Description Reset Value Reserved 7 5 Read undefined Write as zero X Reference Calibrated Code 1 4 0 The RCC for performance level 0x1F y Open loop VDD Core Registers APC_PL1_COREVDD R W Address 0xE100_00A0 y Open loop VDD Core ...

Page 309: ...ntion VDD 6 0 The retention voltage level for performance level zero 0x00 5 3 26 Debug Performance Registers APC_DBG_DLYCODE R Address 0xE100_00E0 APC_DBG_DLYCODE Bits Description Reset Value Reserved 7 5 Read undefined 0 Performance Code 4 0 The PC of the HPM 0x00 5 3 27 Revision Number Registers APC_REV R Address 0xE100_00FC APC_REV Bits Description Reset Value Revision Number 7 0 Holds the APC1...

Page 310: ...ipheral control 3 VIC TZIC is placed on AXI_D0 to reduce the interrupt latency 4 M2M DMA is placed on D0 domain while Peri DMAs are placed on D1 domain 5 Only AXI_D0 s M0 port supports Bus QoS scheme 6 S NS inherited master acts as Secure master when it s SFR slave port set as secure slave Otherwise it acts as non secure master APB1_D1 APB2_D1 Secure slave Configurable slave by port 0 0 1 PWM IEM_...

Page 311: ...traffic The QoS scheme is meaningless to the master interface which is connected to the slave whose combined acceptance capability is only 1 Therefore the QoS feature is only applied to the M0 port of AXI_D0 interconnect in S5PC100 The fixed round robin arbitration was proposed to allocate the proper bandwidth to each slave interface Therefore this arbitration is beneficial to the multimedia maste...

Page 312: ...are a number of outstanding transactions equal to the value stored in the QoS tidemark register It then accepts transactions only from slave ports specified in the QoS access control register This restriction remains until the number of outstanding transactions is again less than the value stored in the QoS tidemark register Figure 3 1 2 shows the implementation for an interconnect that supports t...

Page 313: ...ration mechanism registers the arbitration decision for use in the subsequent cycle An arbitration decision taken in the current cycle does not affect the current cycle If no SI s are active the arbiter adopts default arbitration that is the highest priority SI If this occurs and then the highest priority interface becomes active in the same cycle as or before any other SI then this does not const...

Page 314: ...t currently in the highest priority position becomes the lowest and all other slots move to a higher priority but maintain their relative order as shown in Figure 3 1 3 This means that if an SI is the highest priority active SI but is not the highest priority interface then it continues to win the arbitration until it becomes the highest priority interface and then the lowest priority interface su...

Page 315: ...event other masters in its group from accessing the slave If you configure all master priorities to different levels the arbiter implements a fixed priority scheme This occurs because in this case each master is in a group of its own and therefore masters maintain their ordering If all master priorities are the same then an LRG scheme is implemented The reason that it behaves as an LRG is because ...

Page 316: ... value for MI 2 0x00000000 W_AR_M2 0xE300_044C R W AW Channel Arbitration value for MI 2 0x00000000 CFGR0 0xE300_0FC0 R Primecell Configuration register 0 0x00000003 CFGR1 0xE300_0FC4 R Primecell Configuration register 1 0x00000003 CFGR2 0xE300_0FC8 R Primecell Configuration register 0 0x00000000 CFGR3 0xE300_0FCC R Primecell Configuration register 1 0x00000000 PERPHID0 0xE300_0FE0 R Primecell Per...

Page 317: ...comes active for this MI If a value of 0 is written to this register then the QoS scheme is turned off for this MI This behavior ensures that it is impossible to block all transactions completely by accidental mis programming 0x0 3 2 2 QoS Access Control Registers for M0 QOSAC_M0 R W Address 0xE300_0404 QOSAC_M0 Bit Description Reset Value Reserved 31 3 Reserved QoS Access Control 2 0 A 1 in any b...

Page 318: ...required because the arbitration system must maintain exactly one slot for each SI for correct operation You cannot program the RR scheme therefore writes are completed but are ignored Reads data case W Slot number writing before read M0 M1 M2 Bit Description Reset Value Special Format 31 8 0xFF0000 indicates its slot number writing function Slot 7 0 The slot for which the data is to be read Read ...

Page 319: ... invasive debug with the core halted using breakpoints and watchpoints to halt the core on specific activity a debug connection to examine and modify registers and memory and provide single step execution Conventional monitor debug This is invasive debug with the core running using a debug monitor that resides in memory Trace This is non invasive debug with the core running at full speed using col...

Page 320: ...e following advantages for multi core SoC designs There is no requirement to run at the lowest common speed A slow or powered down component has no effect on access to other components This means that power management has minimal impact on debug The speed of access is not affected by the number of devices in the system You have direct access to individual devices You can add third party debug comp...

Page 321: ...nables tool developers to supply a standard control dialog so that software programmers can connect trigger events 1 2 3 Trace The CoreSight Design Kit provides components that support a standard infrastructure for the capture and transmission of trace data combination of multiple data streams by funneling together and then output of data to a trace port or storing in an on chip buffer 1 3 CORESIG...

Page 322: ...CORESIGHT S5PC100 USER S MANUAL REV1 0 3 2 4 Figure 3 2 2 S5PC100 Coresight Structure ...

Page 323: ...served differently While the memory map for JTAG port is same as shown in Figure 3 2 2 the memory map for system view is same as the memory map for JTAG port system register offset The debugger register map of S5PC100 is summarized in Figure 3 2 3 Figure 3 2 3 Debugger Register Map of S5PC100 The more detail information of debugger register will be handled in programmers model part ...

Page 324: ...e authentication signals such as DBGEN NIDEN SPIDEN SPNIDEN are all 0 before passing authentication AXI_D0 64b 3x3 166MHz DMC0 SEC SS AXI_B0 64b 4x2 166MHz ARM AXI_C0 32b 2x7 166MHz LPDDR1 166MHz 0 0 0 0 1 1 1 2 1 5 CSSYS AHB AP 6 JTAG detector Authentication path DBGEN NIDEN SPIDEN SPNIDEN DBGEN NIDEN SPIDEN SPNIDEN Access controller SecAccessEn NSecAccessEn SMode JTAGDetect DBGEN 1 NIDEN 1 SPIDE...

Page 325: ... invasive 1 1 1 b0 1 b1 1 b0 1 b0 JTAG authenticated as non secure invasive 1 1 1 b1 1 b1 1 b0 1 b0 JTAG authenticated as secure non invasive 1 0 1 b0 1 b1 1 b1 1 b1 JTAG authenticated as secure invasive 1 0 1 b1 1 b1 1 b1 1 b1 non protected mode non secure invasive 0 1 1 b1 1 b1 1 b0 1 b0 non protected mode secure invasive 0 0 1 b1 1 b1 1 b1 1 b1 And the AHB AP s address mux is controlled by auth...

Page 326: ...void security hole before authentication The blue line access is available while the red line accesses are not available AHB2AXI AHB AP 0 1 DBGEN SPIDEN The debugging through AHB AP is available only when the authentication successes in Secure invasive debug mode Figure 3 2 5 AHB AP Mux Control by Authentication Signal The authentication sequence script and the hash key generation program will be ...

Page 327: ...of the DAP The DAP enables debug access to the complete SoC using a number of master ports Access to the CoreSight Debug Advanced Peripheral Bus APB is enabled through the APB Access Port APB AP and APB Multiplexer APB MUX and system access through the Advanced High performance Bus Access Port AHB AP The DAP comprises the following interface blocks External debug access using the JTAG Debug Port E...

Page 328: ...CORESIGHT S5PC100 USER S MANUAL REV1 0 3 2 10 Figure 3 2 6 Structure of the Coresight DAP Components ...

Page 329: ...ociated with its trace source after the data is read back out of the ETB Control Control registers for trace capture and flushing APB interface Read write and data pointers provide access to ETB registers In addition the APB interface supports wait states through the use of a PREADYDBG signal output by the ETB The APB interface is synchronous to the ATB domain Register bank Contains the management...

Page 330: ...CORESIGHT S5PC100 USER S MANUAL REV1 0 3 2 12 Figure 3 2 7 ETB Block Diagram ...

Page 331: ...nformation from one core to another so that program execution on both processors can be stopped at the same time if required Cross Trigger Interface CTI The CTI combines and maps the trigger requests and broadcasts them to all other interfaces on the ECT as channel events When the CTI receives a channel event it maps this onto a trigger output This enables subsystems to cross trigger with each oth...

Page 332: ... TAP reset XjTRSTn Dedicated TCK Input TAP clock XjTCK Dedicated TMS Input TAP test mode selection XjTMS Dedicated TDI Input TAP data in XjTDI Dedicated TDO Output TAP data out XjTDO Dedicated NOTE Type field indicates whether pads are dedicated to the signal or pads are connected to the multiplexed signals ...

Page 333: ...n a TrustZone design It provides system flexibility that enables to configure different areas of memory as secure or non secure The S5PC100 comprises of three TZPC 1 1 FEATURES 1 Protection bits This enables you to program maximum 32 areas of memory as secure or non secure 2 Secure region bits This enables you to split an area of internal RAM into both secure and non secure regions 3 The Access Co...

Page 334: ...er TZMA You can use this to split the RAM into two regions One secure One non secure This enables the best use of memory and other system resources It is assumed that the specific secure and non secure requirements for an application are determined during BOOT UP OS or Secure kernel port development work This means that the secure and non secure memory partitioning is not expected to change dynami...

Page 335: ...C0 TZPC1 TZPC2 Register Bit Module Name Module Name Module Name 0 ASYNC_APBIF GPIO I2S0 1 G2D CFCON IEM_APC I2S1 2 CSSYS IEM_IEC I2S2 3 MEMSYS Data SYSCON_OFF SPDIF 4 AUDIO_SS PWM PCM0 5 DMC SYSTIMER PCM1 6 VIC WDT AC97 TZPCDECPROT0 7 MEMSYS SFR RTC_APBIF CELLGUIDE 0 UART KEYIF 1 SPI0 TSADC 2 SPI1 SDMMC 3 SPI2 USB 4 DMC SFR IrDA LCD 5 I2C TV 6 CAN0 MFC TZPCDECPROT1 7 CAN1 G3D 0 MIPI_DSI 1 HDMI_I2C...

Page 336: ...PID Secure SECKEY Secure MEM_SDMA Secure TZIC Secure SECSS Secure If non secure master accesses to secure slave area DECERR occurs Table 3 3 3 TZPC Transfer Attribite Master Attribute Transfer Attribute Slave Area Attribite Response Secure Transfer Secure Slave Area OK Secure Transfer Non Secure Slave Area OK Non Secure Transfer Secure Slave Area DECERR Secure Master Non Secure Transfer Non Secure...

Page 337: ... 0x0000000D TZPCPCELLID1 0xE380_0FF4 R TZPC Identification Register 1 0x000000F0 TZPCPCELLID2 0xE380_0FF8 R TZPC Identification Register 2 0x00000005 TZPC1 TZPCR0SIZE 0xE280_0000 R W Not used 0x00000200 TZPCDECPROT0Stat 0xE280_0800 R Decode Protection 0 Status Register 0x00000000 TZPCDECPROT0Set 0xE280_0804 W Decode Protection 0 Set Register TZPCDECPROT0Clr 0xE280_0808 W Decode Protection 0 Clear ...

Page 338: ...egister TZPCDECPROT1Clr 0xE290_0814 W Decode Protection 1 Clear Register TZPCDECPROT2Stat 0xE290_0818 R Not used 0x00000000 TZPCDECPROT2Set 0xE290_081C W Not used TZPCDECPROT2Clr 0xE290_0820 W Not used TZPCPERIPHID0 0xE290_0FE0 R TZPC Peripheral Identification Register 0 0x00000070 TZPCPERIPHID1 0xE290_0FE4 R TZPC Peripheral Identification Register 1 0x00000018 TZPCPERIPHID2 0xE290_0FE8 R TZPC Per...

Page 339: ... RAM to secure regardless of size 0x3FF 4 3 DECODE PROTECTION 0 3 STATUS REGISTERS TZPCDECPROTxSTAT TZPC0 R Address 0xE380_0800 0xE380_080C TZPCDECPROTxSTAT TZPC1 R Address 0xE280_0800 0xE280_080C 0xE280_0818 TZPCDECPROTxSTAT TZPC2 R Address 0xE290_0800 0xE290_080C TXPCDECPROTxStat Bit Description Reset Value Reserved 31 8 Read undefined 0 DECPROTxStat 7 0 Show the status of the decode protection ...

Page 340: ...decode region to non secure There is one bit of the register for each protection output eight outputs are implemented as standard 4 5 DECODE PROTECTION 0 2 CLEAR REGISTERS TZPCDECPROTxClr TZPC0 W Address 0xE380_0808 0xE380_081C TZPCDECPROTxClr TZPC1 W Address 0xE280_0808 0xE280_081C 0xE280_0820 TZPCDECPROTxClr TZPC2 W Address 0xE290_0808 0xE290_081C TXPCDECPROTxClr Bit Description Reset Value Rese...

Page 341: ...1 TZPCPERIPHID1 R ADDRESS 0XE380_0FE4 0XE280_0FE4 0XE290_0FE4 TZPCPERIPHID1 Bit Description Reset Value Reserved 31 8 Read undefined 0 Designer0 7 4 These bits read back as 0x1 0x1 Partnumber1 3 0 These bits read back as 0x8 0x8 4 8 TZPC PERIPHERAL IDENTIFICATION REGISTER 2 TZPCPERIPHID2 R ADDRESS 0XE380_0FE8 0XE280_0FE8 0XE290_0FE8 TZPCPERIPHID2 Bit Description Reset Value Reserved 31 8 Read unde...

Page 342: ... read back as 0x0D 0x0D 4 10 IDENTIFICATION REGISTER 1 TZPCPCELLID1 R ADDRESS 0XE380_0FF4 0XE280_0FF4 0XE290_0FF4 TZPCPCELLID1 Bit Description Reset Value Reserved 31 8 Read undefined 0 TZPCPCELLID1 7 0 These bits read back as 0xF0 0xF0 4 11 IDENTIFICATION REGISTER 2 TZPCPCELLID2 R ADDRESS 0XE380_0FF8 0XE280_0FF8 0XE290_0FF8 TZPCPCELLID2 Bit Description Reset Value Reserved 31 8 Read undefined 0 T...

Page 343: ...omains Figure 3 4 1 Asynchronous Bridge Block Diagram The bridge provides buffered synchronization of the AXI channels AW Write Address Channel W Write Data Channel B Write Response Channel AR Read Address Channel R Read Data Channel The major features of the bridge include Single independent AXI master and AXI slave interfaces All AXI channels are buffered independently Configurable FIFO buffer d...

Page 344: ...pins are omitted for clarity Each channel FIFO is divided into two halves that correspond to the source of the clock for the components in them ACLKS Connects to the following Write address channel FIFO write half Write data channel FIFO write half Read address channel FIFO write half Write response channel FIFO read half Read data channel FIFO read half ACLKM Connects to the following Write addre...

Page 345: ...S5PC100 USER S MANUAL REV1 0 ASYNC BRIDGE 3 4 3 Figure 3 4 2 Asynchronous Bridge Components ...

Page 346: ... Asynchronous FIFO The asynchronous FIFOs are implemented as an array of data storage elements in parallel The write enables and read multiplexing are controlled by separate circular counters that operate in each clock domain The data storage elements provide the mechanism for data to cross the timing boundary The read counter is made available to the write process and the write counter is made av...

Page 347: ... does not enable overflow or underflow Subsequent synchronization captures the new value Figure 3 4 4 shows timing for a single place FIFO Each channel exhibits latency between two and three read clock cycles from the write clock edge on which the data is accepted and the earliest read clock edge at which the data can be read The latency experienced by any particular transfer depends on the occupa...

Page 348: ... 2 Gray Code The Gray code used for an N entry FIFO has 2N values in its sequence and the order of the values is chosen so that each value when XORed with the value N places away from it gives the same result and does not give that result when XORed with any other value in the sequence This enables the fullness and emptiness to be determined by comparing the two counters Emptiness is shown by the ...

Page 349: ...ce The first value in the second half of the sequence is the fullness value for the sequence Figure 3 4 5 shows a typical sequence of length 6 Figure 3 4 5 Example Gray Code Sequence of Length 6 for 3 Entry FIFO This results in a sequence where the bits order change between values M and M 1 is the same as the order that they change between M N and M N 1 For example in a sequence of 6 values and 3 ...

Page 350: ... Focused on Clock Although the most masters of D1 domain s performance depend not on memory latency but on memory bandwidth the 3D engine has cache interface whose performance is affected by memory latency The MFC has limited ability of hiding memory latency Therefore the less latency Async Bridge yields the better performance D1 domain can be obtained S5PC100 improved general asynchronous bridge ...

Page 351: ...ency of DRAM from the master of D1 domain is about 15 12 cycle at D1 clock while the latency is about 14 22 cycle by adopting 1 2 cycle synchronizer In S5PC100 system the 7 8 degradation of 3D engine is observed in the experiment which inserts the register slice between 3D engine and the DRAM The full register slice increases total 2 cycles latency Hence we expect that using 1 2 cycle synchronizer...

Page 352: ... the stalling of data channel creates bubbles in data bus Because the read data bubbles are generated after DRAM controller operation there is no bus component that can remove these bubbles except Async Bridge Fortunately these read data bubbles can be reduced by increasing read data FIFO size of Async Bridge In S5PC100 the read data FIFO size is increased to 32 We assumed the worst case is the 4 ...

Page 353: ...er s filling speed after fetching several beat of data the slave should wait for the master s writing down It causes the bubbles in the write data channel In S5PC100 in order to avoid the bubble condition WREADY of Async Bridge s slave part is delayed for proper cycles according to the clock speed rate of master and slave as shown in Figure 3 4 9 As shown in Figure 3 4 9 although we delayed the WR...

Page 354: ...le The bubble generation mechanism and its solution are depicted in Figure 3 4 10 The basic idea is very simple The AWVALID assertion of slave part of Async Bridge is delayed as like delaying WREADY in first write enhancement scheme Figure 3 4 10 Big Bubble Between AW Channel and W Channel and its Solution in Async Bridge The delay cycle of AW channel and W channel depends on both the clock speed ...

Page 355: ...is default master AWVALID signal should be delayed 1 more cycle to increase bandwidth capacity of write data channel Table 3 4 1 The Delay Cycle for Various Burst Transactions and the Clock Combinations Clock Index Bubble Size Delay Cycle D1 D0 Clock Rate Master Clock Slave Clock Async Index 4 8 12 16 4 8 12 16 200 166 200 0 166 7 1 1 4 0 6 0 2 1 0 0 1 1 166 133 166 7 133 3 2 1 3 0 3 0 7 1 8 0 0 1...

Page 356: ...0 0 Using 1 cycle synchronizer 1 Using 1 2 cycle synchronizer 0 3 2 ASYNCINDEX REGISTER ASYNCINDEX R W 0XE340_0004 ASYNCINDEX Bit Description Reset Value Reserved 31 3 Reserved 0 ASYNC_INDEX 2 0 0 D0 clock D1 clock 1 1 W channel BW improve off 1 D0 clock D1 clock 6 5 W channel BW improve on 2 D0 clock D1 clock 5 4 W channel BW improve on 3 D0 clock D1 clock 4 3 W channel BW improve on 4 D0 clock D...

Page 357: ...he nFIQ interrupt and masks the interrupt source s from the interrupt controller on the non secure side of the system VIC Use the latter to generate nIRQ signal To generate nFIQ from the non secure interrupt sources the TZIC0 takes the nNSFIQIN signal from the non secure interrupt controller 1 1 FEATURES Supports 94 vectored IRQ interrupts Fixed hardware interrupts priority levels Programmable int...

Page 358: ...slave interface Nonvectored FIQ interrupt logic Vectored interrupt 0 Vectored interrupt 1 Vectored interrupt 31 FIQStatus 31 0 IRQStatus 31 0 IRQ vector address and priority logic IRQ VectAddr IRQ VectAddrIn 31 0 VectAddrOut 31 0 Control VICINTSOURCE 31 0 Other VIC VICIRQACK nVICSYNCEN VICVECTADDRV SFR AHB I F nVICFIQ nVICIRQ Figure 4 1 1 VICn Diagram ...

Page 359: ...S5PC100 USER S MANUAL REV1 0 VECTORED INTERRUPT CONTROLLER 4 1 3 Figure 4 1 2 VIC Daisy Chain ...

Page 360: ... TSADC EOC End of conversion Interrupt 86 SPDIF SPDIF Interrupt 85 PCM1 PCM1 Interrupt 84 PCM0 PCM0 Interrupt 83 AC97 AC97 Interrupt 82 I2S2 I2S 2 Interrupt 81 I2S1 I2S 1 Interrupt 80 I2S0 I2S 0 Interrupt 79 TVENC TV Encoder Interrupt 78 MFC MFC Interrupt 77 I2C1 for HDMI I2C1 Interrupt 76 HDMI HDMI Interrupt 75 Mixer Mixer Interrupt 74 3D 3D Graphic Controller Interrupt 73 2D 2D Interrupt 72 JPEG...

Page 361: ...upt 52 CAN1 CAN 1 Interrupt 51 CAN0 CAN 0 Interrupt 50 IrDA IrDA Interrupt 49 SPI2 SPI2 Interrupt 48 SPI1 SPI1 Interrupt 47 SPI0 SPI0 Interrupt 46 I2C0 I2C0 Interrupt 45 UART3 UART3 Interrupt 44 UART2 UART2 Interrupt 43 UART1 UART1 Interrupt 42 UART0 UART0 Interrupt 41 CFC CFCON Interrupt 40 NFC NFCON Interrupt 39 ONENAND OneNAND Interrupt 38 IEM_IEC IEM_IEC Interrupt 37 IEM_APC IEM_APC Interrupt ...

Page 362: ...MER2 Timer 2 Interrupt 22 TIMER1 Timer 1 Interrupt 21 TIMER0 Timer 0 Interrupt 20 PDMA1 Peri DMA Interrupt 19 PDMA0 Peri DMA Interrupt 18 MDMA M2M DMA Interrupt 17 BATF Battery Fault Interrupt 16 EINT 16_31 EXT_INT 16 31 15 EINT15 EXT_INT 15 14 EINT14 EXT_INT 14 13 EINT13 EXT_INT 13 12 EINT12 EXT_INT 12 11 EINT11 EXT_INT 11 10 EINT10 EXT_INT 10 9 EINT9 EXT_INT 9 8 EINT8 EXT_INT 8 7 EINT7 EXT_INT 7...

Page 363: ...0 USER S MANUAL REV1 0 VECTORED INTERRUPT CONTROLLER 4 1 7 3 FUNCTIONAL DESCRIPTION When user clears interrupt pending user must write 0 to all the VICADDRESS registers VIC0ADDRESS VIC1ADDRESS and VIC2ADDRESS ...

Page 364: ...x00000000 VIC0VECTADDR4 0xE400_0110 R W Vector Address 4 Register 0x00000000 VIC0VECTADDR5 0xE400_0114 R W Vector Address 5 Register 0x00000000 VIC0VECTADDR6 0xE400_0118 R W Vector Address 6 Register 0x00000000 VIC0VECTADDR7 0xE400_011C R W Vector Address 7 Register 0x00000000 VIC0VECTADDR8 0xE400_0120 R W Vector Address 8 Register 0x00000000 VIC0VECTADDR9 0xE400_0124 R W Vector Address 9 Register...

Page 365: ...ECTPRIORITY6 0xE400_0218 R W Vector Priority 6 Register 0xF VIC0VECTPRIORITY7 0xE400_021C R W Vector Priority 7 Register 0xF VIC0VECTPRIORITY8 0xE400_0220 R W Vector Priority 8 Register 0xF VIC0VECTPRIORITY9 0xE400_0224 R W Vector Priority 9 Register 0xF VIC0VECTPRIORITY10 0xE400_0228 R W Vector Priority 10 Register 0xF VIC0VECTPRIORITY11 0xE400_022C R W Vector Priority 11 Register 0xF VIC0VECTPRI...

Page 366: ...LID3 0xE400_0FFC R PrimeCell Identification Register bit 31 24 0xB1 VIC1IRQSTATUS 0xE410_0000 R IRQ Status Register 0x00000000 VIC1FIQSTATUS 0xE410_0004 R FIQ Status Register 0x00000000 VIC1RAWINTR 0xE410_0008 R Raw Interrupt Status Register VIC1INTSELECT 0xE410_000C R W Interrupt Select Register 0x00000000 VIC1INTENABLE 0xE410_0010 R W Interrupt Enable Register 0x00000000 VIC1INTENCLEAR 0xE410_00...

Page 367: ...000 VIC1VECTADDR23 0xE410_015C R W Vector Address 23 Register 0x00000000 VIC1VECTADDR24 0xE410_0160 R W Vector Address 24 Register 0x00000000 VIC1VECTADDR25 0xE410_0164 R W Vector Address 25 Register 0x00000000 VIC1VECTADDR26 0xE410_0168 R W Vector Address 26 Register 0x00000000 VIC1VECTADDR27 0xE410_016C R W Vector Address 27 Register 0x00000000 VIC1VECTADDR28 0xE410_0170 R W Vector Address 28 Re...

Page 368: ... W Vector Priority 25 Register 0xF VIC1VECTPRIORITY26 0xE410_0268 R W Vector Priority 26 Register 0xF VIC1VECTPRIORITY27 0xE410_026C R W Vector Priority 27 Register 0xF VIC1VECTPRIORITY28 0xE410_0270 R W Vector Priority 28 Register 0xF VIC1VECTPRIORITY29 0xE410_0274 R W Vector Priority 29 Register 0xF VIC1VECTPRIORITY30 0xE410_0278 R W Vector Priority 30 Register 0xF VIC1VECTPRIORITY31 0xE410_027C...

Page 369: ... R W Vector Address 7 Register 0x00000000 VIC2VECTADDR8 0xE420_0120 R W Vector Address 8 Register 0x00000000 VIC2VECTADDR9 0xE420_0124 R W Vector Address 9 Register 0x00000000 VIC2VECTADDR10 0xE420_0128 R W Vector Address 10 Register 0x00000000 VIC2VECTADDR11 0xE420_012C R W Vector Address 11 Register 0x00000000 VIC2VECTADDR12 0xE420_0130 R W Vector Address 12 Register 0x00000000 VIC2VECTADDR13 0x...

Page 370: ...10 0xE420_0228 R W Vector Priority 10 Register 0xF VIC2VECTPRIORITY11 0xE420_022C R W Vector Priority 11 Register 0xF VIC2VECTPRIORITY12 0xE420_0230 R W Vector Priority 12 Register 0xF VIC2VECTPRIORITY13 0xE420_0234 R W Vector Priority 13 Register 0xF VIC2VECTPRIORITY14 0xE420_0238 R W Vector Priority 14 Register 0xF VIC2VECTPRIORITY15 0xE420_023C R W Vector Priority 15 Register 0xF VIC2VECTPRIORI...

Page 371: ...ion Register bit 7 0 0x92 VIC2PERIPHID1 0xE420_0FE4 R Peripheral Identification Register bit 15 9 0x11 VIC2PERIPHID2 0xE420_0FE8 R Peripheral Identification Register bit 23 16 0x04 VIC2PERIPHID3 0xE420_0FEC R Peripheral Identification Register bit 31 24 0x00 VIC2PCELLID0 0xE420_0FF0 R PrimeCell Identification Register bit 7 0 0x0D VIC2PCELLID1 0xE420_0FF4 R PrimeCell Identification Register bit 15...

Page 372: ...xE500_0FF4 R 0x000000F0 TZIC0PCellID2 0xE500_0FF8 R 0x00000005 TZIC0PCellID3 0xE500_0FFC R Identification Registers 0x000000B1 TZIC1FIQStatus 0xE510_0000 R FIQ Status Register 0x00000000 TZIC1RawIntr 0xE510_0004 R Raw Interrupt Status Register TZIC1IntSelect 0xE510_0008 R W Interrupt Select Register 0x00000000 TZIC1FIQEnable 0xE510_000C R W FIQ Enable Register 0x00000000 TZIC1FIQENClear 0xE510_001...

Page 373: ... R W FIQ Bypass Register 0x00000000 TZIC2Protection 0xE520_0018 R W Protection Register 0x00000000 TZIC2Lock 0xE520_001C W Lock Enable Register TZIC2LockStatus 0xE520_0020 R Lock Status Register 0x00000001 TZIC2PeriphID0 0xE520_0FE0 R 0x00000090 TZIC2PeriphID1 0xE520_0FE4 R 0x00000018 TZIC2PeriphID2 0xE520_0FE8 R 0x00000004 TZIC2PeriphID3 0xE520_0FEC R Peripheral Identification Registers 0x0000000...

Page 374: ...n Reset Value FIQStatus 31 0 Shows the status of the FIQ interrupts after masking by the VICINTENABLE and VICINTSELECT Registers 0 Interrupt is inactive 1 Interrupt is active There is one bit of the register for each interrupt source 0x00000000 4 3 RAW INTERRUPT STATUS REGISTER VICRAWINTR R ADDRESS 0XE400_0008 0XE410_0008 0XE420_0008 VICRAWINTR Bit Description Reset Value RawInterrupt 31 0 Shows t...

Page 375: ...Enables the interrupt request lines which allows the interrupts to reach the processor Read 0 Disables Interrupt 1 Enables Interrupt Use this register to enable interrupt The VICINTENCLEAR Register must be used to disable the interrupt enable Write 0 No effect 1 Enables Interrupt On reset all interrupts are disabled There is one bit of the register for each interrupt source 0x00000000 4 6 INTERRUP...

Page 376: ...Value SoftIntClear 31 0 Clears corresponding bits in the VICSOFTINT Register 0 No effect 1 Disables Software interrupt in the VICSOFTINT Register There is one bit of the register for each interrupt source 4 9 PROTECTION ENABLE REGISTER VICPROTECTION R W ADDRESS 0XE400_0020 0XE410_0020 0XE420_0020 VICPROTECTION Bit Description Reset Value Reserved 31 1 Reserved read as 0 do not modify 0x0 Protectio...

Page 377: ...ad as 0 do not modify 0x0 SWPriorityMask 15 0 Controls software masking of the 16 interrupt priority levels 0 Interrupt priority level is masked 1 Interrupt priority level is not masked Each bit of the register is applied to each of the 16 interrupt priority levels 0xFFFF 4 12 VECTOR ADDRESS REGISTERS VICVECTADDR 0 31 R W ADDRESS 0XE400_0100 017C 0XE410_0100 017C 0XE420_0100 017C VICVECTADDR 0 31 ...

Page 378: ...ck as 0x1 0x1 Partnumber1 3 0 These bits read back as 0x1 0x1 4 16 VICPERIPHID2 REGISTER VICPERIPHID2 R ADDRESS 0XE400_0FE8 0XE410_0FE8 0XE420_0FE8 VICPERIPHID2 Bit Description Reset Value 31 8 Reserved read as 0 do not modify 0x0 Revision 7 4 These bits read back as the revision number which can be between 0 and 15 0x0 Designer1 3 0 These bits read back as 0x4 0x4 4 17 VICPERIPHID3 REGISTER VICPE...

Page 379: ...ESS 0XE400_0FF8 0XE410_0FF8 0XE420_0FF8 VICPCELLID2 Bit Description Reset Value 31 8 Reserved read as 0 do not modify 0x0 VICPCellID2 7 0 These bits read back as 0x05 0x05 4 21 VICPCELLID3 REGISTER VICPCELLID3 R ADDRESS 0XE400_0FFC 0XE410_0FFC 0XE420_0FFC VICPCELLID3 Bit Description Reset Value 31 8 Reserved read as 0 do not modify 0x0 VICPCellID3 7 0 These bits read back as 0xB1 0xB1 4 22 FIQ STA...

Page 380: ...elects whether the interrupt source generates an FIQ interrupt or passes straight through to TZICIRQOUT 0 Interrupt passes through to TZICIRQOUT 1 Interrupt is available for FIQ generation 0x00000000 4 25 FIQ ENABLE REGISTER TZICFIQENABLE R W ADDRESS 0XE500_000C 0XE510_000C 0XE520_000C TZICFIQEnable Bit Description Reset Value FIQEnable 31 0 Enables the FIQ selected interrupt lines allowing the in...

Page 381: ... 4 28 PROTECTION REGISTER TZICPROTECTION R W ADDRESS 0XE500_0018 0XE510_0018 0XE520_0018 TZICProtection Bit Description Reset Value 31 1 Read undefined Write as 0 0x0 Protection 0 Enables or disables protected register access 0 Disables Protection mode 1 Enables Protection mode If enabled you can only make privileged mode access reads and writes to the TZIC This register is accessed in privileged ...

Page 382: ...0 TZICPeriphID0 Bit Description Reset Value 31 8 Read undefined 0x0 Partnumber0 7 0 These bits read back as 0x90 0x90 4 32 PERIPHERAL IDENTIFICATION REGISTER TZICPERIPHID1 R ADDRESS 0XE500_0FE4 0XE510_0FE4 0XE520_0FE4 TZICPeriphID1 Bit Description Reset Value 31 8 Read undefined 0x0 Designer0 7 4 These bits read back as 0x1 0x1 Partnumber1 3 0 These bits read back as 0x8 0x8 4 33 PERIPHERAL IDENTI...

Page 383: ...These bits read back as 0x0D 0x0D 4 36 IDENTIFICATION REGISTER TZICPCELLID1 R ADDRESS 0XE500_0FF4 0XE510_0FF4 0XE520_0FF4 TZICPCellID1 Bit Description Reset Value 31 8 Read undefined 0x0 TZICPCellID1 7 0 These bits read back as 0xF0 0xF0 4 37 IDENTIFICATION REGISTER TZICPCELLID2 R ADDRESS 0XE500_0FF8 0XE510_0FF8 0XE520_0FF8 TZICPCellID2 Bit Description Reset Value 31 8 Read undefined 0x0 TZICPCell...

Page 384: ...ne stage for low latency QoS scheme to ensure low latency for some applications An advanced scheduler which enables efficient out of order operations Excellent chip bank interleaving and memory interrupting Adapts to various low power schemes to reduce the dynamic and static current of memory Outstanding exclusive accesses Bank selective precharge policy 1 1 synchronous operation between AXI bus a...

Page 385: ...erface block saves the bus transactions for memory access that come from the AXI slave port to the command queue Additionally it saves the write data to the write buffer or sends the read data to the Master via the AXI bus It also acts as a read FIFO if AXI Master is not ready and has an APB interface for special function registers direct commands and an AXI low power channel interface The Schedul...

Page 386: ...ry chips also set the MemConfig1 register 8 Set the PrechConfig and PwrdnConfig registers 9 Set the TimingAref TimingRow TimingData and TimingPower registers according to memory AC parameters 10 If QoS scheme is required set the QosControl0 7 and QosConfig0 7 registers 11 You must wait for the PhyStatus0 ctrl_locked bit fields to change to 1 Check whether PHY DLL is locked 12 PHY DLL compensates t...

Page 387: ... 11 You must wait for the PhyStatus0 ctrl_locked bit fields to change to 1 Check whether PHY DLL is locked 12 PHY DLL compensates the changes of delay amount caused by Process Voltage and Temperature PVT variation during memory operation Therefore it should not be off for reliable operation It can be off except runs at low frequency If off mode is used set the PhyControl0 ctrl_force bit field to c...

Page 388: ...ion It can be off except runs at low frequency If off mode is used set the PhyControl0 ctrl_force bit field to correct value according to the PhyStatus0 ctrl_lock_value 9 2 bit field for fix delay amount Clear the PhyControl0 ctrl_dll_on bit field to turn off PHY DLL 13 Confirm whether stable clock is issued minimum 200us after power on 14 Issue a NOP command using the DirectCmd register to assert...

Page 389: ...XI offset address The AXI base address activates the appropriate memory chip select and the AXI offset address is mapped to a memory address according to the bank row column number and data width set by the MemConfig register There are two ways to map the AXI offset address as shown below 1 Linear mapping 2 Interleaved mapping 2 2 1 Linear Mapping bank row column widt h AXI base address Linear map...

Page 390: ...own bank2 rown bank3 rown row density Figure 5 1 3 Interleaved Address Mapping As shown in Figure 5 1 3 the interleaved mapping method maps the AXI address in the order of row bank column and width The difference between the linear mapping method and the interleaved method is that the bank and row order is different For accesses beyond a row size interleaved mapping accesses a different bank There...

Page 391: ...e precharge power down state and It is selected by MEMCONTROL dpwrdn_type bit 1 Active precharge power down mode Enter power down without considering whether there is a row open or not 2 Force precharge power down mode Enter power down after closing all banks If a new AXI transaction enters the controller the controller automatically wakes up the memory device from power down state and executes in...

Page 392: ... and other applications to a bank that uses a close page auto precharge policy Open Page Policy After a READ or WRITE the accessed row is left open Close Page Auto Precharge Policy Right after a READ or WRITE command the controller issues an auto precharge to the bank 2 4 2 Timeout Precharge If a certain bank uses an open page policy the row is left open after a data access If this happens and the...

Page 393: ...onfigurable QoSControls applicable to Read data transfers which have independent qos_masks that mask the ARID from one bit up to the ARID width All 8 QoSControls are either enabled or disabled 1 If the command is received via the AXI bus the ARID is masked by the qos_masks QoSConfig n qos_mask from the 8 QoSControls that are enabled 2 The masked results are then compared to the qos_ids QoSConfig n...

Page 394: ...ad Data Capture DDR2 zero delay RL 3 rd_fetch 1 Figure 5 1 5 is for DDR2 having an internal DLL An internal DLL exists which allows it to send the data after an exact amount of read latency If we assume there are minimal or no board PHY input delay if sampling the negedge Q1 Q3 sampling since the data gets saved into the PHY read data input FIFO the controller sends the read data to the AXI read c...

Page 395: ... Capture LPDDR LPDDR2 zero delay RL 3 rd_fetch 1 An LPDDR LPDDR2 does not have an internal DLL Without an internal DLL as you may see in Figure 5 1 7 the data is sent out after tDQSCK before the read latency is over Even if we assume zero delay since tDQSCK becomes relatively large in high frequencies the read fetch cycle should be set to one Delay T0 T1 T2 T3 T4 T5 T6 CK DQS DQ SDRAM command Q0 Q...

Page 396: ... LPDDR2 low frequency RL 3 rd_fetch 0 tDQSCK Delay is relatively small compared to the clock period during low frequencies as shown in Figure 5 1 9 In this situation negedge sampling happens before read latency and therefore read fetch is set to zero To calculate the LPDDR LPDDR2 rd_fetch value rd_fetch LPDDR LPDDR2 INT 1 Delay 0 5T 0 25T T INT Delay T 0 25 Delay board delay PHY input delay T cloc...

Page 397: ...R_RASn O Row Address Selection Xm1RASn dedicated DDR_CASn O Column Address Selection Xm1CASn dedicated DDR_WEn O Write Enable Xm1WEn dedicated DDR_A 31 0 I O Memory Address Bus Xm1ADDR 31 0 dedicated DDR_D 31 0 I O Memory Data Bus Xm1DATA 31 0 dedicated DDR_DQM 3 0 O Write Masking Per Byte Xm1DQM 3 0 dedicated DDR_DQS 3 0 I O Data Strobe Signal Per Byte Xm1DQS 3 0 dedicated DDR_DQSn 3 0 I O Data S...

Page 398: ... ADDR_8 ADDR_8 ADDR_8 ADDR_8 Xm1ADDR 9 ADDR_9 ADDR_9 ADDR_9 CA_9 ADDR_9 ADDR_9 ADDR_9 ADDR_9 ADDR_9 Xm1ADDR 10 ADDR_10 ADDR_10 ADDR_10 ADDR_10 ADDR_10 ADDR_10 ADDR_10 ADDR_10 Xm1ADDR 11 ADDR_11 ADDR_11 ADDR_11 ADDR_11 ADDR_11 ADDR_11 ADDR_11 ADDR_11 Xm1ADDR 12 ADDR_12 ADDR_12 ADDR_12 ADDR_12 ADDR_12 ADDR_12 ADDR_12 Xm1ADDR 13 ADDR_13 ADDR_13 ADDR_13 Xm1ADDR 14 BA_0 BA_0 BA_0 BA_0 BA_0 BA_0 BA_0 BA...

Page 399: ...tatus Register 0x00000000 AREFSTATUS 0xE600_0050 R Counter Status Register for Auto Refresh 0x0000FFFF MRSTATUS 0xE600_0054 R Memory Mode Registers Status Register 0x00000000 PHYTEST0 0xE600_0058 R W PHY Test Register 0 0x00000000 PHYTEST1 0xE600_005C R PHY Test Register 1 0x00000000 QOSCONTROL0 0xE600_0060 R W Quality of Service Control Register 0 0x00000000 QOSCONFIG0 0xE600_0064 R W Quality of ...

Page 400: ...able latency of read data coming from memory devices by tDQSCK variation or the board flying time The read fetch delay of PHY read FIFO must be controlled by this parameter The controller will fetch read data from PHY after read_latency n mclk cycles Refer to Section 2 56 Read Data Capture R W 0x1 Reserved 11 Should be zero 0x0 dq_swap 10 DQ Swap 0x0 Disable 0x1 Enable If enabled the controller re...

Page 401: ...p automatically for continuous reads from two different memory devices R W 0x0 aref_en 5 Auto Refresh Counter 0x0 Disable 0x1 Enable Enable this to decrease the auto refresh counter by 1 at the rising edge of the mclk R W 0x0 out_of 4 Out of Order Scheduling 0x0 Disable 0x1 Enable The embedded scheduler enables out of order operation to improve SDRAM utilization R W 0x1 clk_ratio 3 1 Clock Ratio o...

Page 402: ...erved R W 0x2 mem_type 11 8 Type of Memory 0x0 Reserved 0x1 LPDDR 0x2 LPDDR2 0x3 Reserved 0x4 DDR2 0x5 0xf Reserved R W 0x1 add_lat_pall 7 6 Additional Latency for PALL 0x0 0 cycle 0x1 1 cycle 0x2 2 cycle 0x3 3 cycle If all banks precharge command is issued the latency of precharging will be tRP add_lat_pall R W 0x0 dsref_en 5 Dynamic Self Refresh 0x0 Disable 0x1 Enable Refer to Section 2 3 3 Dyna...

Page 403: ... 4 2 Timeout Precharge dpwrdn_type 3 2 Type of Dynamic Power Down 0x0 Active Precharge power down 0x1 Force precharge power down 0x2 0x3 Reserved Refer to Section 2 3 2 Dynamic Power Down R W 0x0 dpwrdn_en 1 Dynamic Power Down 0x0 Disable 0x1 Enable R W 0x0 clk_stop_en 0 Dynamic Clock Control 0x0 Always running 0x1 Stops during idle periods Refer to Section 2 3 4 Clock Stop R W 0x0 ...

Page 404: ...omparison This bit field is used to check whether accessed address mask address is equal to base address For example if AXI base address of memory chip0 is 0x2000_0000 and AXI Base address mask is 0xF8 then memory chip0 has an address range of 0x2000_0000 0x27FF_FFFF R W 0xF8 chip_map 15 12 Address Mapping Method AXI to Memory 0x0 Linear bank row column width 0x1 Interleaved row bank column width ...

Page 405: ...d is used to check whether accessed address mask address is equal to base address For example if chip_mask 0xF8 then AXI offset address becomes 0x0000_0000 0x07FF_FFFF If AXI base address of memory chip1 is 0x2800_0000 then memory chip1 has an address range of 0x2800_0000 0x2FFF_FFFF R W 0xF8 chip_map 15 12 Address Mapping Method AXI to memory 0x0 Linear bank row column width 0x1 Interleaved row b...

Page 406: ...ing a direct command You must disable dynamic power down dynamic self refresh and force precharge function MemControl register MRS EMRS and MRR commands should be issued if all banks are in idle state If MRS EMRS and MRR is issued to LPDDR2 the CA pins must be mapped as follows MA 7 0 cmd_addr 1 0 cmd_bank 2 0 cmd_addr 12 10 OP 7 0 cmd_addr 9 2 R W 0x0 Reserved 23 21 Should be zero 0x0 cmd_chip 20...

Page 407: ...ive Policy 0x0 Open page policy 0x1 Close page auto precharge policy chip1_policy n n is the bank number of chip1 Open Page Policy After a READ or WRITE the row accessed before is left open Close Page Auto Precharge Policy Right after a READ or WRITE command memory devices automatically precharges the bank This is a bank selective precharge policy For example if chip1_policy 2 is 0x0 bank2 of chip...

Page 408: ... read feedback 0x5 Board PHY internal read feedback 0x6 Board PHY internal write feedback 0x7 Reserved R W 0x0 Reserved 4 Should be zero ctrl_dfdqs 3 Differential DQS If enabled PHY generates differential DQS out signals for write command and receives differential DQS input signals for read command This function is used in case of DDR2 LPDDR2 R W 0x0 ctrl_half 2 DLL Low Speed HIGH active signal to...

Page 409: ... up PLL lock ctrl_clock ctrl_flock ctrl_lock_value DLL Lock Memory Initialization Memory Acess Refresh CMD Refresh CMD Refresh CMD DLL Lock Start DLL Locked Read Write Refresh Period DLL on DLL off Write ctrl_start_point value Write ctrl_inc value Figure 5 1 10 DLL Lock Procedure The case of frequency scaling DLL should be turned off during the clock change time ...

Page 410: ...os 0x1 Pull down all If CAS or read data latency is 2 this register must not set be to 0x0 0x0 ctrl_offsetc 14 8 Delay Offset for DQS Cleaning Gate offset amount for DDR If this field is fixed this should not be changed during operation This value is valid after ctrl_resync becomes HIGH and LOW ctrl_offsetc 6 1 tFS fine step delay GATEout delay amount ctrl_offsetc 5 0 x tFS ctrl_offsetc 6 0 GATEou...

Page 411: ...110 T 2 180 shift 0x111 T 360 shift Recommended values according to memory type 0x100 when LPDDR LPDDR2 0x110 when DDR2 R W 0x0 NOTE DQS CLEANING SCHEME Use DQS cleaning to remove high Z state of DQS PHY Controller FF D Q CK delay line to each data slice GATEO GATEI ctrl _ gate DQS data _ slice IO IO IO io _ gate _ out io _ gate _ in io _ dqs _ in I O IO IO Memory IO ADCT CMD IO CK CK B IO IO IO D...

Page 412: ...value 9 0 tFS can beis calculated If ctrl_half 0 tFS tCK ctrl_lock_value 9 0 If ctrl_half 1 tFS tCK 0 5 ctrl_lock_value 9 0 ctrl_shiftc controls PVT independent delay amount tF and ctrl_offsetc controls PVT dependent delay amount tV Delay line programming value tDL tAC 2 tB tC tD tDL tF ctrl_shiftc 2 0 tV ctrl_offsetc 6 0 If ctrl_shiftc 2 0 is 3 b100 tF is Tperiod 8 0 9375ns If tCK is 7 5ns If ctr...

Page 413: ...0 3 b100 T 8 ctrl_offsetc 6 0 6 h0 ctrl_offsetc 6 1 b1 ctrl_offsetc 5 0 6 h4 ctrl_offsetc 6 1 b0 ctrl_offsetc 5 0 6 h4 D0 D1 D2 D3 ctrl_offsetc 6 1 b0 Cleaned DQS T 8 ctrl_offsetc 5 0 x tFS T 8 ctrl_offsetc 5 0 x tFS tFS Fine Step Delay burst length 2 burst length 2 4 8 16 Figure 5 1 13 DQS Cleaning for LPDDR if tAC max 1 TP TP Clock Period DQ GATEin T 2 shift T 2 T 2 ctrl_offsetc 5 0 xtFS ctrl_of...

Page 414: ...omes HIGH and LOW rd_slice_2 offset amount ctrl_offset2 6 1 tFS fine step delay 90 delay amount ctrl_offset0 5 0 x tFS ctrl_offset2 6 0 90 delay amount ctrl_offset0 5 0 x tFS R W 0x0 Reserved 15 Should be zero 0x0 ctrl_offset1 14 8 This field is for debug purpose If this field is fixed this should not be changed during operation This value is valid after ctrl_resync becomes HIGH and LOW rd_slice_1...

Page 415: ...cycles If the command queue is empty for n 1 cycles the controller forces the memory device into self refresh state Refer to Section 2 3 3 Dynamic Self Refresh R W 0xFFFF Reserved 15 8 Should be zero 0x0 dpwrdn_cyc 7 0 Number of Cycles for Dynamic Power Down Entry 0xn n aclk cycles If the command queue is empty for n 1 cycles the controller forces the memory device into active precharge power down...

Page 416: ...tive Auto refresh command period in cycles t_rft T mclk should be greater than or equal to the minimum value of memory tRFC R W 0xF t_rrd 23 20 Active bank A to Active bank B delay in cycles t_rrd T mclk should be greater than or equal to the minimum value of memory tRRD R W 0x2 t_rp 19 16 Precharge command period in cycles t_rp T mclk should be greater than or equal to the minimum value of memory...

Page 417: ...ernal read to Precharge command delay in cycles t_rtp T mclk should be greater than or equal to the minimum value of memory tRTP t_rtp must be 0x1 in case of JEDEC LPDDR R W 0x1 cl 19 16 CAS Latency for LPDDR DDR DDR2 in cycles cl should be greater than or equal to the minimum value of memory CL R W 0x3 Reserved 15 12 Should be zero 0x0 wl 11 8 Write data latency for only LPDDR2 in cycles wl shoul...

Page 418: ...T mclk should be greater than or equal to the minimum value of memory tXSR In case of DDR DDR2 this value should be greater than or equal to the minimum value of memory tXSRD R W 0x1B t_xp 15 8 Exit power down to next valid command delay in cycles t_xp T mclk should be greater than or equal to the minimum value of memory tXP R W 0x4 t_cke 7 4 CKE minimum pulse width minimum power down mode duratio...

Page 419: ...e 1 0 control value for fine lock R 0x0 Reserved 3 Should be zero 0x0 ctrl_locked 2 DLL Lock 0 Unlocks DLL 1 Locks DLL R 0x0 ctrl_flock 1 Fine Lock Information It is indicated that DLL is locked with fine resolution phase offset error is less than 80ps R 0xX ctrl_clock 0 Coarse Lock Information It is indicated that DLL changes step delays of the delay line and phase offset error is less than 160ps...

Page 420: ... current state of bank 4 of memory chip0 R 0x0 bank3_state 15 12 The current state of bank 3 of memory chip0 R 0x0 bank2_state 11 8 The current state of bank 2 of memory chip0 R 0x0 bank1_state 7 4 The current state of bank 1 of memory chip0 R 0x0 bank0_state 3 0 The current state of bank 0 of memory chip0 0x0 Idle precharged 0x1 MRS EMRS 0x2 Deep power down 0x3 Self refresh 0x4 Auto refresh 0x5 P...

Page 421: ...e current state of bank 4 of SDRAM chip1 R 0x0 bank3_state 15 12 The current state of bank 3 of SDRAM chip1 R 0x0 bank2_state 11 8 The current state of bank 2 of SDRAM chip1 R 0x0 bank1_state 7 4 The current state of bank 1 of SDRAM chip1 R 0x0 bank0_state 3 0 The current state of bank 0 of SDRAM chip1 0x0 Idle precharged 0x1 MRS EMRS 0x2 Deep power down 0x3 Self refresh 0x4 Auto refresh 0x5 Prech...

Page 422: ...t_ref if this becomes zero R 0xFFFF 4 2 20 Memory Mode Registers Status Register MrStatus R Address 0xE600_0054 MRSTATUS Bit Description R W Reset Value Reserved 31 8 Should be zero 0x0 mr_status 7 0 Mode Registers Status R 0x0 4 2 21 PHY Test Register 0 PhyTest0 R W Address 0xE600_0058 PHYTEST0 Bit Description R W Reset Value ctrl_fb_cnt4 31 24 Count Value for Control Channel R 0x0 Reserved 23 21...

Page 423: ...t value for data0 channel R 0x0 4 2 23 Quality of Service Control Register n QosControl n R W Address 0xE600_0060 8n n 0 7 integer QOSCONTROLn Bit Description R W Reset Value Reserved 31 28 Should be zero 0x0 qos_cnt 27 16 QoS Cycles 0xn n aclk cycles The matched ARID uses this value for its timeout counters instead of ConControl timeout_cnt R W 0x0 qos_en 0 QoS Enable 0x0 Disable 0x1 Enable If th...

Page 424: ...the same QoS the 4th and 5th bits must be masked Therefore qos_mask would be 0b1111100111 R W 0x0 qos_id 15 0 QoS ID This is used to compare with the masked ARID to check whether its timeout counter should be used for QoS After applying the qos_mask to these ARID it is compared with qos_id The qos_id must be 0b001100_0000 using the example above Comparing the masked ID if the result is equal to th...

Page 425: ...000_0011_0100 Reserved 12 b0000_0011_1000 Cacheable linefill Linefill into data cache ARM R W 12 b0000_0011_1100 Cacheable linefill Linefill into instruction cache L2 Noncacheable 12 b0000_0000_0001 DMA channel0 thread 12 b0000_0001_0001 DMA channel1 thread 12 b0000_0010_0001 DMA channel2 thread 12 b0000_0011_0001 DMA channel3 thread 12 b0000_0100_0001 DMA channel4 thread 12 b0000_0101_0001 DMA ch...

Page 426: ...0 USBHost 1 USBOTG R W 12 b0000_1010_1110 USBOTG 12 b0000_1100_1110 DMA channel0 thread 12 b0001_1100_1110 DMA channel1 thread 12 b0010_1100_1110 DMA channel2 thread 12 b0011_1100_1110 DMA channel3 thread 12 b0100_1100_1110 DMA channel4 thread 12 b0101_1100_1110 DMA channel5 thread 12 b0110_1100_1110 DMA channel6 thread 12 b0111_1100_1110 DMA channel7 thread PDMA0 R W 12 b1000_1100_1110 DMA manage...

Page 427: ...h PROM SRAM memory From now on we refer this controller as SMC SMC supports 6 bank memory Maximum 128MB 1 1 FEATURE Supports SRAM various ROMs and NOR flash memory Supports only 8 or 16 bit data bus Address space Maximum 4MB per Bank Supports 6 banks Fixed memory bank start address External wait to extend the bus cycle Support byte and half word access for external memory ...

Page 428: ...OLLER S5PC100 USER S MANUAL REV1 0 5 2 2 1 2 BLOCK DIAGRAM SROM DECODER SFR CONTROL STATE MACHINE SROM I F SINGAL GENERATO N AHB I F for SROM SFR AHB I F for SROM MEM SROM MEM I F DATA PATH Figure 5 2 1 SMC Block Diagram ...

Page 429: ... each memory bank is enabled the nOE duration should be prolonged by the external nWAIT pin while the memory bank is active nWAIT is checked from tacc 1 nOE will be deasserted at the next clock after sampling nWAIT is high The nWE signal have the same relation with nOE tRC Tacs Tcos Tacc 4 HCLK ADDR nGCS nOE nWAIT DATA R Delayed Sampling nWAIT Figure 5 2 2 SMC Controller nWAIT Timing Diagram ...

Page 430: ... nOE Tcos Tacp DATA 1 ADDRESS 1 Tacs 2 cycle Tacp 2 cycle Tcos 2 cycle Tcoh 2 cycle Tacc 3 cycle Tcah 2 cycle Figure 5 2 3 SMC Controller Read Timing Diagram HCLK ADDR nGCS DATA W Tacs Tacc Tcoh Tcah ADDRESS nWE Tcos DATA Tacs 2 cycle Tacp don care Tcos 2 cycle Tcoh 2 cycle Tacc 3 cycle Tcah 2 cycle Figure 5 2 4 SMC Controller Write Timing Diagram ...

Page 431: ...Output Bank Selection Signal Xm0CSn 5 0 muxed SMC_ADDR 20 0 Output Address bus Xm0ADDR 20 0 muxed SMC_OEn Output Output Enable Xm0OEn muxed SMC_WEn Output Write Enable Xm0WEn muxed SMC_Ben 1 0 Output Byte write Enable Byte Enable Xm0BEn muxed SMC_DATA 15 0 In Out Data bus Xm0DATA 15 0 muxed SMC_WAITn Input Wait input Xm0WAITn muxed ...

Page 432: ...x00000009 SMC_BC0 0xE700_0004 R W SMC Bank0 Control Register 0x000F0000 SMC_BC1 0xE700_0008 R W SMC Bank1 Control Register 0x000F0000 SMC_BC2 0xE700_000C R W SMC Bank2 Control Register 0x000F0000 SMC_BC3 0xE700_0010 R W SMC Bank3 Control Register 0x000F0000 SMC_BC4 0xE700_0014 R W SMC Bank4 Control Register 0x000F0000 SMC_BC5 0xE700_0018 R W SMC Bank5 Control Register 0x000F0000 ...

Page 433: ... DataWidth5 20 Data bus width control for Memory Bank5 0 8 bit 1 16 bit 0 ByteEnable4 19 nWBE nBE for UB LB control for Memory Bank4 0 Not using UB LB XrnWBE 1 0 is dedicated nWBE 1 0 1 Using UB LB XrnWBE 1 0 is dedicated nBE 1 0 0 WaitEnable4 18 Enables Wait for Memory Bank4 0 Disables WAIT 1 Enables WAIT 0 AddrMode4 17 Select SMC ADDR Base for Memory Bank4 0 SMC_ADDR is Half word base address SR...

Page 434: ...e2 9 Select SMC ADDR Base for Memory Bank2 0 SMC_ADDR is Half word base address SRAM_ADDR 20 0 HADDR 21 1 1 SMC_ADDR is byte base address SMC_ADDR 20 0 HADDR 20 0 Note If DataWidth0 is 0 SMC_ADDR is byte base address Ignored this bit 0 DataWidth2 8 Data bus width control for Memory Bank2 0 8 bit 1 16 bit 0 ByteEnable1 7 nWBE nBE for UB LB control for Memory Bank1 0 Not using UB LB XrnWBE 1 0 is de...

Page 435: ...0 is dedicated nBE 1 0 1 WaitEnable0 2 Wait enable control for Memory Bank0 0 Disables WAIT 1 Enables WAIT 0 AddrMode0 1 Select SMC ADDR Base for Memory Bank0 0 SMC_ADDR is Half word base address SRAM_ADDR 20 0 HADDR 21 1 1 SMC_ADDR is byte base address SMC_ADDR 20 0 HADDR 20 0 Note If DataWidth0 is 0 SMC_ADDR is byte base address This bit is ignored 0 DataWidth0 0 Data bus width control for Memor...

Page 436: ...Bit Description Reset Value Tacs 31 28 Address set up before nGCS 0000 0 clock 0001 1 clocks 0010 2 clocks 0011 3 clocks 1100 12 clocks 1101 13 clocks 1110 14 clocks 1111 15 clocks Note More 1 2 cycles according to bus i f status 0000 Tcos 27 24 Chip selection set up before nOE 0000 0 clock 0001 1 clocks 0010 2 clocks 0011 3 clocks 1100 12 clocks 1101 13 clocks 1110 14 clocks 1111 15 clocks 0000 R...

Page 437: ... 1 clocks 0010 2 clocks 0011 3 clocks 1100 12 clocks 1101 13 clocks 1110 14 clocks 1111 15 clocks Note More 1 2 cycles according to bus i f status 0000 Tacp 7 4 Succesive access cycle 0000 0 clock 0001 1 clocks 0010 2 clocks 0011 3 clocks 1100 12 clocks 1101 13 clocks 1110 14 clocks 1111 15 clocks 0000 Reserved 3 2 Reserved Reserved 1 0 Should be zero 00 ...

Page 438: ...imum performance Asynchronous FIFOs between the controller and the system interface for speed matching Read and write protocols implemented with bus interface read and write commands Erase commands implemented through address mapping Programmable sized burst transfers Support for multiple memory devices in the OneNAND family with a single bus interface protocol Supported transfer types are INCRx t...

Page 439: ... is programmed with 32 word burst length any attempt to change the controller from Main area mode triggers an interrupt and the change is ignored AMBA transactions should be of the same burst type throughout a page During page transfers the entire page must be transferred to memory or to the AMBA bus before the dataram buffer is released for another transaction Register accesses must use a transfe...

Page 440: ...tem interface gets AHB bus clock HCLK Flash controller core gets two flash clocks SCLK_ONENAND and SCLK_ONENAND2 Frequency of SCLK_ONENAND should be double of SCLK_ONENAND2 which is supplied to OneNAND flash memory Set the frequency ratio in the SFR of the System Controller Refer to Chapter 2 3 Clock Controller for clock ratio settings If you change the clock frequency ratio you should follow the ...

Page 441: ...mine the length of time in clock cycles that the controller must wait before capturing data from the flash devices on reads or before sending data to the flash devices on writes Access clocks are used for asynchronous operations The value should be based on the flash clock period based on the following formula As an example if the flash device is running at 83 MHz the clock period would be 12 048 ...

Page 442: ...es into the controller registers If you want to skip Cold_Reset_Delay counting Write 0x00 to Cold_Reset_Delay SFR To configure the system to use the flash memory devices you must read the following controller registers manufacturer_id device_id version_id data_buffer_size boot_buffer_size amount_of_buffers technology 2 Auto Configuration After performing the power on sequence and enable special cl...

Page 443: ...used and the controller is not in the middle of a read modify write sequence only AHB read transactions are appropriate If a MAP00 command is received with an AHB write in this case an interrupt is triggered and the command is ignored 2 5 2 MAP01 The MAP01 interface is used for block data transfers to and from the memory device to a specific sector of the flash array Since the controller only supp...

Page 444: ...to operate special functions of the memory device For writes the data is not transferred to the memory device but is used to manipulate the controller For reads the data is not information from the memory device but indicates status of the controller There are several operations executed through the MAP10 commands such as erase lock unlock lock tight copy back OTP access spare area access verify r...

Page 445: ...t control of the address specified without any translation through the controller The address MAPused is dependent on the memory device being used Data written or read is written to or read from the memory device itself This command type is used to debug or test the memory device MAP11 and MAP10 can not share INT pin If the system use MAP11 and MAP10 in same time replace external interrupt instead...

Page 446: ...start address Write 0x000d Set lock tight end address initiate the lock Write 0x000e Unlock the entire memory array Write 0x0010 Load page to the RMW buffer Write 0x0011 Write RMW buffer to memory Write 0x0012 Set up for OTP access Write 0x0013 Set up for spare area access only Write 0x0014 Set up for main area access only Write 0x0015 Verify erase block Write 0x0016 Set up for main and spare area...

Page 447: ...0 12 ADDR 11 ADDR 10 FBA 0 FBA 0 FPA 5 FPA 5 FPA 5 FPA 5 FPA 5 FPA 5 FPA 5 11 ADDR 10 ADDR 9 FPA 5 FPA 5 FPA 4 FPA 4 FPA 4 FPA 4 FPA 4 FPA 4 FPA 4 10 ADDR 9 ADDR 8 FPA 4 FPA 4 FPA 3 FPA 3 FPA 3 FPA 3 FPA 3 FPA 3 FPA 3 9 ADDR 8 ADDR 7 FPA 3 FPA 3 FPA 2 FPA 2 FPA 2 FPA 2 FPA 2 FPA 2 FPA 2 8 ADDR 7 ADDR 6 FPA 2 FPA 2 FPA 1 FPA 1 FPA 1 FPA 1 FPA 1 FPA 1 FPA 1 7 ADDR 6 ADDR 5 FPA 1 FPA 1 FPA 0 FPA 0 FP...

Page 448: ... to the WTCHDG_RST_L and or WTCHDG_RST_H registers 2 7 ERROR HANDLING If an error is detected the controller updates the int_error_status register with the corresponding error information and sends out an interrupt In addition the ERR_PAGE_ADDR and ERR_PAGE_ADDR_1 registers are updated with the chip number die number block address and page address relating to the error situation These registers ho...

Page 449: ...indicates that the current bus cycle is a write cycle Active LOW Xm0WEn muxed OND_OEn O Output Enable indicates that the current bus cycle is a read cycle Active LOW Xm0OEn muxed OND_INT 1 0 I Interrupt inputs from OneNAND memory Bank 0 1 If OneNAND memory is not used these signals should be tied to zero Xm0FRnB 1 0 muxed OND_AVALID O Address valid output In the POP products address and data are m...

Page 450: ...710_00D0 R W FBA Width Register Device Dependent FPA_WIDTH 0xE710_00E0 R W FPA Width Register Device Dependent FSA_WIDTH 0xE710_00F0 R W FSA Width Register Device Dependent REVISION 0xE710_0100 R Revision Register 0x09 Reserved 0xE710_0110 R Reserved 0x0000 Reserved 0xE710_0120 R Reserved 0x0000 SYNC_MODE 0xE710_0130 R Synchronous Mode Register 0x0000 TRANS_SPARE 0xE710_0140 R W Transfer Size Regi...

Page 451: ...M_CNT 0xE710_02D0 R W Number of Transferred Pages Register 0x0000 TRANS_MODE 0xE710_02E0 R Indicates Transfer Area Register 0x0000 DEV_STAT 0xE710_02F0 R Device Status Register 0x0000 ECC_ERR_STAT_2 0xE710_0300 R ECC Error Status Register 0x0000 ECC_ERR_STAT_3 0xE710_0310 R ECC Error Status Register 0x0000 ECC_ERR_STAT_4 0xE710_0320 R ECC Error Status Register 0x0000 EFCT_BUF_CNT 0xE710_0330 R Eff...

Page 452: ...h of memory device This register is set by software during initialization Device Dependent 4 2 BURST LENGTH REGISTER BURST_LEN R ADDRESS 0XE710_0010 BURST_LEN Bit Description Reset Value Reserved 31 6 Reserved Burst_Length 5 0 Specifies the decoded numerical value of the burst length word count written in the System Configuration 1 register F221 of memory device Read Only Device Dependent 4 3 MEMO...

Page 453: ...ilable OneNAND Device this bit is 1 0 Reserved 11 Reserved 0 INT_act 10 The memory device s INT pin is actively transitioning 0 Unsup_Cmd 9 An unsupported command was received This interrupt is set if an invalid command is received or if a command sequence is broken 0 Locked_Blk 8 The address to program or erase is in a protected block 0 Blk_RW_Cmp 7 This interrupt indicates one of the following h...

Page 454: ... of interrupt Set through software Note Interrupts are only sent to the host if an interrupt is set in the int_error_status register the corresponding bit is set in this register and the INT_PIN_ENABLE register is set 0 4 6 INTERRUPT ERROR ACKNOWLEDGE REGISTER INT_ERR_ACK R W ADDRESS 0XE710_0050 INT_ERR_ACK Bit Description Reset Value Reserved 31 14 Reserved Cache_Op_Err 13 0 Rst_Cmp 12 0 Reserved...

Page 455: ...med depends on the actual memory device being used This register is set by the controller after reset Read Only Device Dependent 4 9 DEVICE ID REGISTER DEVICE_ID R ADDRESS 0XE710_0080 DEVICE_ID Bit Description Reset Value Reserved 31 16 Reserved Memory Device Dependent 15 0 The value programmed depends on the actual memory device being used This register is set by the controller after reset Read O...

Page 456: ...nly Device Dependent 4 13 TECHNOLOGY REGISTER TECH R ADDRESS 0XE710_00C0 TECH Bit Description Reset Value Reserved 31 16 Reserved Memory Device Dependent 15 0 The value programmed depends on the actual memory device being used This register is set by the controller after reset Read Only Device Dependent 4 14 FBA WIDTH REGISTER FBA_WIDTH R W ADDRESS 0XE710_00D0 FBA_WIDTH Bit Description Reset Value...

Page 457: ...ntroller revision number Default value is 0x1 Read Only 0x09 4 18 SYNCHRONOUS MODE REGISTER SYNC_MODE R ADDRESS 0XE710_0130 SYNC_MODE Bit Description Reset Value Reserved 31 2 Reserved RM 1 Sets the transfer mode for read operations as synchronous or asynchronous Default value is 0x0 This value is copied from the memory_configuration register 15 Read Only 0 Asynchronous Mode 1 Activate Synchronous...

Page 458: ...ose not set 0 4 20 PAGE COUNT REGISTER PAGE_CNT R ADDRESS 0XE710_0170 PAGE_CNT Bit Description Reset Value Reserved 31 8 Reserved Page_Count 7 0 Holds the page count of the multi page command currently being executed Read Only 0 4 21 ERROR PAGE ADDRESS REGISTER ERR_PAGE_ADDR R ADDRESS 0XE710_0180 ERR_PAGE_ADDR Bit Description Reset Value Reserved 31 16 Reserved CS 15 14 Chip Select 0 DFS_DBS 13 DF...

Page 459: ...1 12 Reserved Int_Mon_Cyc_ Cnt 11 0 Sets the number of cycles in between checks of the int_error_status register and the memory device s status register This register is used if the Flash configuration register bit IOBE is clear 0x01F4 4 25 ACCESS CLOCK REGISTER ACC_CLOCK R W ADDRESS 0XE710_01C0 ACC_CLOCK Bit Description Reset Value Reserved 31 3 Reserved Access_Clocks 2 0 Sets the number of cycle...

Page 460: ...asing EBI request 3 b010 EBI_RDY_dly 6 4 Defines the value for EBI BUS release delay After transfer is complete OneNAND Controller waits for this number of cycles before release EBI request 3 b010 Reserved 3 2 Reserved 2 b0 bank_en 1 0 Selects the enabled banks 00 Enables Bank 0 01 Enables Bank 0 and 1 10 11 Reserved 2 b00 4 29 WATCHDOG RESET LOW REGISTER WTCHDG_RST_L R W ADDRESS 0XE710_0260 WTCHD...

Page 461: ...register information as programmed Therefore if the host enables the sync_write bit in configuration register the controller sends all future writes to the device as synchronous writes 0 Not supported The Sync_Write bit of the configuration register is masked All writes are in asynchronous mode 1 Supported If the Sync_Write bit of the configuration register is set all writes is performed as synchr...

Page 462: ...DP part 1 DDP part Device Dependent 4 36 MULTI PLANE ENABLE REGISTER MULTI_PLANE R W ADDRESS 0XE710_02C0 MULTI_PLANE Bit Description Reset Value Reserved 31 1 Reserved MP_Device 0 Enables Multi plane Set by software during initialization 0 Not a Multi plane device 1 Multi plane device 0x1 4 37 MEMORY COUNTER REGISTER MEM_CNT R W ADDRESS 0XE710_02D0 MEM_CNT Bit Description Reset Value Reserved 31 1...

Page 463: ...TAT_3 Bit Description Reset Value Reserved 31 16 Reserved Memory Device Dependent 15 0 The value programmed depends on the actual memory device being used This data is used to report ECC error information 0 4 42 ECC ERROR STATUS REGISTER 4 ECC_ERR_STAT_4 R ADDRESS 0XE710_0320 ECC_ERR_STAT_4 Bit Description Reset Value Reserved 31 16 Reserved Memory Device Dependent 15 0 The value programmed depend...

Page 464: ...Value Reserved 31 1 Reserved Cache Program Supported 0 0 Not Supported 1 Supported 0 4 47 SINGLE PAGE BUFFER REGISTER SINGLE_PAGE_BUF R ADDRESS 0XE710_0370 SINGLE_PAGE_BUF Bit Description Reset Value Reserved 31 1 Reserved Single Page Buffer 0 0 Device page size not equal to total data buffer size 1 Device page size equal to total data buffer size 0 4 48 OFFSET ADDRESS OFFSET_ADDR R W ADDRESS 0XE7...

Page 465: ...USER S MANUAL REV1 0 5 3 28 4 49 INT MON STATUS INT_MON_STATUS R ADDRESS 0XE710_0390 INT_MON_STAT Bit Description Reset Value Reserved 31 6 Reserved int_mon_status 5 0 6 h0 RESET WAIT 6 h1 IDLE 6 h2 6 h35 are dependent on H W 0x1 ...

Page 466: ...nt to DRAM The hardware ECC is used to check data validity of the NAND Flash After the NAND Fash content is copied to DRAM main program is executed on DRAM 2 FEATURES NAND Flash memory I F Supports 512Bytes 2KB and 4KB Page Software mode User can directly access NAND flash memory for example this feature is used in read erase program NAND Flash memory Interface 8 bit NAND Flash memory interface bu...

Page 467: ...T E M B U S NAND FLASH Interface CLE ALE nFCE nRE nWE R nB I O0 I O7 AHB Slave I F Control State Machine Figure 5 4 1 NAND Flash Controller Block Diagram 2 2 NAND FLASH MEMORY TIMING HCLK CLE ALE nWE TACLS TWRPH0 TWRPH1 DATA COMMAND ADDRESS Figure 5 4 2 CLE ALE Timing TACLS 1 TWRPH0 0 TWRPH1 0 ...

Page 468: ...S5PC100 USER S MANUAL REV1 0 NAND FLASH CONTROLLER 5 4 3 HCLK nWE nRE DATA DATA TWRPH0 TWRPH1 Figure 5 4 3 nWE nRE Timing TWRPH0 0 TWRPH1 0 ...

Page 469: ... the NAND Flash Memory command cycle Writing to the address register NFADDR the NAND Flash Memory address cycle Writing to the data register NFDATA write data to the NAND Flash Memory write cycle Reading from the data register NFDATA read data from the NAND Flash Memory read cycle Reading main ECC registers NFMECCD0 NFMECCD1 and Spare ECC registers NFSECCD read data from the NAND Flash Memory NOTE...

Page 470: ...4 Bit 23 16 Bit 15 8 Bit 7 0 NFDATA Little 4th I O 7 0 3rd I O 7 0 2nd I O 7 0 1st I O 7 0 B Half word Access Register Endian Bit 31 24 Bit 23 16 Bit 15 8 Bit 7 0 NFDATA Little Invalid Value Invalid Value 2nd I O 7 0 1st I O 7 0 C Byte Access Register Endian Bit 31 24 Bit 23 16 Bit 15 8 Bit 7 0 NFDATA Little Invalid Value Invalid Value Invalid Value 1st I O 7 0 ...

Page 471: ... ECC parity code 4 bit 8 bit ECC module generates parity code for each 512 byte However 1 bit ECC modules generate parity code per byte lane separately Following are the ECC parity code and two tables are 1 bit ECC 28 bit ECC Parity Code 22 bit Line parity 6bit Column Parity 10 bit ECC Parity Code 4 bit Line parity 6bit Column Parity 5 1 2048 BYTE 1 BIT ECC PARITY CODE ASSIGNMENT TABLE DATA7 DATA6...

Page 472: ...1 bit ECC value read from spare area of external NAND Flash memory To compare ECC parity code generated by the H W modules the format of ECC read from memory is important NOTE 4 bit 8 bit ECC decoding scheme is different from 1bit ECC 1 8 bit NAND Flash Memory Interface Register Bit 31 24 Bit 23 16 Bit 15 8 Bit 7 0 NFMECCD0 4th ECC for I O 7 0 3rd ECC for I O 7 0 2nd ECC for I O 7 0 1st ECC for I ...

Page 473: ...the value of the ECC status register does not change 4 To generate spare area ECC parity code Clear SpareECCLock NFCONT 6 bit to 0 Unlock 5 The spare area ECC module generates ECC parity code on register NFSECC whenever data is read or written 6 After you complete read or write spare area set the SpareECCLock bit to 1 Lock ECC Parity code is locked and the value of the ECC status register does not...

Page 474: ...re area However if you use NAND Flash memory more than 512 byte page you can t program immediately In this case copy these parity codes to other memory like DRAM After main data is written write the copied ECC values to spare area The parity codes have self correctable information 4 To generate spare area ECC parity code set the MsgLength to 1 24 byte message length and set the ECCType to 10 enabl...

Page 475: ...cates whether error bit exist or not If any error exists fix it by referring NFECCERR0 1 and NFMLCBITPT register 5 If there is more main data to be read continue from step 1 for remaining data 6 For meta data error check set the MsgLength to 1 24 byte message length and set the ECCType to 1 enable 4 bit ECC ECC module generates ECC parity code for 512 byte read data Therefore reset ECC value by wr...

Page 476: ...te page NAND flash memory is used s w can t program immediately In this case you must copy these parity codes to other memory like DRAM After writing all main data write the copied ECC values to spare area The parity codes have self correctable information include parity code itself 4 To generate spare area ECC parity code set the MsgLength to 1 24 byte message length and set the ECCType to 01 ena...

Page 477: ...CCDecDone NFSTAT 6 is set 1 NF8ECCERR0 indicates whether error bit exist or not If any error exists fix it by referring NF8ECCERR0 1 2 and NFMLC8BITPT0 1 registers 5 If more main data has to be read continue from step 1 6 For meta data error check set the MsgLength to 1 24 byte message length and set the ECCType to 01 enable 8 bit ECC The ECC module generates ECC parity code for 512 byte read data...

Page 478: ...nB 3 0 Input Ready and Busy Xm0FRnB muxed NF_CLE Output Command Latch Enable Xm0FCLE muxed NF_ALE Output Address Latch Enable Xm0FALE muxed NF_nCS 3 0 Output Chip Enable Xm0CSn muxed NF_REn Output Read Enable Xm0FREn muxed NF_WEn Output Write Enable Xm0FWEn muxed NOTE Type field indicates whether pads are dedicated to the signal or pads are connected to the multiplexed signals ...

Page 479: ...er 0x007FFFFA NFECCERR1 0xE720_0030 R ECC Error Status1 Register 0x00000000 NFMECC0 0xE720_0034 R Generated ECC Status0 Register 0xFFFFFFFF NFMECC1 0xE720_0038 R Generated ECC Status1 Register 0xFFFFFFFF NFSECC 0xE720_003C R Generated Spare Area ECC Status Register 0x03FF03FF NFMLCBITPT 0xE720_0040 R 4 bit ECC Error Bit Pattern Register 0x00000000 NF8ECCERR0 0xE720_0044 R 8bit ECC Error Status0 Re...

Page 480: ...tion setting value 0 7 Duration HCLK x TACLS 001 Reserved 11 Reserved 0 TWRPH0 10 8 TWRPH0 duration setting value 0 7 Duration HCLK x TWRPH0 1 000 Reserved 7 Reserved 0 TWRPH1 6 4 TWRPH1 duration setting value 0 7 Duration HCLK x TWRPH1 1 000 MLCFlash 3 This bit indicates type of NAND Flash memory used 0 SLC NAND Flash 1 MLC NAND Flash 0 PageSize 2 This bit indicates the page size of NAND Flash Me...

Page 481: ... to clear LockTight by software If this bit is set to 1 the location excluding the area between NFSBLK 0xE720_0020 and NFEBLK 0xE720_0024 1 is locked write or erase to the area is invalid and only read access is possible If you try to write or erase locked area the illegal access occurs NFSTAT 3 bit will be set If the NFSBLK and NFEBLK are same entire area is locked 0 LOCK 16 Soft Lock configurati...

Page 482: ...rising edge 1 Detects falling edge 0 MECCLock 7 Lock Main area ECC generation 0 Unlocks Main area ECC 1 Locks Main area ECC Main area ECC status register is NFMECC0 NFMECC1 0xE720_0034 0xE720_0038 1 SECCLock 6 Lock Spare area ECC generation 0 Unlocks Spare ECC 1 Locks Spare ECC Spare area ECC status register is NFSECC 0xE720_003C 1 InitMECC 5 1 Initialize main area ECC decoder encoder write only 0...

Page 483: ... 7 0 NAND Flash memory address value 0x00 7 5 DATA REGISTER NFDATA R W ADDRESS 0XE720_0010 NFDATA Bit Description Reset Value NFDATA 31 0 NAND Flash read program data value for I O Note Refer to DATA REGISTER CONFIGURATION in page 6 5 0x00000000 7 6 MAIN DATA AREA ECC REGISTER NFMECCD0 R W ADDRESS 0XE720_0014 NFMECCD0 Bit Description Reset Value ECCData1_1 31 24 2nd ECC for I O 15 8 0x00 ECCData1_...

Page 484: ... for I O 7 0 0x00 ECCData2_1 15 8 3rd ECC for I O 15 8 0x00 ECCData2_0 ECC2 7 0 3rd ECC for I O 7 0 0x00 NOTE Only word access is valid 7 8 SPARE AREA ECC REGISTER NFSECCD R W ADDRESS 0XE720_001C NFSECCD Bit Description Reset Value SECCData1_1 31 24 2nd ECC for I O 15 8 0x00 SECCData1_0 23 16 2nd ECC for I O 7 0 0x00 SECCData0_1 15 8 1st ECC for I O 15 8 0x00 SECCData0_0 7 0 1st ECC for I O 7 0 0x...

Page 485: ...BLK R W ADDRESS 0XE720_0024 NFEBLK Bit Description Reset Value Reserved 31 24 Reserved 0x00 EBLK_ADDR2 23 16 The 3rd block address of the block erase operation 0x00 EBLK_ADDR1 15 8 The 2nd block address of the block erase operation 0x00 EBLK_ADDR0 7 0 The 1st block address of the block erase operation Only bit 7 5 are valid 0x00 NOTE Advance Flash s block Address start from 3 address cycle Therefo...

Page 486: ... ECC or 8 bit ECC encoding is completed 0 MLCDecodeDone 6 If 4 bit ECC or 8 bit ECC decoding is finished this field set and issues interrupt The NFMLCBITPT NFMLCL0 and NFMLCEL1 have valid values To clear this write 1 1 4 bit ECC or 8 bit ECC decoding is completed 0 IllegalAccess 5 Once Soft Lock or Lock tight is enabled The illegal access program erase to the memory set this bit 0 illegal access i...

Page 487: ...ther main data area bit fail error occurred 00 No Error 01 1 bit error correctable 10 Multiple error 11 ECC area error 10 NOTE The above values are valid if both ECC register and ECC status register have valid value If ECCType is 4bit ECC NFECCERR0 Bit Description Reset Value MLCECCBusy 31 Indicates that the 4 bit ECC decoding engine is searching whether a error exists or not 0 Idle 1 Busy 0 MLCEC...

Page 488: ...1SprErrNo 3 2 Indicates whether spare area bit fail error occurred 00 No Error 01 1 bit error correctable 10 Multiple error 11 ECC area error 00 ECC1MainErrNo 1 0 Indicates whether main data area bit fail error occurred 00 No Error 01 1 bit error correctable 10 Multiple error 11 ECC area error 00 NOTE The above values are valid if both ECC register and ECC status register have valid value If ECCTy...

Page 489: ...te NFMECC0 1 if read or write main area data while the MainECCLock NFCONT 7 bit is 0 Unlock If ECCType is 4 bit ECC NFMECC0 Bit Description Reset Value 4th Parity 31 24 4th Check Parity generated from main area 512 byte 0x00 3rd Parity 23 16 3rd Check Parity generated from main area 512 byte 0x00 2nd Parity 15 8 2nd Check Parity generated from main area 512 byte 0x00 1st Parity 7 0 1st Check Parit...

Page 490: ...ntroller generates NFMECC0 1 if read or write main area data while the MainECCLock NFCONT 7 bit is 0 Unlock If ECCType is 4 bit ECC NFMECC1 Bit Description Reset Value Reserved 31 24 Reserved 0x00 7th Parity 23 16 7th Check Parity generated from main area 512 byte 0x00 6th Parity 15 8 6th Check Parity generated from main area 512 byte 0x00 5th Parity 7 0 5th Check Parity generated from main area 5...

Page 491: ...0 0x03 SECC0_0 7 0 Spare area ECC0 Status for I O 7 0 0xFF NOTE The NAND flash controller generates NFSECC if read or write spare area data while the SpareECCLock NFCONT 6 bit is 0 Unlock 7 17 MLC 4 BIT ECC ERROR PATTEN REGISER NFMLCBITPT R ADDRESS 0XE720_0040 NFMLCBITPT Bit Description Reset Value 4th Error bit pattern 31 24 4th Error bit pattern 0x00 3rd Error bit pattern 23 16 3rd Error bit pat...

Page 492: ...bit error 0110 6 bit error 0111 7 bit error 1000 8 bit error 1001 Uncorrectable 1010 1111 reserved 0000 MLC8ErrLocation2 24 15 Error byte location of 2nd bit error 0x000 Reserved 14 10 Reserved 0x00 MLC8ErrLocation1 9 0 Error byte location of 1st bit error 0x000 NOTE These values are updated if ECCDecodeDone NFSTAT 6 is set 1 7 19 ECC0 1 2 FOR 8BIT ECC STATUS REGISTER NFECCERR1 R ADDRESS 0XE720_00...

Page 493: ...CCERR1 Bit Description Reset Value MLCErrLocation8 31 22 Error byte location of 8th bit error 0x000 Reserved 21 Reserved 0 MLCErrLocation7 20 11 Error byte location of 7th bit error 0x000 Reserved 10 Reserved 0 MLCErrLocation6 9 0 Error byte location of 6th bit error 0x000 NOTE These values are updated if ECCDecodeDone NFSTAT 6 is set 1 ...

Page 494: ...yte 0x00 6th Parity 15 8 6th Check Parity generated from main area 512 byte 0x00 5th Parity 7 0 5th Check Parity generated from main area 512 byte 0x00 7 23 MAIN DATA AREA ECC0 STATUS REGISTER NFM8ECC2 R ADDRESS 0XE720_0058 NFM8ECC2 Bit Description Reset Value 12th Parity 31 24 12th Check Parity generated from main area 512 byte 0x00 11th Parity 23 16 11th Check Parity generated from main area 512...

Page 495: ...ttern 7 0 1st Error bit pattern 0x00 7 26 MLC 8 BIT ECC ERROR PATTEN REGISTER NFMLC8BITPT1 R ADDRESS 0XE720_0064 NFMLC8BITPT1 Bit Description Reset Value 8th Error bit pattern 31 24 8th Error bit pattern 0x00 7th Error bit pattern 23 16 7th Error bit pattern 0x00 6th Error bit pattern 15 8 6th Error bit pattern 0x00 5th Error bit pattern 7 0 5th Error bit pattern 0x00 7 27 NFCON ACCESS TIMING ADJU...

Page 496: ...tFlash memory CFC is compatible with CF standard specification Revision 3 0 It is also compatible with AMBA 2 0 specification The CFC supports PC card memory IO mode True IDE mode CFC operates in one mode at a time Default mode is PC card mode The CFC has a top level SFR that includes a mode select bit 1 1 FEATURES The Features supported by the CFC are CompactFlash Specification Revision 3 0 AMBA ...

Page 497: ...0 5 5 2 1 2 BLOCK DIAGRAM Output pad enble PC card controller ATAPI controller Top level SFR Address decoder IDE mode Card power enable AHB master IF AHB slave IF HADDR CF card A H B B a c k b o n e CF controller Figure 5 5 1 CFC Block Diagram ...

Page 498: ... enable strobe and nOE_CF output enable strobe to access memory locations PC card distinguishes between attribute memory and common memory by the signal nREG_CF If nREG_CF is high common memory is accessed If this signal goes low it access attribute memory The PC card I O mode use nIOWR_CF and nIORD_CF to access I O locations Refer to Table 5 5 2 Table 5 5 1 Control Signaling Each Transaction Type...

Page 499: ...T UP IDLE COMMAND HOLD IDLE nCE1 nCE2 IORD IOWR nOE nWE Figure 5 5 2 PC Card State Definition HTRANS HADDR HCLK HREADY HW DATA HRDATA ADDR 25 1 ADDR 0 REG CE 1 CE 2 IORD IOW R OE W E RDATA W DATA SEQ NO N 0 x 20 0 x 21 Data 0 x 20 0 x 20 D 7 0 0 x 20 Even I O interface M em ory Data 0 x 20 D 7 0 0 x 20 Even IDLE SETUP CO M M AND HOLD IDLE Figure 5 5 3 PC Card 8 bit Transfer 8 bit PC Card ...

Page 500: ...0x20 Data 0x22 D 15 0 0x22 D 15 0 0x20 IDLE SETUP COMMAND HOLD SETUP COMMAND HOLD IDLE IDLE Figure 5 5 4 PC Card 16 bit Transfer 16 bit PC Card HTRANS HADDR HCLK HREADY HWDATA HRDATA ADDR 25 0 REG CE1 CE2 IORD IOWR OE WE RDATA WDATA NON SEQ 0x20 0x24 Data 0x20 0x20 0x22 D 15 0 0x20 I O Data 0x20 D 15 0 0x22 D 15 0 0x20 IDLE SETUP COMMAND HOLD SETUP COMMAND HOLD D 15 0 0x22 IDLE T_IDLE Memory Figur...

Page 501: ...ming for SETUP COMMAND and HOLD state for the attribute I O or common memory Each Function Mode Control Signaling is described in Table 5 5 2 below Table 5 5 2 Addressing Mode Valid Data Addressing mode nCE1 nCE2 A 0 D 15 8 D 7 0 No access standby mode 1 1 X High Z High Z 8 16 bit mode even byte 0 1 0 High Z Even byte 8 bit mode odd byte 0 1 1 High Z Odd byte 16 bit mode odd byte only 1 0 1 Odd by...

Page 502: ...l down resistor and pull up resistor on DD 7 to allow a host to recognize the absence of a device at power up so that a host shall detect BSY as being cleared when attempting to read the Status register of a device that is not present The Figure 5 5 6 shows the timing cycle of the true IDE PIO mode if ATA controller is in the ATA_TRANS state The figure indicates various timing parameters Timing t1...

Page 503: ...ual therefore pio_t1 3 0 assigns 6 which is 7 minus 1 If it has residual assign the quotient at pio_t1 3 0 ATA_PIO_TIME Tpara PIO mode Minimum Maximum system clock 1 tPIO0 Timing Parameter of PIO Mode 0 in case of Register Transfer 32 h000_17_1c_6 t1 70 10 7 pio_t1 value 7 1 6 pio_t1 3 0 0x6 t2 290 10 29 pio_t2 value 29 1 28 pio_t2 11 4 0x1c teoc 240 10 24 pio_teoc value 24 1 23 pio_teoc 19 12 0x1...

Page 504: ...A_PIO_LHR set to 8 hFF PIO timing register configured ATA_CONTROL register sets ATA enable ATA class set to PIO DMA transfer direction set to host read from data device Write data at ATA_PIO_DTR register address Increment AHB address and write to other register Read data at AHB address ATA_PIO_DTR Figure 5 5 7 Flowchart for Read Write in PIO Class ...

Page 505: ...timing parameters The ATA_CS0n and CS1n are inactive during MDMA transfer The ATA Host controller is always the master in the MDMA transfer classes The MDMA has three transfer modes Mode 0 2 The fastest mode is mode 2 The Figure 5 5 8 defines the relationships between host and device interface signals for data transfer The Table 5 5 4 describes the timing parameters of MDMA read and write transfer...

Page 506: ...r ATAPI MDMA transfer protocol To write and read transfer Steps to Write Protocol 1 Wait for the driver to activate ATA_DMARQ 2 Activate ATA_DMACKn deactivate ATA_CS0n CS1n and set time to 0 3 Activate ATA_DIOWn at time tM 4 Drive 16 bit data on the lines at time tD 5 Deactivate ATA_DIOWn after tD 6 If ATA_DMARQ is still active repeat step 3 to 6 for another word and deactivate ATA_DMACKn at time ...

Page 507: ...he following figures figure 7 figure 8 figure 9 and figure 10 defines the relationships between host and device interface signals for UDMA data transfer The timing parameters involved are tACKENV tRP tSS tDVS tDVH tACKENV indicates the setup and hold times of DMACK Before assertion or negation and envelope time From DMACKn to STOP and HDMARDYn tRP indicates Ready to pause time tSS indicates time f...

Page 508: ...7 0 DMACK DMARQ DIOW DIOR IORDY tRP tACKENV tACKENV tDVS tDVH Figure 5 5 10 UDMA In Operation Terminated by Host CS0 CS1 DA 2 0 DD 15 0 or DD 7 0 DMACK DMARQ DIOW DIOR IORDY tACKENV tACKENV tACKENV tSS tDVS tDVH tACKENV tDVS tDVH Figure 5 5 11 UDMA Out Operation Terminated by Device ...

Page 509: ...5 12 UDMA Out Operation Terminated by Host Table 5 5 5 Timing Parameter Each UDMA Mode UDMA mode UDMA 0 UDMA 1 UDMA 2 UDMA 3 UDMA 4 tACKENV 20 70 20 70 20 70 20 55 20 55 tSS 50 50 50 50 50 tRP 160 125 100 100 100 tDVS 70 48 31 20 6 7 tDVH 6 2 50 6 2 32 6 2 29 6 2 25 6 2 23 3 tDVS tDVH 120 80 60 45 30 unit ns 50 is tDVS tDVH tDVS 120 70 50 ...

Page 510: ...a_trp 15 8 0x0f tdvs 70 10 7 udma_tdvs value 7 1 6 udma_tdvs 23 16 0x06 tdvh 50 10 5 udma_tdvh value 5 1 4 udma_tdvh 27 24 0x4 tdvh minimum timing is 6 2ns but the timing parameter sets 50ns since the tDVS and tDVH summation is 120ns The Table 5 5 6 shows True IDE Mode Control Signaling Table 5 5 6 True IDE Mode I O Decoding nCE2 nCE1 A2 A1 A0 nDMACK nIORD 0 nIOWR 0 Note 1 0 0 0 0 1 PIO RD data PI...

Page 511: ...f the finite state machine The FSM transition from IDLE state happens if ATA transfer state is in ATA_TRANS The FSM continues the cycle while the abort is asserted The transfer in any class stays in IDLE after detecting ATA state in ATA_ABORT PIO PDMA MDMA or UDMA IDLE state ATA state ATA_TRANS Complete the FSM cycle IDLE state Figure 5 5 13 Flowchart for Abort in ATA Mode ...

Page 512: ...over values of internal registers 6 Re sets transfer configuration and re start remaining data transmission continuously Set ebi_bf_en SFR in ATA_CFG_2 Unmasking Interrupt bit mask_ebi_bf_rd_int or mask_ebi_bf_wr_int 1 10 2 Level 2 1 EBI issues EBI BACKOFF signal during write operation with UDMA MDMA Class 2 Complete operation for current transfer sector 3 Aborts ATA I F and releases EBI BUS Other...

Page 513: ...A_STATUS ATA status 3 ATA_COMMAND ATA command 4 ATA_SWRST ATA software reset 5 ATA_IRQ ATA interrupt sources 6 ATA_IRQ_MASK ATA interrupt mask 7 ATA_CFG ATA configuration for ATA interface 8 ATA_CFG2 ATA configuration 2 for ATA interface 9 ATA_MDMA_TIME ATA multi word DMAtiming 10 ATA_PIO_TIME ATA PIO time 11 ATA_UDMA_TIME ATA UDMA timing 12 ATA_XFR_NUM ATA transfer number 13 ATA_XFR_CNT ATA curre...

Page 514: ...LBA high register 26 ATA_PIO_DVR ATA PIO device register 27 ATA_PIO_CSD ATA PIO device command status register 28 ATA_PIO_DAD ATA PIO device control alternate status register 29 ATA_PIO_READY ATA PIO data read write ready 30 ATA_PIO_RDATA ATA PIO read data from device data register 31 BUS_FIFO_STATUS ATA internal AHB FIFO status 32 ATA_FIFO_STATUS ATA internal ATA FIFO status ...

Page 515: ...FCON_Base 0x0000 CFCON_Base 0x0800 CFCON_Base 0x1000 SFR_Base CFCON_Base 0x1800 MUX_REG Reserved Area PC card controller SFRs Reserved Area ATAPI controlller SFRs Reserved Area SFR_Base 0x0000 SFR_Base 0x0020 SFR_Base 0x0004 SFR_Base 0x0034 SFR_Base 0x0100 SFR_Base 0x0188 CFCON_Base 0xE780_0000 Figure 5 5 14 Memory Map Diagram ...

Page 516: ...ue IDE mode True IDE mode Output port enable Output port enable Card power enable Card power enable Read CIS data Set the operating timing register Ready for operating PC card mode ATAPI controller ON Identify device command Set the mode PIO mode or UDMA mode Ready for operating True IDE mode Card out Card out No Yes No Yes No Yes PC card mode True IDE mode Figure 5 5 15 Basic Function Flow Chart ...

Page 517: ...his device is configured as a Slave This signal must be tied GND or VCC not pulled up pulled down If you pulled down this signal on board nCSEL voltage level is not stable because this signal internally pulled up in CF CF card 2 3 EXTERNAL PULL UP PULL DOWN Table 5 5 7 Externally Pull Up Pull Down Signals Pull up to VCC Pull down to GND nIREQ R 10KΩ nINPACK R 5 6KΩ nWAIT R 10KΩ nIOIS16 R 10KΩ nCD ...

Page 518: ...uring the status register apbif_single_write CFC_PROGRAMMING PCCARD_INTMSK_SRC 0xaaaa_af00 configuring the pccard interrupt mask and source register ATA MODE apbif_single_write CFC_PROGRAMMING MUX_REG 0xaaaa_aaa7 Initialize the internal mode Register apbif_single_write CFC_PROGRAMMING ATA_CFG 0xaaaa_0000 Initializing the ata configuration Register apbif_single_write CFC_PROGRAMMING ATA_IRQ 0xaaaa_...

Page 519: ..._SRC 0Xaaaa_aff2 Void interrupt_service_routine void Poll for the INTSRC_CD bit to be set to 0 in the PCCARD_INTMSK_SRC register wait_for_cfc_intstat Read the INTSRC_CD bit of the PCCARD_INTMSK_SRC register apbif_single_read SEND_FROM_CFC PCCARD_INTMSK_SRC Write 1 to the INTSRC_CD bit of the PCCARD_INTMSK_SRC register this clears the interrupt apbif_single_write SEND_TO_CFC PCCARD_INTMSK_SRC 0Xaaa...

Page 520: ...void Poll for the udma_hold_int bit to be set to 0 in the ATA_IRQ register wait_for_cfc_intstat Read the udma_hold_int bit of the ATA_IRQ register apbif_single_read SEND_FROM_CFC ATA_IRQ Write 1 to the udma_hold_int bit of the ATA_IRQ register this clears the interrupt apbif_single_write SEND_TO_CFC ATA_IRQ 0Xaaaa_aff2 Void interrupt_service_routine void Poll for the xfr_done_int bit to be set to ...

Page 521: ...from CF Card muxed with IORDY at ATA mode Xm0IORDY XmsmADDR 3 muxed CF_INTRQ I Interrupt request from CF Card muxed with INTRQ at ATA mode Xm0INTRQ XmsmADDR 4 muxed CF_INPACKn I Input Acknowledge in I O mode muxed with DMARQ at ATA mode Xm0INPACKn XmsmADDR 5 muxed CF_RESET O CF Card Reset muxed with ATA_RST at ATA mode Xm0RESET XmsmADDR 6 muxed CF_REG O Register in CF Card Strobe muxed with DMACKn...

Page 522: ...CF_D 1 16 DD14 Data 14 CF_D 14 17 DD0 Data 0 CF_D 0 18 DD15 Data 15 CF_D 15 19 GND Ground 20 keypin Key 21 DMARQ DMA Request CF_INPACKn 22 GND Ground 23 DIOW Write Strobe CF_IOWRn 24 GND Ground 25 DIOR Read Strobe CF_IORDn 26 GND Ground 27 IORDY IO Ready CF_IORDY 28 CSEL Cable Select Low master Hi Z slave 29 DMACK DMA Acknowledge CF_REG 30 GND Ground 31 INTRQ Interrupt Request CF_INTRQ 32 N C Not ...

Page 523: ... A02 Address 2 CF_A 2 19 A01 Address 1 CF_A 1 20 A00 Address 0 CF_A 0 21 D00 Data 0 CF_D 0 22 D01 Data 1 CF_D 1 23 D02 Data 2 CF_D 2 24 WP Write Protect 25 CD2 Card Detect 2 CF_CDn 26 CD1 Card Detect 1 CF_CDn 27 D11 Data 11 CF_D 11 28 D12 Data 12 CF_D 12 29 D13 Data 13 CF_D 13 30 D14 Data 14 CF_D 14 31 D15 Data 15 CF_D 15 32 CE2 Card Enable 2 CF_nCS 1 33 VS1 Ground 34 IORD IO Read Strobe CF_IORDn ...

Page 524: ...S5PC100 USER S MANUAL REV1 0 CF CONTROLLER 5 5 29 48 DO9 Data 9 CF_D 9 49 D10 Data 10 CF_D 10 50 GND Ground ...

Page 525: ...0xE780_1900 R W ATA enable and clock down status 0x00000002 ATA_STATUS 0xE780_1904 R ATA status 0x00000008 ATA_COMMAND 0xE780_1908 R W ATA command 0x00000000 ATA_SWRST 0xE780_190C R W ATA software reset 0x00000000 ATA_IRQ 0xE780_1910 R W ATA interrupt sources 0x00000000 ATA_IRQ_MASK 0xE780_1914 R W ATA interrut mask 0x00000000 ATA_CFG 0xE780_1918 R W ATA configuration for ATA interface 0x80000000 ...

Page 526: ... ATA_PIO_LLR 0xE780_1960 R W ATA PIO device LBA low register 0x00000000 ATA_PIO_LMR 0xE780_1964 R W ATA PIO device LBA middle register 0x00000000 ATA_PIO_LHR 0xE780_1968 R W ATA PIO device LBA high register 0x00000000 ATA_PIO_DVR 0xE780_196C R W ATA PIO device register 0x00000000 ATA_PIO_CSD 0xE780_1970 R W ATA PIO device command status register 0x00000000 ATA_PIO_DAD 0xE780_1974 R W ATA PIO devic...

Page 527: ...ion Register MUX_REG R W Address 0xE780_1800 MUX_REG Bit Description R W Initial State Reserved 31 3 Reserved R 0x0 ATA_Indep_Port 2 Indep ATA I F Select 0 EBI Muxed port 1 Indep ATA I F Modem I F R W 0x0 Reserved 1 Fixed to 1 R W 0x1 IDE_MODE 0 Internal operation mode select 0 PC card mode 1 True IDE mode R W 0x0 ...

Page 528: ...card 0 Disables always ready 1 Enables R W 0x1 DEVICE_ATT 10 Device type is 16 bits or 8 bits Attribute memory area 0 8 bit device 1 16 bit device R W 0x1 DEVICE_COMM 9 Device type is 16 bits or 8 bits Common memory area 0 8 bit device 1 16 bit device R W 0x1 DEVICE_IO 8 Device type is 16 bits or 8 bits I O area 0 8 bit device 1 16 bit device R W 0x1 Reserved 7 4 Reserved R 0x0 NOCARD_ERR 3 No car...

Page 529: ...INTSRC_ERR_N 2 If host access no card in slot CPU clears this interrupt by writing 1 R W 0x0 INTSRC_IREQ 1 If CF card interrupt request CPU clears this interrupt by writing 1 R W 0xX INTSRC_CD 0 If CF card is detected in slot CPU clears this interrupt by writing 1 R 0xX 5 2 4 Attribute Memory Card Access Timing PCCARD_ATTR R W Address 0xE780_1828 PCCARD_ATTR Bit Description R W Reset Value Reserve...

Page 530: ... R W Reset Value Reserved 31 23 Reserved R 0x0 HOLD_COMM 22 16 Hold state timing of common memory area R W 0x03 Reserved 15 Reserved R 0x0 CMND_COMM 14 8 Command state timing of common memory area R W 0x19 Reserved 7 Reserved R 0x0 SETUP_COMM 6 0 Setup state timing of common memory area R W 0x09 5 2 7 ATA Control Register ATA_CONTROL R W Address 0xE780_1900 ATA_CONTROL Bit Description R W Reset Va...

Page 531: ...t Value Reserved 31 6 Reserved R 0x0 atadev_cblid 5 ATAPI cable identification R 0x0 atadev_irq 4 ATAPI interrupt signal line R 0x0 atadev_iordy 3 ATAPI iordy signal line R 0x1 atadev_dmareq 2 ATAPI dmareq signal line R 0x0 xfr_state 1 0 Transfer state 2 b00 Idle state 2 b01 Transfer state 2 b10 Abort state 2 b11 Wait for completion state R 0x0 ...

Page 532: ...se After CPU ABORT commands make a software reset by ATA_SWRST to clear the leftover values of internal registers R W 0x0 If CPU wants to pause data transfer use STOP command Issue a CONTINUE command to send data continuously The STOP command controls the ATA Device side signal but does not control DMA side Namely if the FIFO has data after STOP command DMA operation progresses until the FIFO beco...

Page 533: ...FF signal in case of write transfer UDMA MDMA class CPU clears this interrupt by writing 1 R W 0x0 ebi_bf_rd_int 7 When EBI BACKOFF signal is issued by EBI In case of read transfer If CFCON release the EBI BUS this bit clears automatically R W 0x0 ebi_bf_wr_int 6 When EBI BACKOFF signal is issued by EBI in case of write transfer If CFCON release the EBI BUS this bit clears automatically R W 0x0 md...

Page 534: ...ask ebi_bf_rd_int Enable R W 0x0 mask_ebi_bf_wr_int 6 0 Mask ebi_bf_wr_int Disable 1 Unmask ebi_bf_wr_int Enable R W 0x0 mask_mdma_hold_int 5 0 Mask mdma_hold_int Disable 1 Unmask mdma_hold_int Enable R W 0x0 mask_sbut_empty_int 4 0 Mask sbut_empty_int Disable 1 Unmask sbuf_empty_int Enable R W 0x0 mask_tbuf_full_int 3 0 Mask tbuf_full_int Disable 1 Unmask tbuf_full_int Enable R W 0x0 mask_atadev_...

Page 535: ...nged during runtime operation 0 Stays in pause state and wait for CPU s action 1 Continue automatically R W 0x0 Reserved 8 Reserved R 0x0 Reserved 7 Reserved R 0x0 byte_swap 6 Determines whether data endian is little or big in 16 bit data 0 Little endian data 15 8 data 7 0 1 Big endian data 7 0 data 15 8 R W 0x0 atadev_irq_al 5 Device interrupt signal level 0 Active high 1 Active low R W 0x0 dma_d...

Page 536: ...ps to Auto ABORT 1 EBI issues EBI BACKOFF 2 Complete operation of current transfer sector 3 Assert ABORT command by H W Release EBI BUS 4 Issues interrupt ebi_abort_rd_int 5 CPU checks ATA_XFR_CNT 6 Make software reset by ATA_SWRST 7 Re Start for remaining transition by S W R W 0x0 ebi_wr_abort_en 2 Asserted auto abort command when EBI BACKOFF is issued in case of write transfer UDMA MDMA class Th...

Page 537: ... 19 12 PIO timing parameter teoc end of cycle time It shall not have zero value R W 0x27 pio_t2 11 4 PIO timing parameter t2 DIOR Wn pulse width It cannot have zero value R W 0x2f pio_t1 3 0 PIO timing parameter t1 address valid to DIOR Wn R W 0xa 5 2 17 ATA UDMA Time ATA_UDMA_TIME R W Address 0xE780_1930 ATA_UDMA_TIME Bit Description R W Reset Value Reserved 31 28 Reserved R 0x0 udma_tdvh 27 24 U...

Page 538: ... read transfer ATA_XFR_NUM decreases by 1 2 byte In case of write transfer ATA_XFR_NUM decreases by 16 32 byte because the AHB burst size is 8 R 0x00000000 Reserved 0 Reserved R 0x0 5 2 20 Start Address of the Track Buffer ATA_TBUF_BASE R W Address 0xE780_193C ATA_TBUF_BASE Bit Description R W Reset Value track_buffer_base 31 2 Start address of track buffer 4 byte unit R W 0x00000000 Reserved 1 0 ...

Page 539: ... buffer 32byte unit This should be set to size_of_data_in_bytes 1 For example to transfer 1 sector 512 byte 32 h200 you should set 32 h1FF 32 h200 1 R W 0x0000000 Reserved 4 0 Reserved R 0x00 5 2 24 Current Address of Track Buffer ATA_CADDR_TBUF R Address 0xE780_194C ATA_CADDR_TBUF Bit Description R W Reset Value track_buf_cur_adr 31 2 Current address of track buffer R 0x00000000 Reserved 1 0 Rese...

Page 540: ... 2 28 ATA PIO Device Sector Count Register ATA_PIO_SCR R W Address 0xE780_195C ATA_PIO_SCR Bit Description R W Reset Value Reserved 31 8 Reserved R 0x0 pio_dev_scr 7 0 8 bit PIO device sector count command block register R W 0x00 5 2 29 ATA PIO Device LBA Low Register ATA_PIO_LLR R W Address 0xE780_1960 ATA_PIO_LLR Bit Description R W Reset Value Reserved 31 8 Reserved R 0x0 pio_dev_llr 7 0 8 bit ...

Page 541: ...d R 0x0 pio_dev_csd 7 0 8 bit PIO device command status command block register R W 0x00 5 2 34 ATA PIO Device Control Alternate Status Register ATA_PIO_DAD R W Address 0xE780_1974 ATA_PIO_DAD Bit Description R W Reset Value Reserved 31 8 Reserved R 0x0 pio_dev_dad 7 0 8 bit PIO device control alternate status control block register R W 0x00 5 2 35 ATA PIO Data Ready Register ATA_PIO_READY R Addres...

Page 542: ...ATA device register R 0x0000 5 2 37 AHB Bus FIFO Status Register BUS_FIFO_STATUS R Address 0xE780_1980 BUS_FIFO_STATUS Bit Description R W Reset Value Reserved 31 19 Reserved R 0x0 bus_state 2 0 18 16 3 b000 IDLE 3 b001 BUSYW 3 b010 PREP 3 b011 BUSYR 3 b100 PAUSER 3 b101 PAUSEW 3 b110 PAUSER2 R 0x00 Reserved 15 14 Reserved R 0x0 bus_fifo_rdpnt 13 8 Bus FIFO read pointer R 0x00 Reserved 7 6 Reserve...

Page 543: ...00 IDLE 2 b01 T1 2 b10 T2 2 b11 TEOC R 0x0 pdma_state 25 24 2 b00 IDLE 2 b01 T1 2 b10 T2 2 b11 TEOC R 0x0 Reserved 23 Reserved R 0x0 dma_state 1 0 22 21 0 IDLE 1 TD 2 TM 3 TEOC R 0x00 udma_state 4 0 20 16 5 b00000 IDLE 5 b00001 TMI 5 b00010 CRCS 5 b00011 CRCH 5 b00100 END 5 b01000 STOPW 5 b01001 ACKW 5 b01010 NSEQWS 5 b01011 NSEQWH 5 b01100 SEQWS 5 b01101 SEQWH 5 b01110 TSSW 5 b10000 STOPR 5 b1000...

Page 544: ...at they require external bus access The respective arbitrated EBIGNT is issued to the highest priority memory controller EBIBACKOFF is output of the EBI to signal that the memory controller must complete the current transfer and release the bus The EBI arbitration scheme keeps track of the memory controller that is currently granted and waits for the transaction from that memory controller to fini...

Page 545: ...EXTERNAL BUS INTERFACE S5PC100 USER S MANUAL REV1 0 5 6 2 3 BLOCK DIAGRAM Figure 5 6 1 Memory Interface Through EBI ...

Page 546: ...NTERFACE 5 6 3 4 CLOCK SCHEME Figure 5 6 2 Clock Scheme of Memory Controllers and EBI NOTE The OneNAND Clock selection register name in Chapter 02 03 Clock Controller is OneNAND_SEL OneNAND_Async This register address is 0xE010_0200 CLK_SRC0 24 ...

Page 547: ...ntroller is MEM_SYS_CFG This register address is 0xE020_0200 Clock controller sends information based on fixed priority order Fixed Priority Order is summarized in the table below EBI Priority Type 0 Fixed priority 1 Circular priority Fixed Priority Order CfgFixPriTyp 1 0 1st 2nd 3rd 4th 0 SROMC OneNANDC NFCON CFCON 1 OneNANDC SROMC NFCON CFCON 2 NFCON SROMC OneNANDC CFCON 3 CFCON SROMC OneNANDC N...

Page 548: ...MC_DATA 15 0 NF_DATA 15 0 OND_DATA 15 0 CF_D 15 0 Xm0CSn 5 0 SMC_nCS 5 0 NF_nCS 3 0 OND_CSn 1 0 CF_nCS 1 0 Xm0FRnB 1 0 NF_RnB 3 0 OND_INT 1 0 Xm0OEn SMC_OEn OND_OEn Xm0WEn SMC_WEn OND_WEn Xm0BEn 1 0 SMC_Ben 1 0 Xm0WAITn SMC_WAITn Xm0FCLE NF_CLE OND_AVALID Xm0FALE NF_ALE OND_SMCLK Xm0FREn NF_REn Xm0FWEn NF_WEn OND_PRn Xm0IORDY CF_IORDY Xm0INTRQ CF_INTRQ Xm0INPACKn CF_INPACKn Xm0REG CF_REG Xm0IORDn ...

Page 549: ...L330 Conv erter Conv erter Conv erter BREQ0 31 0 BREQ1 31 0 CLR0 31 0 CLR1 31 0 DMA_peri dma_map only wires and OR gates REQ from IPs ACK to IPs DMA PL330 Conv erter Conv erter DMA_mem SEC_ TX_REQ SEC_ TX_CLR SEC_ RX_REQ SEC_ RX_CLR IRQ to interrupt controller IRQ to interrupt controller IRQ to interrupt controller Figure 6 1 1 Two DMA Tops All peripherals must be set as non secure at TZPC module ...

Page 550: ... interrupt is sent to VIC Vectored Interrupt Controller for each DMA To see interrupt number of DMA refer interrupt number table at 04 01 S5PC100_Interrupt Controller chapter SW reads INTSTATUS Interrupt Status register for each module to keep track of occurred interrupt source Table 6 1 1 DMA Request Mapping Table Module No DMA Request Category Service Module 31 Reserved 30 Reserved 29 MSM_REQ3 2...

Page 551: ...ART1 1 2 UART1 0 1 UART0 1 0 UART0 0 System 31 Reserved 30 Reserved 29 HSI_TX 28 HSI_RX 27 SPDIF 26 PWM 25 EXTERNAL GPIO Others 24 AC_PCMout 23 AC_PCMin 22 AC_MICin by only DMA0 21 SPI2_TX 20 SPI2_RX 19 SPI1_TX 18 SPI1_RX 17 SPI0_TX 16 SPI0_RX 15 I2S2_TX 14 I2S2_RX 13 I2S1_TX 12 I2S1_RX 11 I2S0S_TX 10 I2S0_TX 9 I2S0_RX Audio and SPI Peri DMA0 8 IrDA System ...

Page 552: ...ER S5PC100 USER S MANUAL REV1 0 6 1 4 Module No DMA Request Category Service Module 7 UART3 1 6 UART3 0 5 UART2 1 4 UART2 0 3 UART1 1 2 UART1 0 1 UART0 1 0 UART0 0 1 SEC_TX DMA_mem 0 SEC_RX Security by M2M DMA only ...

Page 553: ...Register For more information refer to Page 3 14 of PL330 TRM 0x0 INTSTATUS 0xE810_0028 R Interrupt Status Register For more information refer to Page 3 16 of PL330 TRM 0x0 INTCLR 0xE810_002C W Interrupt Clear Register For more information refer to Page 3 17 of PL330 TRM 0x0 FSM 0xE810_0030 R Fault Status DMA Manager Register For more information refer to Page 3 18 of PL330 TRM 0x0 FSC 0xE810_0034...

Page 554: ...xE810_0124 R Channel PC for DMA Channel 4 0x0 CPC5 0xE810_012C R Channel PC for DMA Channel 5 0x0 CPC6 0xE810_0134 R Channel PC for DMA Channel 6 0x0 CPC7 0xE810_013C R Channel PC for DMA Channel 7 0x0 Reserved 0xE810_0140 0xE810_03FC Reserved Source Address Registers For more information refer to Page 3 27 of PL330 TRM SA_0 0xE810_0400 R Source Address for DMA Channel 0 0x0 SA_1 0xE810_0420 R Sou...

Page 555: ...0_040C R Loop Counter 0 for DMA Channel 0 0x0 LC0_1 0xE810_042C R Loop Counter 0 for DMA Channel 1 0x0 LC0_2 0xE810_044C R Loop Counter 0 for DMA Channel 2 0x0 LC0_3 0xE810_046C R Loop Counter 0 for DMA Channel 3 0x0 LC0_4 0xE810_048C R Loop Counter 0 for DMA Channel 4 0x0 LC0_5 0xE810_04AC R Loop Counter 0 for DMA Channel 5 0x0 LC0_6 0xE810_04CC R Loop Counter 0 for DMA Channel 6 0x0 LC0_7 0xE810...

Page 556: ... Configuration Register 0 For more information refer to Page 3 40 of PL330 TRM 0x003E_1071 CR1 0xE810_0E04 R Configuration Register 1 For more information refer to Page 3 42 of PL330 TRM 0x0000_0075 CR2 0xE810_0E08 R Configuration Register 2 For more information refer to Page 3 43 of PL330 TRM 0x0 CR3 0xE810_0E0C R Configuration Register 3 For more information refer to Page 3 44 of PL330 TRM 0xFFF...

Page 557: ...00_0034 R Fault Status DMA Channel Register For more information refer to Page 3 19 of PL330 TRM 0x0 FTM 0xE900_0038 R Fault Type DMA Manager Register For more information refer to Page 3 20 of PL330 TRM 0x0 Reserved 0xE900_003C Reserved FTC0 0xE900_0040 R Fault Type for DMA Channel 0 0x0 FTC1 0xE900_0044 R Fault Type for DMA Channel 1 0x0 FTC2 0xE900_0048 R Fault Type for DMA Channel 2 0x0 FTC3 0...

Page 558: ...900_0460 R Source Address for DMA Channel 3 0x0 SA_4 0xE900_0480 R Source Address for DMA Channel 4 0x0 SA_5 0xE900_04A0 R Source Address for DMA Channel 5 0x0 SA_6 0xE900_04C0 R Source Address for DMA Channel 6 0x0 SA_7 0xE900_04E0 R Source Address for DMA Channel 7 0x0 Destination Address Registers For more information refer to Page 3 29 of PL330 TRM DA_0 0xE900_0404 R Destination Address for DM...

Page 559: ...Counter 0 for DMA Channel 7 0x0 Loop Counter 1 Registers For more information refer to Page 3 36 of PL330 TRM LC1_0 0xE900_0410 R Loop Counter 1 for DMA Channel 0 0x0 LC1_1 0xE900_0430 R Loop Counter 1 for DMA Channel 1 0x0 LC1_2 0xE900_0450 R Loop Counter 1 for DMA Channel 2 0x0 LC1_3 0xE900_0470 R Loop Counter 1 for DMA Channel 3 0x0 LC1_4 0xE900_0490 R Loop Counter 1 for DMA Channel 4 0x0 LC1_5...

Page 560: ... to Page 3 42 of PL330 TRM 0x0000_0074 CR2 0xE900_0E08 R Configuration Register 2 For more information refer to Page 3 43 of PL330 TRM 0x0000_0000 CR3 0xE900_0E0C R Configuration Register 3 For more information refer to Page 3 44 of PL330 TRM 0xFFFF_FFF F CR4 0xE900_0E10 R Configuration Register 4 For more information refer to Page 3 45 of PL330 TRM 0xFFFF_FFF F CRDn 0xE900_0E14 R Configuration Re...

Page 561: ...920_0034 R Fault Status DMA Channel Register For more information refer to Page 3 19 of PL330 TRM 0x0 FTM 0xE920_0038 R Fault Type DMA Manager Register For more information refer to Page 3 20 of PL330 TRM 0x0 Reserved 0xE920_003C Reserved FTC0 0xE920_0040 R Fault Type for DMA Channel 0 0x0 FTC1 0xE920_0044 R Fault Type for DMA Channel 1 0x0 FTC2 0xE920_0048 R Fault Type for DMA Channel 2 0x0 FTC3 ...

Page 562: ...920_0460 R Source Address for DMA Channel 3 0x0 SA_4 0xE920_0480 R Source Address for DMA Channel 4 0x0 SA_5 0xE920_04A0 R Source Address for DMA Channel 5 0x0 SA_6 0xE920_04C0 R Source Address for DMA Channel 6 0x0 SA_7 0xE920_04E0 R Source Address for DMA Channel 7 0x0 Destination Address Registers For more information refer to Page 3 29 of PL330 TRM DA_0 0xE920_0404 R Destination Address for DM...

Page 563: ...nel 6 0x0 LC0_7 0xE920_04EC R Loop Counter 0 for DMA Channel 7 0x0 Loop Counter 1 Registers For more information refer to Page 3 36 of PL330 TRM LC1_0 0xE920_0410 R Loop Counter 1 for DMA Channel 0 0x0 LC1_1 0xE920_0430 R Loop Counter 1 for DMA Channel 1 0x0 LC1_2 0xE920_0450 R Loop Counter 1 for DMA Channel 2 0x0 LC1_3 0xE920_0470 R Loop Counter 1 for DMA Channel 3 0x0 LC1_4 0xE920_0490 R Loop Co...

Page 564: ...L330 TRM 0x0000_0074 CR2 0xE920_0E08 R Configuration Register 2 For more information refer to Page 3 43 of PL330 TRM 0x0000_0000 CR3 0xE920_0E0C R Configuration Register 3 For more information refer to Page 3 44 of PL330 TRM 0xFFFF_FFF F CR4 0xE920_0E10 R Configuration Register 4 For more information refer to Page 3 45 of PL330 TRM 0xFFFF_FFF F CRDn 0xE920_0E14 R Configuration Register Dn For more...

Page 565: ...E810_0488 CC_5 R Address 0xE810_04A8 CC_6 R Address 0xE810_04C8 CC_7 R Address 0xE810_04E8 CCn Bit Description Reset Value dst_burst_size 17 15 Programs the burst size that the DMAC uses when it writes the destination data b000 1 byte b001 2 bytes b010 4 bytes b011 8 bytes Other Reserved 0 src_burst_size 3 1 Programs the burst size that the DMAC uses when it reads the source data b000 1 byte b001 ...

Page 566: ... 0xE900_0488 0xE920_0488 CC_5 R Address 0xE900_04A8 0xE920_04A8 CC_6 R Address 0xE900_04C8 0xE920_04C8 CC_7 R Address 0xE900_04E8 0xE920_04E8 CCn Bit Description Reset Value dst_burst_size 17 15 Programs the burst size that the DMAC uses when it writes the destination data b000 1 byte b001 2 bytes b010 4 bytes Other Reserved 0 src_burst_size 3 1 Programs the burst size that the DMAC uses when it r...

Page 567: ...ral request interfaces that the DMAC provides b11111 32 peripheral request interfaces 0x1F num_chnls 6 4 Number of DMA channels that the DMAC supports b111 8 DMA channels 0x7 mgr_ns_at_rst 2 Indicates the status of the boot_manager_ns signal when the DMAC exited from reset 1 boot_manager_ns was HIGH 1 boot_en 1 Indicates the status of the boot_from_pc signal when the DMAC exited from reset 0 boot_...

Page 568: ...he line is 16 bytes 0x4 3 2 5 Configuration Register2 for DMA_PERI 0 1 CR2 R CR2 for DMA_PERI0 R Address 0xE900_0E08 CR2 for DMA_PERI1 R Address 0xE920_0E08 CR2 Bit Description Reset Value boot_addr 31 0 Provides the value of boot_addr 31 0 when the DMAC exited from reset 32 b0 0 3 2 6 Configuration Register3 for DMA_PERI 0 1 CR3 R CR3 for DMA_PERI0 R Address 0xE900_0E0C CR3 for DMA_PERI1 R Addres...

Page 569: ...ERI 0 1 CRdn R CRDn for DMA_PERI0 R Address 0xE900_0E14 CRDn for DMA_PERI1 R Address 0xE920_0E14 CRDn Bit Description Reset Value data_buffer_dep 29 20 The number of lines that the data buffer contains b000000111 8 lines 0x7 rd_q_dep 19 16 The depth of the read queue b0111 8 lines 0x7 rd_cap 14 12 Read issuing capability that programs the number of outstanding read transactions b011 4 0x3 wr_q_dep...

Page 570: ... mgr_ns_at_rst 2 Indicates the status of the boot_manager_ns signal when the DMAC exited from reset 0 boot_manager_ns was LOW 0 boot_en 1 Indicates the status of the boot_from_pc signal when the DMAC exited from reset 0 boot_from_pc was LOW 0 periph_req 0 Supports peripheral requests 1 the DMAC provides the number of peripheral request interfaces that the num_periph_req field specifies 1 3 2 10 Co...

Page 571: ...Register3 for DMA_MEM CR3 R Address 0xE810_0E0C CR3 Bit Description Reset Value INS 31 0 Provides the security state of the interrupt outputs Bit N 1 Assigns irq N to the Non secure state 32 hffff_ffff 0xFFFF_FFFF 3 2 13 Configuration Register4 for DMA_MEM CR4 R Address 0xE810_0E10 CR4 Bit Description Reset Value PNS 31 0 Provides the security state of the peripheral request interfaces Bit N 1 Ass...

Page 572: ...b000011111 32 lines 0x1F rd_q_dep 19 16 The depth of the read queue b0111 8 lines 0x7 rd_cap 14 12 Read issuing capability that programs the number of outstanding read transactions b011 4 0x3 wr_q_dep 11 8 The depth of the write queue b0111 8 lines 0x7 wr_cap 6 4 Write issuing capability that programs the number of outstanding write transactions b011 4 0x3 data_width 2 0 The data bus width of the ...

Page 573: ...3 of PL330 TRM DMAKILL Kill M C See DMAKILL on page 4 13 of PL330 TRM DMAMOV Move C See DMAMOV on page 4 14 of PL330 TRM DMANOP No operation M C See DMANOP on page 4 16 of PL330 TRM DMARMB Read Memory Barrier C See DMARMB on page 4 16 of PL330 TRM DMASEV Send Event M C See DMASEV on page 4 17 of PL330 TRM DMAST Store C See DMAST S B on page 4 17 of PL330 TRM DMASTP Store and notify Peripheral C Se...

Page 574: ... B Refer to PL330 TRM Page 4 25 4 26 for exact DMA setting you need like burst length bit width address increment and etc DMALD DMALDP Load instructs the DMAC to perform a DMA load using AXI transactions that the SAR and CCR specify For example if you define CCR as 32 bit burst length 2 one DMALD generates a bus transaction of 32 bit and burst length2 DMALDP notifies the peripheral that the data t...

Page 575: ...heral instructs the DMAC to halt execution of the thread until the specified peripheral signals a DMA request for that DMA channel DMAFLUSHP This is used for peripheral DMA Flush Peripheral clears the state in DMA that describes the contents of the peripheral and sends a message to the peripheral to resend its level status This instruction asserts DMAACK If you need DMAACK at certain point place t...

Page 576: ...ons DMAGO DMASEV and DMAKILL DMAGO starts a channel For more information refer to PL330 TRM P 3 38 3 40 and P 4 6 4 8 C DBGCMD executes the instruction stored in DBGINST0 and 1 SFRs Security Scheme DMA_mem runs on both secure non secure mode and DMA_peri runs only on non secure mode 1 Channel thread A DMA_mem both secure ns bit at DMAGO instruction as 0 and non secure ns bit at DMAGO instruction a...

Page 577: ... irq N HIGH 2 Program assembly code to set the corresponding IRQ HIGH by executing DMASEV Use DMASEV instruction to signal an interrupt using one of the IRQ outputs 3 Clear the interrupt by writing to the Interrupt Clear Register Each bit in the INTCLR Register controls the clearing of an interrupt Program to controls the clearing of the irq outputs Bit N 0 The status of irq N does not change Bit ...

Page 578: ...ects the external clock PWM_TCLK Each timer has its own 32 bit down counter which is driven by the timer clock The down counter is initially loaded from the Timer Count Buffer register TCNTBn If the down counter reaches zero the timer interrupt request is generated to inform the CPU that the timer operation is complete If the timer down counter reaches zero the value of corresponding TCNTBn automa...

Page 579: ...159 50 109 and TCMPBn with 109 2 Start Timer Set the start bit and manual update bit to off The TCNTBn value of 159 is loaded into the down counter the output is driven low 3 If down counter counts down to value in the TCMPBn register 109 the output changes from low to high 4 If the down counter reaches 0 it generates interrupt request 5 The down counter automatically reloads with TCNTBn This rest...

Page 580: ... 6 1 MUX 1 2 1 4 1 8 1 16 PCLK PWM_TCLK PWM_TCLK PWM_TCLK PWM_TCLK PWM_TCLK PWM_CLK Control Logic0 Control Logic1 Control Logic2 Control Logic3 Control Logic4 DeadZone Generator Deadzone Deadzone XpwmTOUT0 No pin No pin XpwmTOUT1 1 1 1 1 XpwmTOUT2 Figure 7 1 2 PWM TIMER Clock Tree Diagram The Figure 7 1 2 shows the clock generation scheme for individual PWM Channels Each timers can generate level ...

Page 581: ...M is stopped Dynamic Configuration PWM is running Auto Reload Mode and One Shot Pulse Mode One external input to start PWM Dead Zone Generator on two PWM Outputs Level Interrupt Generation The PWM has two operation modes Auto Reload Mode Continuous PWM pulses are generated based on programmed duty cycle and polarity One Shot Pulse Mode Only one PWM pulse is generated based on programmed duty cycle...

Page 582: ...Clock Divider Values 4 bit Divider Settings Minimum Resolution prescaler value 1 Maximum Resolution prescaler value 255 Maximum Interval TCNTBn 4294967295 1 1 PCLK 66MHz 0 030us 33 0MHz 3 879us 257 8KHz 16659 27s 1 2 PCLK 66MHz 0 061us 16 5MHz 7 758us 128 9KHz 33318 53s 1 4 PCLK 66MHz 0 121us 8 25MHz 15 515us 64 5KHz 66637 07s 1 8 PCLK 66MHz 0 242us 4 13MHz 31 03us 32 2KHz 133274 14s 1 16 PCLK 66M...

Page 583: ...e TCNTn register is read from the TCNTOn register If you want to generate interrupt at intervals 3cycle of XpwmTOUTn set TCNTBn TCMPBn and TCON register as shown in Figure 7 1 3 Steps to generate interrupt 1 Set TCNTBn 3 and TCMPBn 1 2 Set auto reload 1 and manual update 1 If manual update bit is 1 TCNTBn and TCMPBn value are loaded to TCNTn and TCMPn 3 Set TCNTBn 2 and TCMPBn 0 for next operation...

Page 584: ...read from TCNTOn Timer Count Observation register If TCNTBn is read the read value is not the current state of the counter but the reload value for the next timer duration The auto reload is the operation which copies the TCNTBn into TCNTn if TCNTn reaches 0 The value written into TCNTBn is loaded to TCNTn if the TCNTn reaches to 0 and auto reload is enabled If the TCNTn is 0 and the auto reload b...

Page 585: ...TOUTn is changed from low to high 4 As soon as TCNTn reaches to 0 it generates interrupt request 5 TCNTn and TCMPn are reloaded automatically with TCNTBn and TCMPBn as 79 40 39 and 39 In the ISR Interrupt Service Routine the TCNTBn and TCMPBn are set as 79 20 59 and 59 6 If TCNTn and TCMPn has same value the logic level of TOUTn is changed from low to high 7 As soon as TCNTn reaches to 0 it genera...

Page 586: ...Note We recommend you to set the inverter on off bit whether inverter is used or not 3 Set the start bit of corresponding timer to start the timer 3 6 PWM PULSE WIDTH MODULATION Write TCMPBn 60 Write TCMPBn 50 Write TCMPBn 40 Write TCMPBn 30 Write TCMPBn 30 Write TCMPBn next PWM 60 50 40 30 30 Figure 7 1 6 Example of PWM Use TCMPBn to implement PWM feature PWM frequency is determined by TCNTBn A P...

Page 587: ...y the inverter on off bit in TCON The inverter removes the additional circuit to adjust the output level 3 8 DEAD ZONE GENERATOR The deadzone is for the PWM control of power devices This feature is used to insert the time gap between a turn off of a switching device and a turn on of the other switching device This time gap prohibits the two switching device turning on simultaneously even for a ver...

Page 588: ...S5PC100 USER S MANUAL REV1 0 PULSE WIDTH MODULATION TIMER 7 1 11 TOUT0 nTOUT0 DEADZONE INTERVAL TOUT0_DZ nTOUT0_DZ Figure 7 1 8 The Waveform when a Dead Zone Feature is Enabled ...

Page 589: ...ad Type TOUT0 Output PWMTIMER TOUT 0 XpwmTOUT 0 muxed TOUT1 Output PWMTIMER TOUT 1 XpwmTOUT 1 muxed TOUT2 Output PWMTIMER TOUT 2 XpwmTOUT 2 muxed PWM_TCLK Input PWMTIMER External Clock XpwmTOUT 0 muxed NOTE Type field indicates whether pads are dedicated to the signal or pads are connected to the multiplexed signals ...

Page 590: ...bservation Register 0x0000_0000 TCNTB1 0xEA00_0018 R W Timer 1 Count Buffer Register 0x0000_0000 TCMPB1 0xEA00_001C R W Timer 1 Compare Buffer Register 0x0000_0000 TCNTO1 0xEA00_0020 R Timer 1 Count Observation Register 0x0000_0000 TCNTB2 0xEA00_0024 R W Timer 2 Count Buffer Register 0x0000_0000 TCMPB2 0xEA00_0028 R W Timer 2 Compare Buffer Register 0x0000_0000 TCNTO2 0xEA00_002C R Timer 2 Count O...

Page 591: ...vider value prescaler value 1 255 divider value 1 2 4 8 16 TCLK Dead zone length 0 254 TCFG0 Bit Description Reset Value Reserved 31 24 Reserved Bits 0x00 Dead zone length 23 16 Dead zone length 0x00 Prescaler 1 15 8 Prescaler 1 value for Timer 2 3 and 4 0x01 Prescaler 0 7 0 Prescaler 0 value for timer 0 1 0x01 NOTE If Dead Zone Length is set n Real Dead Zone Length is n 1 n 0 254 ...

Page 592: ...1 4 0011 1 8 0100 1 16 0101 PWM_TCLK 0x00 Divider MUX1 7 4 Selects Mux input for PWM Timer 1 0000 1 1 0001 1 2 0010 1 4 0011 1 8 0100 1 16 0101 PWM_TCLK 0x00 Divider MUX0 3 0 Selects Mux input for PWM Timer 0 0000 1 1 0001 1 2 0010 1 4 0011 1 8 0100 1 16 0101 PWM_TCLK 0x00 NOTE If you use PWM_TCLK duty of TOUT may show slight error PWM_TCLK is sampled by PCLK in PWM module But PWM_TCLK and PCLK is...

Page 593: ...Output Inverter on off 14 0 Inverter Off 1 TOUT_2 Inverter On 0x0 Timer 2 Manual Update 13 0 No Operation 1 Update TCNTB2 TCMPB2 0x0 Timer 2 Start Stop 12 0 Stop 1 Start Timer 2 0x0 Timer 1 Auto Reload on off 11 0 One Shot 1 Interval Mode Auto Reload 0x0 Timer 1 Output Inverter on off 10 0 Inverter Off 1 TOUT_1 Inverter On 0x0 Timer 1 Manual Update 9 0 No Operation 1 Update TCNTB1 TCMPB1 0x0 Timer...

Page 594: ...ADDRESS 0XEA00_0014 TCNTO0 Bit Description Reset Value Timer 0 Count Observation 31 0 Timer 0 Count Observation Register 0x0000_0000 NOTE Counter observation time is dependent on PWM timer clock and PCLK When you observe counter value after PWM timer start wait for delay time Timer Clock period 2 2 PCLK period Example if Prescaler is 4 and Divider mux is 1 2 Timer clock period 4 1 2 PCLK TCNTO obs...

Page 595: ...r 2 Compare Buffer Register 0x0000_0000 5 12 TIMER2 OBSERVATION REGISTER TCNTO2 R ADDRESS 0XEA00_002C TCNTO2 Bit Description Reset Value Timer 2 Count Observation 31 0 Timer 2 Count Observation Register 0x0000_0000 NOTE Counter observation time is dependent on PWM timer clock and PCLK When you observe counter value after PWM timer start wait for delay time Timer Clock period 2 2 PCLK period 5 13 T...

Page 596: ...r 4 Count Buffer Register 0x0000_0000 5 16 TIMER4 OBSERVATION REGISTER TCNTO4 R ADDRESS 0XEA00_0040 TCNTO4 Bit Description Reset Value Timer 4 Count Observation 31 0 Timer 4 Count Observation Register 0x0000_0000 NOTE Counter observation time is dependent on PWM timer clock and PCLK When you observe counter value after PWM timer start wait for delay time Timer Clock period 2 2 PCLK period ...

Page 597: ...er 2 Interrupt Status Bit Clears by writing 1 on this bit 0x0 Timer 1 Interrupt Status 6 Timer 1 Interrupt Status Bit Clears by writing 1 on this bit 0x0 Timer 0 Interrupt Status 5 Timer 0 Interrupt Status Bit Clears by writing 1 on this bit 0x0 Timer 4 interrupt Enable 4 Enables Timer 4 Interrupt 1 Enabled 0 Disabled 0x0 Timer 3 interrupt Enable 3 Enables Timer 3 Interrupt 1 Enabled 0 Disabled 0x...

Page 598: ...IEW System timer provides two distinctive features First one is accurate timer which provides 1ms time tick at any power mode except sleep mode Second one is changeable interrupt interval without stopping reference tick timer Figure 7 2 1 Overall System Timer Block Diagram ...

Page 599: ...Address R W Description Reset Value TCFG EA10_0000 R W Configures 8 bit Prescaler and Clock MUX 0x0000_0000 TCON EA10_0004 R W Timer Control Register 0x0000_0000 TCNTB EA10_0008 R W Tick Count Buffer Register 0x0000_0000 TCNTO EA10_000C R Tick Count Observation Register 0x0000_0000 ICNTB EA10_0010 R W Interrupt Count Buffer Register 0x0000_0000 ICNTO EA10_0014 R Interrupt Count Observation Registe...

Page 600: ...pt INTCNT INTCNT 1 Tick Fixed tick pulse User Change Interrupt Interval Counter ICNTB Value Without Timer Stop User Observe Counter Value ICNTO TICK Generation region Interrupt Generation region Auto Reload Figure 7 2 2 Two Separate Timers There are two separate timers One for tick generation and the other for interrupt generation and there are two independent SFR sets and logic blocks for each ti...

Page 601: ...se tick and interrupt counter are independent to each other Interrupt is asserted at INTCNT value is expired INTCNT 0 SW can know elapsed time by reading ICNTO NOTE When ICNTB is changed with interrupt manual update TCON 4 at Figure 7 2 3 the new changed value is applied to INTCNT interrupt counter at that time When ICNTB is changed without interrupt manual update TCON 4 at Figure 7 2 3 the new ch...

Page 602: ...ause sometimes system timer uses RTC or XXTI clock for counter They are slower than PCLK operating clock of SFR After those write status interrupts are asserted SW can assure new value is really updated at internal counter SW must wait until that time Note TCON and ICNTB writing interrupt can be disabled by SFR But TCNTB writing can t be disabled When you write TCNTB SFR that interrupt is always a...

Page 603: ...11 to update wanted value to internal interrupt counter at that time and start interrupt counter 11 Wait until TCON write interrupt occurs and write 1 to INT_CSTAT 4 to clear interrupt status bit 12 If auto reload mode is needed TCON 4 must be de asserted and write 1 to TCON 5 13 Wait until TCON write interrupt occurs and write 1 to INT_CSTAT 4 to clear interrupt status bit 6 4 STOP TIMER 1 Write ...

Page 604: ...and Clock MUX 0x0000_0000 TCON EA10_0004 R W Timer Control Register 0x0000_0000 TCNTB EA10_0008 R W Tick Count Buffer Register 0x0000_0000 TCNTO EA10_000C R Tick Count Observation Register 0x0000_0000 ICNTB EA10_0010 R W Interrupt Count Buffer Register 0x0000_0000 ICNTO EA10_0014 R Interrupt Count Observation Register 0x0000_0000 INT_CSTAT EA10_0018 R W Clears Interrupt 0x0000_0000 ...

Page 605: ...APB Usable clock source is restricted by power mode oscillator pad configuration XrtcXTI for any power mode oscillator pad configuration XXTI XusbXTI for any power mode with turning on OSCs XXTI and XusbXTI PCLKD1 for just normal idle mode To get detailed information refer PMU Power Management Unit user s manual 0x0 Divider MUX 10 8 Selects Mux input for Timer 000 1 001 1 2 010 1 4 011 1 8 100 1 1...

Page 606: ...shot mode 0x0 Timer Start Stop 0 0 Stop 1 Start timer 0x0 If you want to use One shot mode for interrupt remain interrupt manual update bit as asserted as 1 In that case interrupt occurs at every TICK after interrupt counter is reached to zero If you want to use interval mode for interrupt de assert as 0 manual update bit after asserting it In that case the value in ICNTB is automatically reloaded...

Page 607: ...TROL AND STATUS REGISTER INT_CSTAT R W Address EA10_0018 INT_CSTAT Bit Description Reset Value TCON Write Status 4 TCON Write Status Interrupt Bit After internal counters are updated this bit is asserted Clear by writing 1 on this bit 0x0 ICNTB Write Status 3 ICNTB Write Status Interrupt Bit After internal counters are updated this bit is asserted Clear by writing 1 on this bit 0x0 TCNTB Write Sta...

Page 608: ...noise and system errors It is used as a normal 16 bit interval timer to request interrupt service The WDT generates the reset signal Difference between WDT and PWM timer is that WDT generates the reset signal 2 FEATURES Supports Normal interval timer mode with interrupt request Activates Internal reset signal if the timer count value reaches 0 Time out Supports Level triggered Interrupt mechanism ...

Page 609: ...ion factor can be selected as 16 32 64 or 128 Use the following equation to calculate the watchdog timer clock frequency and the duration of each timer clock cycle t_watchdog 1 PCLK Prescaler value 1 Division_factor 3 2 WTDAT WTCNT Once the watchdog timer is enabled the value of watchdog timer data WTDAT register cannot be automatically reloaded into the timer counter WTCNT For this reason an init...

Page 610: ... its power on if controller restart is not desired the Watchdog timer should be disabled If you want to use the normal timer provided by the Watchdog timer enable the interrupt and disable the Watchdog timer WTCON Bit Description Reset Value Reserved 31 16 Reserved 0 Prescaler value 15 8 Prescaler value The valid range is from 0 to 28 1 0x80 Reserved 7 6 Reserved These two bits must be 00 in norma...

Page 611: ...unt values for the watchdog timer during normal operation Note that the content of the WTDAT register cannot be automatically loaded into the timer count register if the watchdog timer is enabled initially therefore the WTCNT register must be set to an initial value before enabling it WTCNT Bit Description Reset Value Reserved 31 16 Reserved 0 Count value 15 0 The current count value of the watchd...

Page 612: ...Month and Year The RTC unit works with an external 32 768 kHz crystal and performs the alarm function 2 FEATURES BCD Number Second Minute Hour Date Day Month and Year Leap Year Generator Alarm Function Alarm Interrupt or Wake up from Power off mode Tick Counter Function Tick Interrupt or Wake up from Power off mode Year 2000 problem is removed Independent Power Pin RTCVDD Supports millisecond tick...

Page 613: ...s hard wired logic to support the leap year in 2000 Note 1900 is not leap year while 2000 is leap year Therefore two digits of 00 in S5PC100 denote 2000 not 1900 5 READ WRITE REGISTER Set Bit 0 of the RTCCON register to high in order to write the BCD register in RTC block To display the second minute hour day date month and year the CPU should read the data in BCDSEC BCDMIN BCDHOUR BCDDATE BCDDAY ...

Page 614: ...and the backup battery only drives the oscillation circuit and the BCD counters to minimize power dissipation 7 ALARM FUNCTION The RTC generates an alarm signal at a specified time in the power off mode or normal operation mode In normal operation mode the alarm interrupt ALMINT is activated In the power off mode the power management wakeup PMWKUP signal is activated as well as the ALMINT The RTC ...

Page 615: ...16384 2 14 0 262143 0 06 4 b0010 8192 2 13 0 524287 0 12 4 b0011 4096 2 12 0 1048575 0 24 4 b0100 2048 2 11 0 2097151 0 49 4 b0101 1024 2 10 0 4194303 0 97 4 b0110 512 2 9 0 8388607 1 95 4 b0111 256 2 8 0 16777215 3 90 4 b1000 128 2 7 0 33554431 7 81 4 b1001 64 2 6 0 67108863 15 62 4 b1010 32 2 5 0 134217727 31 25 4 b1011 16 2 4 0 268435455 62 50 4 b1100 8 2 3 0 536870911 125 4 b1101 4 2 2 0 10737...

Page 616: ...en XrtcXTI and XrtcXTO 10 DRIVE STRENGTH CONTROL For more information refer to ETC4DRV 0xE030_056C in Pad Control doc SFR Name Field Value Min Type Max Unit 1 1 7 1 8 1 9 V ETC4DRV 0 default 2 3 2 5 3 3 3 6 V 11 RTC START To start RTC set RTCCON 0 as 1 12 I O DESCRIPTION Function Signal I O Description Pad Type RTC_XTI Input 32 768 KHz RTC Oscillator Clock Input XrtcXTI Dedicated RTC_XXTO Output 3...

Page 617: ...0 ALMHOUR 0xEA30_005C R W Alarm Hour Data Register 0x00000000 ALMDATE 0xEA30_0060 R W Alarm Date Data Register 0x00000000 ALMMON 0xEA30_0064 R W Alarm Month Data Register 0x00000000 ALMYEAR 0xEA30_0068 R W Alarm Year Data Register 0x00000000 BCDSEC 0xEA30_0070 R W BCD Second Register Undefined BCDMIN 0xEA30_0074 R W BCD Minute Register Undefined BCDHOUR 0xEA30_0078 R W BCD Hour Register Undefined ...

Page 618: ...ific bits of INTP register by writing 1 s to the bits that you want to clear regardless of RTCEN value INTP Bit Description Reset Value Reserved 31 2 Reserved 0 ALARM 1 Alarm interrupt pending bit 0 No interrupt occurred 1 Interrupt occurred 0 Time TIC 0 Time TIC interrupt pending bit 0 No interrupt occurred 1 Interrupt occurred 0 ...

Page 619: ...cription Reset Value Reserved 31 9 Reserved 0 TICEN 8 Tick timer enable 0 Disables 1 Enables 0 TICCKSEL 7 4 Tick timer sub clock selection 4 b0000 32768 hz 4 b0001 16384 hz 4 b0010 8192 hz 4 b0011 4096 hz 4 b0100 2048 hz 4 b0101 1024 hz 4 b0110 512 hz 4 b0111 256 hz 4 b1000 128 hz 4 b1001 64 hz 4 b1010 32 hz 4 b1011 16 hz 4 b1100 8 hz 4 b1101 4 hz 4 b1110 2 hz 4 b1111 1 hz 4 b0000 CLKRST 3 RTC clo...

Page 620: ...at the RTCALM register generates the alarm signal through both ALMINT and PMWKUP in power down mode but only through ALMINT in the normal operation mode RTCALM Bit Description Reset Value Reserved 31 7 Reserved 0 ALMEN 6 Alarm global enable 0 Disables 1 Enables 0 YEAREN 5 Year alarm enable 0 Disables 1 Enables 0 MONEN 4 Month alarm enable 0 Disables 1 Enables 0 DATEEN 3 Date alarm enable 0 Disable...

Page 621: ...MIN Bit Description Reset Value Reserved 31 7 Reserved 0 6 4 BCD value for alarm minute 0 5 000 MINDATA 3 0 0 9 0000 13 7 ALARM HOUR DATA REGISTER ALMHOUR R W ADDRESS 0XEA30_005C ALMHOUR Bit Description Reset Value Reserved 31 6 Reserved 0 5 4 BCD value for alarm hour 0 2 00 HOURDATA 3 0 0 9 0000 13 8 ALARM DATE DATA REGISTER ALMDATE R W ADDRESS 0XEA30_0060 ALMDATE Bit Description Reset Value Rese...

Page 622: ...LMYEAR R W ADDRESS 0XEA30_0068 ALMYEAR Bit Description Reset Value Reserved 31 8 Reserved 0 7 4 BCD value for year 0 9 0x0 YEARDATA 3 0 0 9 0x0 13 11 BCD SECOND REGISTER BCDSEC R W ADDRESS 0XEA30_0070 BCDSEC Bit Description Reset Value Reserved 31 7 Reserved 6 4 BCD value for second 0 5 SECDATA 3 0 0 9 13 12 BCD MINUTE REGISTER BCDMIN R W ADDRESS 0XEA30_0074 BCDMIN Bit Description Reset Value Rese...

Page 623: ...E R W ADDRESS 0XEA30_007C BCDDAY Bit Description Reset Value Reserved 31 6 Reserved 5 4 BCD value for date 0 3 DATEDATA 3 0 0 9 13 15 BCD DAY REGISTER BCDDAY R W ADDRESS 0XEA30_0080 BCDDAY Bit Description Reset Value Reserved 31 3 Reserved DAYDATA 2 0 BCD value for a day of the week 1 7 13 16 BCD MONTH REGISTER BCDMON R W ADDRESS 0XEA30_0084 BCDMON Bit Description Reset Value Reserved 31 5 Reserve...

Page 624: ...AR R W ADDRESS 0XEA30_0088 BCDYEAR Bit Description Reset Value Reserved 31 8 Reserved 7 4 BCD value for year 0 9 YEARDATA 3 0 0 9 13 18 TICK COUNTER REGISTER CURTICCNT R ADDRESS 0XEA30_0090 CURTICCNT Bit Description Reset Value Tick counter observation 31 0 Current tick count value ...

Page 625: ...es infrared IR transmit receive one or two stop bit insertion 5 bit 6 bit 7 bit or 8 bit data width and parity checking Each UART contains a baud rate generator a transmitter a receiver and a control unit as shown in Figure 8 1 1 The baud rate generator is clocked by PCLK or UCLK The transmitter and the receiver contain 64 byte FIFOs and data shifters The data to be transmitted is written to FIFO ...

Page 626: ...ding Register Non FIFO mode Receive FIFO Register FIFO mode Receive Holding Register Non FIFO mode only In FIFO mode all 64 Byte of Buffer register are used as FIFO register In non FIFO mode only 1 Byte of Buffer register is used as Holding register Transmit Shifter Transmit Buffer Register 64 Byte Receive Shifter Receive Buffer Register 64 Byte Figure 8 1 1 UART Block Diagram ...

Page 627: ...rwritten the old data before the old data has been read Parity error indicates that the receiver has detected an unexpected parity condition Frame error indicates that the received data does not have a valid stop bit Break condition indicates that the RxDn input is held in the logic 0 state for more than one frame transmission time Receive time out condition occurs if no data is received during th...

Page 628: ...tware because the AFC does not support the RS 232C interface 3 6 INTERRUPT DMA REQUEST GENERATION Each UART of the S5PC100 has seven status Tx Rx Error signals namely Overrun error Parity error Frame error Break Receive buffer data ready Transmit buffer empty and Transmit shifter empty These conditions are indicated by the corresponding UART status register UTRSTATn UERSTATn The Overrun Error Pari...

Page 629: ...IFO Generated if the number of data in FIFO does not reaches Rx FIFO trigger Level and does not receive any data during 3 word time receive time out This interval follows the setting of Word Length bit Generated by receive holding register whenever receive buffer becomes full Tx interrupt Generated if transmit data reaches the trigger level of transmit FIFO Tx FIFO trigger Level Generated by trans...

Page 630: ...Receives the five Characters including two errors Time Sequence Flow Error Interrupt Note 0 If no character is read out 1 A B C D and E is received 2 After A is read out Frame error in B interrupt occurs The B has to be read out 3 After B is read out 4 After C is read out Parity error in D interrupt occurs The D has to be read out 5 After D is read out 6 After E is read out ...

Page 631: ...e the transmit pulse comes out at a rate of 3 16 the normal serial transmit rate If the transmit data bit is 0 In IR receive mode the receiver must detect the 3 16 pulsed period to recognize a 0 value Refer frame timing diagrams shown in Figure 8 1 and Figure 8 1 IrDA Tx Encoder 0 1 0 1 IrDA Rx D ecoder TxD R xD TxD IRS RxD RE UAR T Block Figure 8 1 4 IrDA Function Block Diagram Start Bit Stop Bit...

Page 632: ...Data Bits IR Transmit Frame Bit Time Pulse Width 3 16 Bit Frame 0 0 0 0 1 1 1 1 1 Figure 8 1 6 Infra Red Transmit Mode Frame Timing Diagram 0 Start Bit Stop Bit Data Bits IR Receive Frame 0 0 0 0 1 1 1 1 1 Figure 8 1 7 Infra Red Receive Mode Frame Timing Diagram ...

Page 633: ... be set as the following sequence 1 Set Line control register ULCON to set a frame format 2 Set Control register UCON without Transmit mode bits and Receive mode bits 3 Set 1 b1 on TX FIFO Reset bit and RX FIFO Reset bit of FIFO control register UFCON to reset TX FIFO and RX FIFO 4 Set FIFO control register UFCON to set Triger Levels and Enable TX FIFO and RX FIFO 5 Set Modem control register UMCO...

Page 634: ...Sn Output Request to Send active low for UART1 XuRTSn 1 muxed UART2_RXD Input Receive Data for UART2 XuRXD 2 muxed UART2_TXD Output Transmit Data for UART2 XuTXD 2 muxed UART2_CTSn Input Clear to Send active low for UART2 XuRXD 3 muxed UART2_RTSn Output Request to Send active low for UART2 XuTXD 3 muxed UART3_RXD Input Receive Data for UART3 XuRXD 3 muxed UART3_TXD Output Transmit Data for UART3 X...

Page 635: ...Register 0x0 UINTSP0 0xEC00_0034 R W UART Channel 0 Interrupt Source Pending Register 0x0 UINTM0 0xEC00_0038 R W UART Channel 0 Interrupt Mask Register 0x0 ULCON1 0xEC00_0400 R W UART Channel 1 Line Control Register 0x00 UCON1 0xEC00_0404 R W UART Channel 1 Control Register 0x00 UFCON1 0xEC00_0408 R W UART Channel 1 FIFO Control Register 0x0 UMCON1 0xEC00_040C R W UART Channel 1 Modem Control Regi...

Page 636: ... UINTSP2 0xEC00_0834 R W UART Channel 2 Interrupt Source Pending Register 0x0 UINTM2 0xEC00_0838 R W UART Channel 2 Interrupt Mask Register 0x0 ULCON3 0xEC00_0C00 R W UART Channel 3 Line Control Register 0x00 UCON3 0xEC00_0C04 R W UART Channel 3 Control Register 0x00 UFCON3 0xEC00_0C08 R W UART Channel 3 FIFO Control Register 0x0 UMCON3 0xEC00_0C0C R W UART Channel 3 Modem Control Register 0x0 UTR...

Page 637: ...to use the Infrared mode 0 Normal mode operation 1 Infrared Tx Rx mode 0 Parity Mode 5 3 Specifies the type of parity generation to be performed and checking during UART transmit and receive operation 0xx No parity 100 Odd parity 101 Even parity 110 Parity forced checked as 1 111 Parity forced checked as 0 000 Number of Stop Bit 2 Specifies how many stop bits are used to signal end of frame signal...

Page 638: ...tant Rx buffer receives the data in Non FIFO mode or reaches Rx FIFO Trigger Level in FIFO mode 1 Level Interrupt is requested while Rx buffer is receiving data in Non FIFO mode or reaches Rx FIFO Trigger Level in FIFO mode 0 Rx Time Out Enable 7 Enables Disables Rx time out interrupts if UART FIFO is enabled The interrupt is a receive interrupt 0 Disable 1 Enable 0 Rx Error Status Interrupt Enabl...

Page 639: ...0 NOTE 1 DIV_VAL UBRDIVn num of 1 s in UDIVSLOTn 16 Refer to UART Buad Rate Configure Registers 2 RX interrupt type must be set to pulse for every transfer in S5PC100 3 If the UART does not reach the FIFO trigger level and does not receive data during 3 word time in DMA receive mode with FIFO the Rx interrupt is generated receive time out and you must check the FIFO status and read out the rest 4 ...

Page 640: ...he trigger level of transmit FIFO 00 Empty 01 16 byte 10 32 byte 11 48 byte 00 Rx FIFO Trigger Level 5 4 Determines the trigger level of receive FIFO 00 1 byte 01 8 byte 10 16 byte 11 32 byte 00 Reserved 3 0 Tx FIFO Reset 2 Auto cleared after resetting FIFO 0 Normal 1 Tx FIFO reset 0 Rx FIFO Reset 1 Auto cleared after resetting FIFO 0 Normal 1 Rx FIFO reset 0 FIFO Enable 0 0 Disable 1 Enable 0 NOT...

Page 641: ... 48 bytes 011 If RX FIFO contains 40 bytes 100 If RX FIFO contains 32 bytes 101 If RX FIFO contains 24 bytes 110 If RX FIFO contains 16 bytes 111 If RX FIFO contains 8 bytes 000 Auto Flow Control AFC 4 0 Disables 1 Enables 0 Modem Interrupt Enable 3 0 Disables 1 Enables 0 Reserved 2 1 These bits must be 0 00 Request to Send 0 If AFC bit is enabled this value will be ignored In this case the S5PC10...

Page 642: ...empty 1 Transmit buffer empty 1 This bit is automatically set to 1 if transmit buffer register is empty 0 Buffer register is not empty 1 Buffer register is empty In Non FIFO mode Interrupt or DMA is requested In FIFO mode Interrupt or DMA is requested if Tx FIFO Trigger Level is set to 00 Empty If UART uses FIFO check Tx FIFO Count bits and Tx FIFO Full bit in UFSTAT register instead of this bit 1...

Page 643: ...eceived Interrupt is requested 0 Frame Error 2 This bit is automatically set to 1 if a frame error occurs during the receive operation 0 No frame error during receive 1 Frame error Interrupt is requested 0 Parity Error 1 This bit is automatically set to 1 if a parity error occurs during the receive operation 0 No parity error during receive 1 Parity error Interrupt is requested 0 Overrun Error 0 T...

Page 644: ...FSTAT3 in the UART block UFSTATn Bit Description Reset Value Reserved 15 0 Tx FIFO Full 14 This bit is automatically set to 1 if the transmitted FIFO is full during transmit operation 0 0 byte Tx FIFO data 63 byte 1 Full 0 Tx FIFO Count 13 8 Number of data in Tx FIFO 0 Reserved 7 0 Rx FIFO Full 6 This bit is automatically set to 1 if the received FIFO is full during receive operation 0 0 byte Rx F...

Page 645: ...he UART block UMSTAT0 Bit Description Reset Value Reserved 7 5 reserved 000 Delta CTS 4 This bit indicates that the nCTS input to the S5PC100 has changed its state since the last time it was read by CPU Refer Figure 8 1 0 Has not changed 1 Has changed 0 Reserved 3 1 Reserved 00 Clear to Send 0 0 CTS signal is not activated nCTS pin is high 1 CTS signal is activated nCTS pin is low 0 nCTS Delta CTS...

Page 646: ... Value UTXHn 7 0 Transmit data for UARTn 6 9 UART RECIVE BUFFER REGISTER HOLDING REGISTER FIFO REGISTER URXH0 R Address 0xEC00_0024 URXH1 R Address 0xEC00_0424 URXH2 R Address 0xEC00_0824 URXH3 R Address 0xEC00_0C24 There are four UART receive buffer registers namely URXH0 URXH1 URXH2 and URXH3 in the UART block URXHn has an 8 bit data for received data URXHn Bit Description Reset Value URXHn 7 0 ...

Page 647: ...15 0 Baud rate division value When UART clock source is PCLK UBRDIVn must be more than 0 UBRDIVn 0 NOTE If UBRDIV value is 0 UART baudrate is not affected by UDIVSLOT value 6 11 UART CHANNEL DIVIDING SLOT REGISTER UDIVSLOT0 R W Address 0xEC00_002C UDIVSLOT1 R W Address 0xEC00_042C UDIVSLOT2 R W Address 0xEC00_082C UDIVSLOT3 R W Address 0xEC00_0C2C UDIVSLOT n Bit Description Reset Value UDIVSLOTn 1...

Page 648: ... MHz UBRDIVn and UDIVSLOTn are DIV_VAL 40000000 115200 x 16 1 21 7 1 20 7 UBRDIVn 20 integer part of DIV_VAL num of 1 s in UDIVSLOTn 16 0 7 then num of 1 s in UDIVSLOTn 11 so UDIVSLOTn can be 16 b1110_1110_1110_1010 or 16 b0111_0111_0111_0101 etc We recommend selecting UDIVSLOTn as described in the following table Num of 1 s UDIVSLOTn Num of 1 s UDIVSLOTn 0 0x0000 0000_0000_0000_0000b 8 0x5555 010...

Page 649: ... allows sufficient time to write the received data to the receive FIFO 6 12 UART INTERRUPT PENDING REGISTER UINTP0 R W Address 0xEC00_0030 UINTP1 R W Address 0xEC00_0430 UINTP2 R W Address 0xEC00_0830 UINTP3 R W Address 0xEC00_0C30 Interrupt pending register contains the information of the interrupts that are generated UINTPn Bit Description Reset Value MODEM 3 Generates Modem interrupt 0 TXD 2 Ge...

Page 650: ...00_0038 UINTM1 R W Address 0xEC00_0438 UINTM2 R W Address 0xEC00_0838 UINTM3 R W Address 0xEC00_0C38 Interrupt mask register contains the information which interrupt source is masked If a specific bit is set to 1 interrupt request signal to Interrupt Controller is not generated even though corresponding interrupt is generated NOTE Even in such a case the corresponding bit of UINTSPn register is se...

Page 651: ...S5PC100 USER S MANUAL REV1 0 UART 8 1 27 Figure 8 1 10 UINTSP UINTP and UINTM block diagram ...

Page 652: ...UART S5PC100 USER S MANUAL REV1 0 8 1 28 NOTES ...

Page 653: ...ON Multi master I2 C bus control status register I2CSTAT Multi master I2 C bus Tx Rx data shift register I2CDS Multi master I2 C bus address register I2CADD If the I2 C bus is free the SDA and SCL lines should be both at High level A High to Low transition of SDA initiates a Start condition A Low to High transition of SDA initiates a Stop condition while SCL remains steady at High Level The master...

Page 654: ... a data transfer on the SDA line can be initiated and SCL signal generated A Start condition transfers one byte serial data over the SDA line and a Stop condition terminates the data transfer A Stop condition is a Low to High transition of the SDA line while SCL is High The master generates Start and Stop conditions The I2 C bus gets busy if a Start condition is generated A Stop condition frees th...

Page 655: ...bus is operating in Master mode master transmit the address field Each byte should be followed by an acknowledgement ACK bit The MSB bit of the serial data and addresses are sent first NOTES 1 S Start rS Repeat Start P Stop A Acknowledge 2 From Master to Slave From Slave to Master Write Mode Format with 7 bit Addresses 0 Write Data Transferred Data Acknowledge S Slave Address 7bits R W A P DATA 1B...

Page 656: ...d for the one byte data transfer The master generates the clock pulse required to transmit the ACK bit The transmitter releases the SDA line by making the SDA line High if the ACK clock pulse is received The receiver drives the SDA line Low during the ACK clock pulse so that the SDA keeps Low during the High period of the ninth SCL pulse The software I2CSTAT enables or disables ACK bit transmit fu...

Page 657: ...ts the address bit on the SDA line because the SDA line is likely to get Low rather than to keep High Assume that one master generates a Low as first address bit while the other master is maintaining High In this case both masters detect Low on the bus because the Low status is superior to the High status in power If this happens Low as the first bit of address generating master gets the mastershi...

Page 658: ...smitted After ACK period interrupt is pending Write 0xD0 M T Stop to I2CSTAT Write new data transmitted to I2CDS Stop Clear pending bit to resume The data of the I2CDS is shifted to SDA START Master Tx mode has been configured Clear pending bit Wait until the stop condition takes effect END Y N Figure 8 2 6 Operations for Master Transmitter Mode ...

Page 659: ...slave address is transmitted After ACK period interrupt is pending Write 0x90 M R Stop to I2CSTAT Read a new data from I2CDS Stop Clear pending bit to resume SDA is shifted to I2CDS START Master Rx mode has been configured Clear pending bit Wait until the stop condition takes effect END Y N Figure 8 2 7 Operations for Master Receiver Mode ...

Page 660: ...es I2CADD and I2CDS the received slave address Write data to I2CDS The I2C address match interrupt is generated Clear pending bit to resume The data of the I2CDS is shifted to SDA START Slave Tx mode has been configured END Matched N Y Stop Interrupt is pending N Y Figure 8 2 8 Operations for Slave Transmitter Mode ...

Page 661: ...2C compares I2CADD and I2CDS the received slave address Read data from I2CDS The I2C address match interrupt is generated Clear pending bit to resume SDA is shifted to I2CDS START Slave Rx mode has been configured END Matched N Y Stop Interrupt is pending N Y Figure 8 2 9 Operations for Slave Receiver Mode ...

Page 662: ...us Interface0 control register 0x0X I2CSTAT0 0xEC10_0004 R W I2 C Bus Interface0 control status register 0x00 I2CADD0 0xEC10_0008 R W I2 C Bus Interface0address register 0xXX I2CDS0 0xEC10_000C R W I2 C Bus Interface0transmit receive data shift register 0xXX I2CLC0 0xEC10_0010 R W I2 C Bus Interface0multi master line control register 0x00 I2CCON1 0xEC20_0000 R W I2 C Bus Interface1 control registe...

Page 663: ...Resume the operation If write 1 1 Interrupt is pending If read 2 N A If write 0 Transmit clock value 4 3 0 I2 C Bus transmit clock prescaler I2 C Bus transmit clock frequency is determined by this 4 bit prescaler value according to the following formula Tx clock I2CCLK I2CCON 3 0 1 Undefined NOTES 1 Interfacing with EEPROM the ACK generation may be disabled before reading the last data in order to...

Page 664: ...omatically just after the start signal 0 Serial output 4 I2 C bus data output enable disable bit 0 Disable Rx Tx 1 Enable Rx Tx 0 Arbitration status flag 3 I2 C bus arbitration procedure status flag bit 0 Bus arbitration successful 1 Bus arbitration failed during serial I O 0 Address as slave status flag 2 I2 C bus address as slave status flag bit 0 Cleared when START STOP condition was detected 1...

Page 665: ...Bit Description Reset Value Data shift 7 0 8 bit data shift register for I2 C bus Tx Rx operation If serial output enable 1 in the I2CSTAT I2CDS is write enabled The I2CDS value is read any time regardless of the current serial output enable bit I2CSTAT setting Undefined 3 5 MULTI MASTER I2 C BUS LINE CONTROL REGISTER I2CLC0 R W Address 0xEC10_0014 I2CLC1 R W Address 0xEC20_0014 I2CLC Bit Descript...

Page 666: ...lly and received shifted in serially SPI supports the protocols for National Semiconductor Microwire and Motorola Serial Peripheral Interface 2 FEATURES Full duplex 8 16 32 bit shift register for TX RX 8 bit Prescaler Logic 3 clocks source Supports 8 bit 16 bit 32 bit bus interface Supports the Motorola SPI protocol and National Semiconductor Microwire Supports two independent transmit and receive...

Page 667: ...efore packets are transmitted or received 2 1 2 FIFO Access The SPI in S5PC100x supports CPU access and DMA access to FIFOs Data size of CPU access and DMA access to FIFOs are selected from 8 bit 16 bit or 32 bit data If 8 bit data size is selected valid bits are from 0 bit to 7 bit CPU accesses are normally on and off by trigger threshold This is user defined The trigger level of each FIFO is set...

Page 668: ...rds a chip is selected when XspiCS input is 0 XspiCS can be selected auto control or manual control When you use manual control mode AUTO_N_MANUAL must be cleared Default value is 0 XspiCS level is controlled by NSSOUT bit When you use audio control mode AUTO_N_MANUAL must be set XspiCS toggled between packet and packet automatically Inactive period of XspiCS is controlled by NCS_TIME_COUNT NSSOUT...

Page 669: ... 1 CPHA 1 Format B Cycle MOSI 1 2 3 4 5 6 7 8 MSB 6 5 4 3 2 1 LSB 6 5 4 3 2 1 LSB MSB SPICLK MISO MSB CPOL 1 CPHA 0 Format A Cycle MOSI 1 2 3 4 5 6 7 8 6 5 4 3 2 1 LSB 6 5 4 3 2 1 LSB SPICLK MISO LSB CPOL 0 CPHA 1 Format B Cycle MOSI 1 2 3 4 5 6 7 8 MSB 6 5 4 3 2 1 LSB 6 5 4 3 2 1 LSB MSB SPICLK MISO MSB CPOL 0 CPHA 0 Format A LSB MSB MSB MSB MSB of previous frame LSB LSB of next frame LSB LSB of ...

Page 670: ...sed to get data from slave output port Data are transmitted to master through this port in slave mode Out when used as slave In when used as master XspiMISO 0 XspiMISO 1 Xmmc2DATA 0 muxed SPI0_MOSI SPI1_MOSI SPI2_MOSI In Out This port is the output port in Master mode This port is used to transfer data from master output port Data are received from master through this port in slave mode Out when u...

Page 671: ...S Ch0 0xEC30_0014 R SPI Status Register 0x0 SPI_STATUS Ch1 0xEC40_0014 R SPI Status Register 0x0 SPI_STATUS Ch2 0xEC50_0014 R SPI Status Register 0x0 SPI_TX_DATA Ch0 0xEC30_0018 W SPI TX DATA Register 0x0 SPI_TX_DATA Ch1 0xEC40_0018 W SPI TX DATA Register 0x0 SPI_TX_DATA Ch2 0xEC50_0018 W SPI TX DATA Register 0x0 SPI_RX_DATA Ch0 0xEC30_001C R SPI RX DATA Register 0x0 SPI_RX_DATA Ch1 0xEC40_001C R ...

Page 672: ...ansfer Type CPOL CPHA set 2 Set Clock configuration register 3 Set SPI MODE configuration register 4 Set SPI INT_EN register 5 Set Packet count configuration register if necessary 6 Set Tx or Rx Channel on 7 Set nSSout low to start Tx or Rx operation a Set nSSout Bit to low then start TX data writing b If auto chip selection bit is set should not control nSSout ...

Page 673: ... SLAVE 4 Whether SPI Channel is Master or Slave 0 Master 1 Slave 0 CPOL 3 Determines whether active high or active low clock 0 Active High 1 Active Low 0 CPHA 2 Select one of the two fundamentally different transfer format 0 Format A 1 Format B 0 RX_CH_ON 1 SPI Rx Channel On 0 Channel Off 1 Channel On 0 TX_CH_ON 0 SPI Tx Channel On 0 Channel Off 1 Channel On 0 4 2 2 Clock Configuration Register CL...

Page 674: ...to 63 The value means byte number in TX FIFO 0 Reserved 4 3 Reserved RX_DMA_SW 2 Rx DMA mode enable disable 0 Disables DMA Mode 1 Enables DMA Mode 0 TX_DMA_SW 1 Tx DMA mode on off 0 Disables DMA Mode 1 Enables DMA Mode 0 DMA_TYPE 0 DMA transfer type single or 4 busts 0 single 1 4 burst DMA transfer size must be set as the same size in SPI DMA 0 Channel Transfer size must be smaller than Bus Transf...

Page 675: ...N_RX_OVERRUN 5 Interrupt Enable for RxOverrun 0 Disable 1 Enable 0 INT_EN_RX_UNDERRUN 4 Interrupt Enable for RxUnderrun 0 Disable 1 Enable 0 INT_EN_TX_OVERRUN 3 Interrupt Enable for TxOverrun 0 Disable 1 Enable 0 INT_EN_TX_UNDERRUN 2 Interrupt Enable for TxUnderrun In slave mode this bit must be clear first after turning on slave TX path 0 Disable 1 Enable 0 INT_EN_RX_FIFO_RDY 1 Interrupt Enable f...

Page 676: ...3 Data level in RX FIFO 0 64 byte 0 TX_FIFO_LVL 12 6 Data level in TX FIFO 0 64 byte 0 RX_OVERRUN 5 Rx Fifo overrun error 0 No Error 1 Overrun Error 0 RX_UNDERRUN 4 Rx Fifo underrun error 0 No Error 1 Underrun Error 0 TX_OVERRUN 3 Tx Fifo overrun error 0 No Error 1 Overrun Error 0 TX_UNDERRUN 2 Tx FIFO underrun error Tx FIFO underrun error is occurred if TX FIFO is empty in slave mode no empty sta...

Page 677: ...ister SPI_RX_DATA0 R Address 0xEC30_001C SPI_RX_DATA1 R Address 0xEC40_001C SPI_RX_DATA2 R Address 0xEC50_001C SPI_RX_DATAn Bit Description Reset Value RX_DATA 31 0 This field contains the data to be received over the SPI channel 0 4 2 9 Packet Count Register PACKET_CNT_REG0 R W Address 0xEC30_0020 PACKET_CNT_REG1 R W Address 0xEC40_0020 PACKET_CNT_REG2 R W Address 0xEC50_0020 PACKET_CNT_REGn Bit ...

Page 678: ...s 0xEC50_0024 PENDING_CLR_REGn Bit Description Reset Value TX_UNDERRUN_CLR 4 TX underrun pending clear bit 0 Non Clear 1 Clear 0 TX_OVERRUN_CLR 3 TX overrun pending clear bit 0 Non Clear 1 Clear 0 RX_UNDERRUN_CLR 2 RX underrun pending clear bit 0 Non clear 1 Clear 0 RX_OVERRUN_CLR 1 RX overrun pending clear bit 0 Non Clear 1 Clear 0 TRAILING_CLR 0 Trailing pending clear bit 0 Non Clear 1 Clear 0 ...

Page 679: ...AP_EN 0 Swap enable 0 Normal 1 Swap 0 Data size must be larger than swap size 4 2 12 FeedBack Clock Selection FB_CLK_SEL Ch0 R W Address 0xEC30_002C FB_CLK_SEL_REG0 R W Address 0xEC30_002C FB_CLK_SEL_REG1 R W Address 0xEC40_002C FB_CLK_SEL_REG2 R W Address 0xEC50_002C FB_CLK_SELn Bit Description Reset Value FB_CLK_SEL 1 0 00 0nS additional delay 01 3nS additional delay 10 6nS additional delay 11 9...

Page 680: ...U burden This makes it easy to adjust the internal FIFO sizes A user can program the core by accessing 16 internal registers At the time of receiving the infrared pulses core detects three kinds of line errors namely z CRC Error z PHY Error z Payload Length Error 2 FEATURE 1 IrDA Specification compliant Support IrDA 1 1 physical layer specification 4Mbps 1 152Mpbs and 0 576Mbps 2 Supports FIFO ope...

Page 681: ...CR Iinterrupt Control and payload length store IER ICR RXFLH RXFLL TXFLH TXFLL TX FIFO Control THR PLR RX FIFO Control RBR PLL FIR Mod Demodl MIR Mod Demodl MUX M SCLK_IRDA 48MHz INTERRUPT DMA IRRX IRTX HRESETn TX FIFO RAM RX FIFO RAM IRSDBW MOD DEMOD MOD DEMOD AHB BUS Figure 8 4 1 Block Diagram ...

Page 682: ...ee different kinds of errors which may occur in the middle of transmission These are Phy Error Frame Length Error and CRC error The last one CRC error is checked after the entire payload data is received The micro controller monitors the error status of the received frame by reading the Line Status Register LSR at the end of the frame receiving The below diagram shows the frame structure of the FI...

Page 683: ...d Frame data with error crc abort by underrun abort 2u Pulse transmit sip pul_end ena 0 1 2 3 4 5 6 7 stp_end ena pul_end ena Figure 8 4 2 FIR Modulation Process Figure 8 4 2 shows the FIR modulation state machine The FIR transmission mode is selected by programming ACR register If an underrun condition occurs the state machine appends the payload with error CRC data and terminates the transmissio...

Page 684: ... stp_end ena str_end ena prebyte Pay Load Detect CRC check 2 phy_err crc_decod_start Stop Flag Detect Figure 8 4 3 FIR Demodulation Process Figure 8 4 3 shows FIR demodulation state machine The state machine starts if ACR register bit 6 is set to logic high The incoming data is depacketized by removing preamble and start flag and stop flag 4PPM decoding and CRC decoding is also carried out ...

Page 685: ...n MIR mode have the core insert zero bit per every 5 consecutive ones in transmission mode In receiving mode the stuffed bit should be removed Three different kinds of errors CRC PHY and frame length error is reported to the microcontroller in receiving mode by reading the LSR register The diagram below shows the data structure of MIR frame STA STA Link layer frame Payload CRC16 STO STA Beginning ...

Page 686: ...errun abort 2u Pulse transmit sip pul_end ena 0 stp_end ena pul_end ena 1 2 3 4 5 6 str_end Figure 8 4 5 MIR Modulation Process Figure 8 4 5 shows MIR modulation state machine This machine works very similarly with FIR modulation state machine The major difference is that the MIR data transmission needs bit stuffing After 5 consecutive 1 a zero data should be stuffed in MIR payload data The state ...

Page 687: ...cess Figure 8 4 6 shows the MIR demodulation state machine Basically it has similar structure with FIR demodulation state machine Instead of having 4 PPM demodulation phase it has the stage of removing stuffed bits from payload data stream Since the MIR data stream does not have preamble data the preamble start flag data detection stage in MIR demodulation is simplified to start flag detection sta...

Page 688: ...gister to select the number of preamble or start flag and TX threshold level 4 Program the RXFLL and RXFLH register maximum available receive bytes in frame 5 Program the TXFLL and TXFLH register transmit bytes in transmission frame 6 Program the FCR registers FIFO size and RX threshold level 7 Program the IER registers the types of interrupt 8 Program the ACR registers TX enable or RX enable 9 Pr...

Page 689: ...I O Description Pad Type IrDA_RXD Input IrDA Rx signal XuTXD 3 Muxed IrDA_TXD Output IrDA Tx signal XuRXD 3 Muxed IrDA_SDBW Output IrDA Transceiver control Shutdown Bandwidth XuCLK Muxed NOTE Type field indicates whether pads are dedicated to the signal or pads are connected to the multiplexed signals ...

Page 690: ...0_0018 R W IrDA FIFO Control Register 0x00 IrDA _PLR 0xEC60_001C R W IrDA Preamble Length Register 0x12 IrDA_RBR IrDA_THR 0xEC60_0020 R W IrDA Receiver Transmitter Buffer Register 0x00 IrDA _TXNO 0xEC60_0024 R The total number of data bytes remained in Tx FIFO 0x00 IrDA _RxNO 0xEC60_0028 R The total number of data bytes remained in Rx FIFO 0x00 IrDA _TXFLL 0xEC60_002C R W IrDA Transmit Frame Lengt...

Page 691: ...smission of a frame by writing a 1 to bit 1 Neither the end flag nor the CRC bits are appended to the frame The receiver finds the frame with the abort pattern in the MIR mode and a PHY error in the FIR mode The CPU must reset the TX FIFO and reset this bit by writing a 0 to bit 1 before next frame is transmitted 0 SD BW 0 This signal controls IrDA_SDBW output signal It is used for controlling mod...

Page 692: ...Underrun 5 Enables transmitter under run interrupt 0 Last Byte Detect 4 Detect stop flag interrupt enable If this bit is set to 1 an interrupt signal is activated if the last byte of the received data frame comes into the demodulation block and CRC decoding is finished 0 Rx Overrun 3 Enables receiver over run interrupt 0 Last Byte Read from Rx FIFO 2 Bit 2 enables last byte from RX FIFO interrupt ...

Page 693: ...is cleared by serving the under run 0 Last Byte Detect 4 Detects last byte of a frame interrupt pending If the corresponding interrupt enable bit is active bit 4 is set to 1 if the demodulation block detects the last byte of a received frame and the CRC decoding is finished Bit 4 is cleared if it is read 0 Rx Overrun 3 RX FIFO over run interrupt If corresponding interrupt enable bit is set bit 3 i...

Page 694: ...ared if the microcontroller reads the IrDA_LSR register If this error is detected current frame reception is terminated Data receiving is stopped until the next BOF is detected Bit 4 is cleared to 0 if the IrDA_LSR register is read by the microcontroller 0 PHY Error 3 PHY error In FIR mode It is set to a 1 if an illegal 4PPM symbol is received In IrDA_MIR mode if an abort pattern more than 7 conse...

Page 695: ...he CPU reads this register 0 RX FIFO CLEAR NOTIFICATION 3 This bit will be activated if the FIFO clear is over This bit is cleared by the CPU reads this register 0 Tx FIFO Reset 2 TX FIFO reset If set to 1 bit 2 clears all bytes in the transmitter FIFO and reset its counter to 0 A 1 written to bit 2 is self clearing 0 Rx FIFO Reset 1 RX FIFO reset If set to 1 bit 1 clears all bytes in the receiver...

Page 696: ... Number of start flags in MIR mode The number of start flags to be transmitted at the beginning of a frame is equal to the IrDA_PLR 3 0 value The minimum value is 3 0010 6 9 IRDA RECEIVER TRANSMITTER BUFFER REGISTER IRDA_RBR IRDA_THR R W ADDRESS 0XEC60_0020 IrDA _RBR Bit Description Initial State Rx Tx Data 7 0 Received data If read data Data to transmit If write data 0x00 6 10 IRDA TOTAL NUMBER O...

Page 697: ... transmitted 00 6 14 IRDA RECEIVER FRAME LENGTH REGISTER LOW IRDA_RXFLL R W ADDRESS 0XEC60_0034 IrDA _RXFLL Bit Description Initial State Rx frame length low 7 0 RXFLL stores the lower 8 bits of the maximum byte number of the frame to be received 00 6 15 IRDA RECEIVER FRAME LENGTH REGISTER HIGH IRDA_RXFLH R W ADDRESS 0XEC60_0038 IrDA _RXFLH Bit Description Initial State Reserved 7 6 00 Rx frame le...

Page 698: ...n the Message Handler The functions implemented are Acceptance Filtering Transfer of messages between the CAN Core and the Message RAM and Handling of transmission requests as well as the generation of the module interrupt The register set of the C_CAN is accessed directly by an external CPU via the module interface These registers are used to control configure the CAN Core and the Message Handler...

Page 699: ...d to control and configure the C_CAN module Message Handler State Machine that controls the data transfer between the Rx Tx Shift Register of the CAN Core and the Message RAM as well as the generation of interrupts as programmed in the Control and Configuration Registers Module Interface The C_CAN module is delivered with three different interfaces An 8 bit interface for the Motorola HC08 controll...

Page 700: ...the CPU has to set up the Bit Timing Register and each Message Object If a Message Object is not needed it is sufficient to set it s MsgVal bit to not valid Otherwise the whole Message Object has to be initialized Access to the Bit Timing Register and to the BRP Extension Register for the configuration of the bit timing is enabled if both bits Init and CCE in the CAN Control Register are set Reset...

Page 701: ... Object has to be configured before the transmission of this message is requested The transmission of any number of Message Objects may be requested at the same time they are transmitted subsequently according to their internal priority Messages is updated or set to not valid any time even if their requested transmission is still pending The old data is discarded if a message is updated before its...

Page 702: ...nant bit ACK bit overload flag active error flag the bit is rerouted internally so that the CAN Core monitors this dominant bit although the CAN bus may remain in recessive state The Silent Mode is used to analyze the traffic on a CAN bus without affecting it by the transmission of dominant bits Acknowledge Bits Error Frames Figure 8 5 2 shows the connection of signals CAN_TX and CAN_RX to the CAN...

Page 703: ...rs are loaded into the shift register of the CAN Core and the transmission is started If the transmission is complete the Busy bit is reset and the locked IF1 Registers are released A pending transmission is aborted any time by resetting the Busy bit in the IF1 Command Request Register while the IF1 Registers are locked If the CPU has reset the Busy bit a possible retransmission in case of lost ar...

Page 704: ...oop Back Mode Silent Mode or Basic Mode are selected 4 2 APB INTERFACE There are two interfaces to the AMBA APB With APB1 interface the block CCAN_GENERIC is clocked by the APB system clock PCLK For the APB2 interface a clock divider is inserted between APB2 interface and CCAN_GENERIC Please refer to AMBA Specification Rev 2 0 for more details on the ARM AMBA bus The APB2 interface synchronizes wr...

Page 705: ...CCAN S5PC100 USER S MANUAL REV1 0 8 5 8 The structure of the APB2 interface is shown is Figure 8 5 5 Figure 8 5 5 Structure of the C_CAN with APB2 Interface ...

Page 706: ...TOGGLE_WR WR_TOGGLE1 and WR_TOGGLE2 describe a shift register where TOGGLE_WR is clocked by PCLK WR_TOGGLE1 and WR_TOGGLE2 are clocked by CAN_CLK The synchronized write signal SYNC_WRITE is generated by an EXOR of signals WRITE_TOGGLE1 and WRITE_TOGGLE2 see Figure 8 5 6 Two consecutive write accesses must have a minimum distance of eight PCLK periods 2 CAN_CLK periods when frequency PCLK 4 x frequ...

Page 707: ...the requested data is written into the internal register SYNC_PRDATA clocked by CAN_CLK With the second read the data output register PRDATA takes over the value of SYNC_PRDATA see Figure 8 5 7 The two consecutive read accesses must have a minimum distance of nine PCLK periods when frequency PCLK 4 x frequency CAN_CLK Figure 8 5 7 APB2 Read Timing ...

Page 708: ...scription Pad Type CAN0_TX Output CCAN0 TX Data XEINT 28 Muxed CAN0_RX Input CCAN0 RX Data XEINT 29 Muxed CAN1_TX Output CCAN1 TX Data XEINT 30 Muxed CAN1_RX Input CCAM1 RX Data XEINT 31 Muxed NOTE Type field indicates whether pads are dedicated to the signal or pads are connected to the multiplexed signals ...

Page 709: ...e enabled by Test 0x0000 CAN_BRP 0xEC70_0018 R W BRP Extension Register Write enabled by CCE 0x0000 0xEC70_001C reserved 0x0000 CAN_IF1_CR 0xEC70_0020 R W IF1 Command Request 0x0001 CAN_IF1_CM 0xEC70_0024 R W IF1 Command Mask 0x0000 CAN_IF1_M1 0xEC70_0028 R W IF1 Mask1 0xFFFF CAN_IF1_M2 0xEC70_002C R W IF1 Mask2 0xFFFF CAN_IF1_A1 0xEC70_0030 R W IF1 Arbitration 1 0x0000 CAN_IF1_A2 0xEC70_0034 R W ...

Page 710: ...148 0xEC70_015C Reserved 0x0000 CAN_MesVal1 0xEC70_0160 R Message Valid 1 0x0000 CAN_MesVal2 0xEC70_0164 R Message Valid 2 0x0000 0xEC70_0168 0xEC70_017C Reserved 0x0000 CCAN1 CAN_CON 0xEC80_0000 R W CAN Control Register 0x0001 CAN_STS 0xEC80_0004 R W Status Register 0x0000 CAN_ERR 0xEC80_0008 R Error Counter 0x0000 CAN_BT 0xEC80_000C R W Bit Timing Register Write enabled by CCE 0x2301 CAN_INTR 0x...

Page 711: ...ation 2 0x0000 CAN_IF2_MC 0xEC80_0x98 R W IF2 Message Control 0x0000 CAN_IF2_DA1 0xEC80_009C R W IF2 Data A 1 0x0000 CAN_IF2_DA2 0xEC80_00A0 R W IF2 Data A 2 0x0000 CAN_IF2_DB1 0xEC80_00A4 R W IF2 Data B 1 0x0000 CAN_IF2_DB2 0xEC80_00A8 R W IF2 Data B 2 0x0000 0xEC80_00AC 0xEC80_00FC Reserved 0x0000 CAN_TrReq1 0xEC80_00100 R Transmission Request 1 0x0000 CAN_TrReq2 0xEC80_00104 R Transmission Requ...

Page 712: ...N After hardware reset the registers of the C_CAN hold the values described in table 8 5 3 Additionally the busoff state is reset and the output CAN_TX is set to recessive HIGH The value 0x0001 Init 1 in the CAN Control Register enables the software initialization The C_CAN does not influence the CAN bus until the CPU resets Init to 0 The data stored in the Message RAM is not affected by a hardwar...

Page 713: ...ange in the bits BOff or EWarn in the Status Register will generate an interrupt 0 Disabled No Error Status Interrupt is generated R W 0 SIE 2 Status Change Interrupt Enable 1 Enabled An interrupt is generated if a message transfer is successfully completed or a CAN bus error is detected 0 Disabled No Status Change Interrupt is generated R W 0 IE 1 Module Interrupt Enable 1 Enabled Interrupts sets...

Page 714: ...defined in the CAN Specification 0 The CAN Core is in error active state R 0 RxOk 4 Received a Message Successfully 1 Since this bit was last reset to zero by the CPU a message has been successfully received independent of the result of acceptance filtering 0 Since this bit was last reset by the CPU no message has been successfully received This bit is never reset by the CAN Core R W 0 TxOk 3 Tran...

Page 715: ...ery sequence indicating the bus is not stuck at dominant or continuously disturbed 110 CRCError The CRC check sum is incorrect in the message received The CRC received for an incoming message does not match with the calculated CRC for the received data 111 unused If the LEC show the value 7 no CAN bus event was detected since the CPU wrote this value to the LEC 6 2 3 Error Counter CAN0_ERR R W Add...

Page 716: ...e programmed here is used R W 0x3 SJW 7 6 Re Synchronisation Jump Width 0x0 0x3 Valid programmed values are 0 3 The actual interpretation by the hardware of this value is such that one more than the value programmed here is used R W 0 BRP 5 0 Baud Rate Prescaler 0x01 0x3F The value by which the oscillator frequency is divided for generating the bit time quanta The bit time is build up from a multi...

Page 717: ...s the actual value of the CAN_RX Pin 1 The CAN bus is recessive CAN_RX 1 0 The CAN bus is dominant CAN_RX 0 R 0 Tx1 0 6 5 Control of CAN_TX Pin 00 Reset value CAN_TX is controlled by the CAN Core 01 Sample Point is monitored at CAN_TX pin 10 CAN_TX pin drives a dominant 0 value 11 CAN_TX pin drives a recessive 1 value R W 0 LBack 4 Loop Back Mode 1 Enables Loop Back Mode 0 Disables Loop Back Mode ...

Page 718: ...mode Basic One set of registers is used for data transfer to the Message RAM while the other set of registers is used for the data transfer from the Message RAM allowing both processes to be interrupted by each other Figure 6 shows an overview of the two Interface Register sets Each set of Interface Registers consists of Message Buffer Registers controlled by their own Command Registers The Comman...

Page 719: ...ad write action is complete R 0 Reserved 14 6 Reserved R 0 Message Number 5 0 0x01 0x20 Valid Message Number the Message Object in the Message RAM is selected for data transfer 0x00 Not a valid Message Number interpreted as 0x20 0x21 0x3F Not a valid Message Number interpreted as 0x01 0x1F R W 0x01 NOTE If a Message Number that is not valid is written into the Command Request Register the Message ...

Page 720: ...nged If Direction Read 1 Transfer Identifier Mask MDir MXtd to IFx Message Buffer Register 0 Mask bits unchanged R W 0 Arb 5 Access Arbitration Bits If Direction Write 1 Transfer Identifier Dir Xtd MsgVal to message Object 0 Arbitration bits unchanged If Direction Read 1 Transfer Identifier Dir Xtd MsgVal to IFx Message Buffer Register 0 Arbitration bits unchanged R W 0 Control 4 Access Control Bi...

Page 721: ...o Message Object 0 Data Bytes 4 7 unchanged If Direction Read 1 Transfer Data Bytes 4 7 to IFx Message Buffer Register 0 Data Bytes 4 7 unchanged R W 0 6 2 13 IF1 Mask 1 Register CAN0_IF1_M1 R W Address 0xEC70_0028 CAN1_IF1_M1 R W Address 0xEC80_0028 6 2 14 IF2 Mask 1 Register CAN0_IF2_M1 R W Address 0xEC70_0088 CAN1_IF2_M1 R W Address 0xEC80_0088 CANn_IF1_M1 CANn_IF2_M1 Bit Description R W Reset ...

Page 722: ...tended identifier bit IDE has no effect on the acceptance filtering R W 1 MDir 14 Mask Message Direction 1 The message direction bit Dir is used for acceptance filtering 0 The message direction bit Dir has no effect on the acceptance filtering R W 1 Reserved 13 Reserved R 1 Msk28 16 12 0 Identifier Mask 28 16 1 The corresponding identifier bit is used for acceptance filtering 0 The corresponding b...

Page 723: ...18 IF2 Arbitration 1 Register CAN0_IF2_A1 R W Address 0xEC70_0090 CAN1_IF2_A1 R W Address 0xEC80_0090 CANn_IF1_A1 CANn_IF2_A1 Bit Description R W Reset Value ID15 0 15 0 Message Identifier 15 0 R W 0 6 2 19 IF1 Arbitration 2 Register CAN_IF1_A2 R W Address 0xEC70_0034 0xEC80_0034 CAN0_IF1_A2 R W Address 0xEC70_0034 CAN1_IF1_A2 R W Address 0xEC80_0034 ...

Page 724: ...er the TxRqst bit of this Message Object is set if RmtEn 1 b1 0 Direction receive On TxRqst a Remote Frame with the identifier of this Message Object is transmitted On reception of a Data Frame with matching identifier that message is stored in this Message Object R W 0 ID28 16 12 0 Message Identifier ID28 ID0 29 bit Identifier Extended Frame ID28 ID18 11 bit Identifier Standard Frame R W 0 NOTES ...

Page 725: ...andler stores a new message into this object if NewDat was still set the CPU has lost a message 0 No message lost since last time this bit was reset by the CPU R W 00 IntPnd 13 Interrupt Pending 1 This message object is the source of an interrupt The Interrupt Identifier in the Interrupt Register will point to this message object if there is no other interrupt source with higher priority 0 This me...

Page 726: ...a Length Code Data 0 1st data byte of a CAN Data Frame Data 1 2nd data byte of a CAN Data Frame Data 2 3rd data byte of a CAN Data Frame Data 3 4th data byte of a CAN Data Frame Data 4 5th data byte of a CAN Data Frame Data 5 6th data byte of a CAN Data Frame Data 6 7th data byte of a CAN Data Frame Data 7 8th data byte of a CAN Data Frame R W 0 6 2 23 IF1 Message Data A1 CAN_IF1_DA1 R W Address 0...

Page 727: ...ddress 0xEC80_00A0 CANn_IF1_A2 CANn_IF2_A2 Bit Description R W Reset Value Data3 15 8 Data3 Rw 0 Data2 7 0 Data2 RW 0 6 2 27 IF1 Message Data B1 CAN_IF1_DB1 R W Address 0xEC70_0044 0xEC80_0044 CAN0_IF1_DB1 R W Address 0xEC70_0044 CAN1_IF1_DB1 R W Address 0xEC80_0044 6 2 28 IF2 Message Data B1 CAN_IF2_DB1 R W Address 00EC70_0xA4 0xEC80_00A4 CAN0_IF2_DB1 R W Address 0xEC70_00A4 CAN1_IF2_DB1 R W Addr...

Page 728: ...100 CAN0_TrReq1 R W Address 0xEC70_0100 CAN1_TrReq1 R W Address 0xEC80_0100 CANn_TrReq1 Bit Description R W Reset Value TxRqst16 1 15 0 Transmission Request Bits of all Message Objects 1 The transmission of this Message Object is requested and is not yet done 0 This Message Object is not waiting for transmission R 0x0000 6 2 32 Transmission Request Register 2 CAN_TrReq2 R Address 00EC70_0104 0xEC8...

Page 729: ...0124 CAN0_ND2 R W Address 0xEC70_0124 CAN1_ND2 R W Address 0xEC80_0124 CANn_ND2 Bit Description R W Reset Value NewDat32 17 15 0 New Data Bits of all Message Objects 1 The Message Handler or the CPU has written new data into the data portion of this Message Object 0 No new data has been written into the data portion of this Message Object by the Message Handler since last time this flag was cleare...

Page 730: ... R W Address 0xEC70_0160 CAN1_MesVal1 R W Address 0xEC80_0160 CANn_MesVal1 Bit Description R W Reset Value MsgVal16 1 15 0 Message Valid Bits of all Message Objects 1 This Message Object is configured and should be considered by the Message Handler 0 This Message Object is ignored by the Message Handler R 0 6 2 38 Message Valid Register 2 CAN_MesVal2 R Address 00EC70_0164 0xEC80_0164 CAN0_MesVal2 ...

Page 731: ...IEW MIPI HSI is a high speed synchronous serial interface and is defined for communication between two ICs The targeted scenario is an application IC and cellular modem IC communication Data transaction model is peer to peer Figure 8 6 1 MIPI HSI Signal Definition Figure 8 6 2 MIPI HSI Transmitting Example ...

Page 732: ...atus internal status current status next status Configuration Register Select Operation mode Stream mode or Frame mode Fixed channel ID mode Number of channel Generated Error clear TxHOLD state timer and enable TxIDLE state timer and enable TxREQ state timer and enable Interrupt Source Register FIFO empty Break frame transfer done TxHOLD state timeout TxIDLE state timeout TxREQ state timeout Inter...

Page 733: ...Fixed channel ID mode Number of channel Generated Error clear RxACK state timer and enable Rx state timer Configuration Register 1 Rx FIFO clear Rx FIFO timer and enable Interrupt Source Register Rx FIFO full Rx FIFO timeout Data Receiving Done Break frame received Break frame receiving error RxACK state timeout Missed clock input Added clock input Software Reset Register Channel ID Register Data ...

Page 734: ...32bits width MIPI HSI FSM MIPI HSI Parallel To Serial module APB BUS MTx_Data MTx_Flag MTx_Wake MRx_Ready DMAreq Figure 8 6 3 MIPI HSI Interface Controller Tx Module Top Block Diagram APB IF module MIPI HSI Rx FSM MIPI HSI Serial To Parallel module APB BUS MRx_Data MRx_Flag MRx_Wake MTx_Ready Ch ID 3bit Data FIFO 32bit DMAreq Figure 8 6 4 MIPI HSI Interface Controller Rx Module Top Block Diagram ...

Page 735: ...rt Parallel to Serial Block A top level block diagram of the PC card controller is shown below in Figure 8 6 5 DATA 31 0 Channel ID F D PRE_D FLAG DATA MSB LSB Shift data DATA 31 0 DATA 31 0 DATA 31 0 Tx F I F O Data Flag PCLK Data Figure 8 6 5 Parallel to Serial Block Tx Module Part ...

Page 736: ...al to Parallel Block A top level block diagram of the ATAPI controller is shown below in Figure 8 6 6 FLAG DATA DATA 31 0 Channel ID F DATA 31 0 DATA 31 0 DATA 31 0 Rx F I F O Ch ID REG Rising edge shift counter Falling edge shift counter Figure 8 6 6 Serial to Parallel Block Rx Module Part ...

Page 737: ...CONTROLLER 8 6 7 4 CLOCK SCHEME 4 1 TX MODULE PART PARALLEL TO SERIAL BLOCK DATA 31 0 Channel ID F D PRE_D FLAG DATA MSB LSB Shift data DATA 31 0 DATA 31 0 DATA 31 0 Tx F I F O Data Flag PCLK Data Figure 8 6 7 Parallel to Serial Block Tx Module Part ...

Page 738: ...UAL REV1 0 8 6 8 4 2 RX MODULE PART SERIAL TO PARALLEL BLOCK FLAG DATA DATA 31 0 Channel ID F DATA 31 0 DATA 31 0 DATA 31 0 Rx F I F O Ch ID REG Rising edge shift counter Falling edge shift counter Figure 8 6 8 Serial to Parallel Block Rx Module Part ...

Page 739: ...l Timings Parameter Description 1 Mbit s 100 Mbit s 200 Mbit s TNomBit Nominal bit time 1000 ns 10 ns 5 ns TMinEdgeSep Minimum allowed separation of DATA and FLAG signal transitions 500 ns 5 ns 2 5 ns TMaxSkew Maximum allowed time for combined skew and jitter 249 ns 1 5 ns 0 75 ns tRise and tFall Minimum allowed signal rise and fall time 2 ns 2 ns 1 ns ...

Page 740: ...s in Single channel ID mode it attaches channel ID to each data whenever HSI transfers data If HSI is in Burst channel ID mode it attaches channel ID to beginning of data frame and transfers 32 bit data before it enters IDLE state That is reason bandwidth of Burst channel ID mode is wider than that of Single channel ID mode 5 4 STREAM MODE Figure 8 6 11 Example of Stream Mode ...

Page 741: ...Normal Mode Figure 8 6 12 Example of Frame Mode Normal Mode 5 5 2 Break Frame Figure 8 6 13 Break Frame Flag line toggles until the transfer is end if Break frame transfers at least 36 zeros Tx module transferring Break frame does not require to monitor the ready signal unlike normal mode ...

Page 742: ...ake up line to the other side Rx XmsmA 2 Muxed HSI_TX_READY I MIPI HSI ready line from the other side Rx XmsmA 3 Muxed MIPI HSI interface Signals Rx HSI_RXD I MIPI HSI data line XmsmA 4 Muxed HSI_RX_FLAG I MIPI HSI flag line XmsmA 5 Muxed HSI_RX_WAKE I MIPI HSI wake up line from the other side Tx XmsmA 6 Muxed HSI_RX_READ Y O MIPI HSI ready line to the other side Tx XmsmA 7 Muxed Note Type field i...

Page 743: ...S5PC100 USER S MANUAL REV1 0 MIPI HSI INTERFACE CONTROLLER 8 6 13 ...

Page 744: ... R W MIPI HSI Tx Controller Channel ID Register 0x00000000 DATA_REG 0xEC90_001C W MIPI HSI Tx Controller Data Register FIFO input 0x00000000 Table 8 6 4 Rx Controller Register Map Table Register Address R W Description Reset Value STATUS_REG 0xECA0_0000 R MIPI HSI Rx Controller Status Register 0x00010000 CONFIG0_REG 0xECA0_0004 R W MIPI HSI Rx Controller Configuration Register 0x0FFFFF02 CONFIG1_R...

Page 745: ...next_state 30 28 Next state 0x0 reserved 27 0x0 current state 26 24 Current state 0x0 reserved 23 18 0x00 FIFO_full 17 TxFIFO full 0 FIFO not full 1 FIFO full 0x0 FIFO_empty 16 TxFIFO empty 0 FIFO not empty 1 FIFO empty 0x1 reserved 15 13 0x0 tx_rd_point 12 8 TxFIFO read point 0x00 reserved 7 5 0x0 tx_wr_point 4 0 TxFIFO write point 0x00 State register value 000 IDLE 001 TxREQ 010 Tx 011 TxHOLD 10...

Page 746: ...e 0xFF TxREQ time 15 8 TxREQ state timer setting value 0xFF TxHOLD time_en 7 Enable TxHOLD state timer 0 Disables 1 Enables 0x0 TxIDLE time_en 6 Enable TxIDLE state timer 0 Disables 1 Enables 0x0 TxREQ time_en 5 Enable TxREQ state timer 0 Disables 1 Enables 0x0 Err_clr 4 Clear generated Error 0 Stay 1 Clear 0x0 Num of CHID 3 2 Number of channel ID 0x0 Burst_mode 1 Fixed channel ID mode 0 Burst cha...

Page 747: ...1 to clear 0x0 TxFIFO_empty 0 TxFIFO empty interrupt set 1 to clear 0x0 behave 0x1 8 4MIPI HSI TX CONTROLLER INTERRUPT MASK REGISTER INTMSK_REG R W ADDRESS 0XEC90_0010 INTMSK_REG Bit Description Reset Value DMA_req_en 31 Enables DMA request signal 0 Enables 1 Disables 0x1 Reserved 30 5 0x0000000 TxH_timeout_msk 4 TxHOLD state timeout interrupt mask 0 Unmask 1 Mask 0x1 TxI_timeout_msk 3 TxIDLE stat...

Page 748: ...e 31 Break frame transfer in Frame mode In auto clear mode this bit is automatically cleared But the other mode TxDATA send 0 stream during setting 1 at br_frame_clr bit 0x0 Auto_clr 30 Break frame auto clear bit 0 Auto clear TxBRK state end 1 Auto clear disable TxBRK state continue 0x0 Br_frame_clr 29 Stop break frame continuing transfer 0x0 Reserved 28 3 0x0000000 CHID 2 0 Channel ID 0x0 8 7MIPI...

Page 749: ...tate 26 24 Current state 0x0 Reserved 23 19 0x00 FIFO_timeout 18 RxFIFO read timeout 0 In time 1 Time out 0x0 FIFO_full 17 RxFIFO full 0 FIFO not full 1 FIFO full 0x0 FIFO_empty 16 RxFIFO empty 0 FIFO not empty 1 FIFO empty 0x1 Reserved 15 14 0x0 Rx_rd_point 13 8 RxFIFO read point 0x00 Reserved 7 6 0x0 Rx_wr_point 5 0 RxFIFO write point 0x00 State register value 000 IDLE 001 RxACK 010 Rx 011 RxHOL...

Page 750: ...re than 4word 0x10 more than 8word 0x11 more than 16word 0x00 Rx_state time 27 16 Rx state timer setting value 0xFFF RxACK time 15 8 RxACK state timer setting value 0xFF Reserved 7 0x0 RxACK time_en 6 Enable RxACK state timer 0 Disables 1 Enables 0x0 Break_clr 5 RxBREAK state clear bit 0 Disables 1 Enables 0x0 Err_clr 4 Generated Error clear 0x0 Num of CHID 3 2 Number of channel ID 0x0 Burst_mode ...

Page 751: ... ADDRESS 0XECA0_000C INTSRC_REG Bit Description Reset Value Reserved 31 10 0x000000 RxWakeup 9 Received Rx wake up signal set 1 for clearing 0x0 Reserved 8 0x000000 Break_done 7 Received Break frame in Frame mode set 1 to clear 0x0 Added_clock 6 Added clock input set 1 to clear 0x0 Missed_clock 5 Missed clock input interrupt set 1 to clear 0x0 RxACK_timeout 4 RxACK state timeout interrupt set 1 to...

Page 752: ...ake up 0 Enables 1 Disables 0x1 Break_done_msk 7 Break frame done interrupt mask 0 Unmask 1 Mask 0x1 Added_clock_msk 6 Added clock input interrupt mask 0 Unmask 1 Mask 0x1 Missed_clock_msk 5 Missed clock input interrupt mask 0 Unmask 1 Mask 0x1 RxACK_timeout_msk 4 RxACK state timeout interrupt mask 0 Unmask 1 Mask 0x1 Brframe_err_msk 3 Break frame err interrupt mask 0 Unmask 1 Mask 0x1 RxDONE_msk ...

Page 753: ...x00000000 Sw_rst 0 Software reset 0 Set 1 Reset 0x0 8 14 MIPI HSI RX CONTROLLER CHANNEL ID REGISTER CHID_REG R ADDRESS 0XECA0_0018 CHID_REG Bit Description Reset Value Reserved 31 3 0x0000000 CURR_ID 2 0 Current Channel ID 0x0 8 15 MIPI HSI RX CONTROLLER DATA REGISTER FIFO OUTPUT DATA_REG R ADDRESS 0XECA0_ 001C DATA_REG Bit Description Reset Value RxFIFO out 31 0 RxFIFO data output 0x0 ...

Page 754: ...OGRAMMING GUIDE 9 1 BASIC DRAWING FUNCTION 9 1 1 Tx Module Programming Guide Flow Chart Start Put the channel ID Put the Data at FIFO Change Channel ID FIFO empty Y N FIFO full Y Y Wait FIFO not full N N Wait FIFO empty Figure 8 6 14 Basic Tx Module Programming Flow Chart ...

Page 755: ...I INTERFACE CONTROLLER 8 6 25 9 1 2 Rx Module Programming Guide Flow Chart Start Wait interrupt ISR RxDONE FIFO full FIFO time out Read channel ID reg Read Data FIFO Y N Y FIFO empty N Figure 8 6 15 Basic Rx Module Programming Flow Chart ...

Page 756: ...MIPI HSI INTERFACE CONTROLLER S5PC100 USER S MANUAL REV1 0 8 6 26 NOTES ...

Page 757: ...r 3 data lanes Supports pixel format 16bpp 18bpp packed 18bpp loosely packed 3 byte format and 24bpp Interfaces Compatible to Protocol to PHY Interface PPI in MIPI D PHY Specification V0 86 RGB Interface for Video Image Input from display controller I80 Interface for Command mode Image input from display controller PMS control interface for PLL to configure byte clock frequency Prescaler to genera...

Page 758: ...D 5 ch Blender 5 ch Overlay Dither ing VTIME_ RG B _TV VTIME_i 8 0 Local I F 2 c h DMA 2 c h DMA 3 c h TVENC I F RGB I F I 8 0 I F SFRFIL E RG B _VD i 8 0 _VD 2 4 1 8 CTR L 3 2 2 4 2 4 2 4 FIFO I F 8 bit 3 AHB Master I F AHB Slave I F MIPI DSI Master block CLKlane DATlane0 DATlane1 DATlane2 APB I F Figure 8 7 1 MIPI DSI System Block Diagram ...

Page 759: ...ByteClkHS TxRequestHS TxReadyHS TxClkEsc TxRequestEsc TxLpdtEsc Enable UlpsAcitveNot Stopstate Dp Dn TxUlpsEsc TxUlpsExitEsc TxTriggerEsc 3 0 TxValidEsc TxReadyEsc RxClkEsc TxDataHS LP 7 0 RxLpdtEsc RxUlpsEsc RxTriggerEsc 3 0 RxValidEsc RxDataEsc 7 0 ForceTxStopmode Direction TurnRequest ErrEsc ErrSyncEsc ErrControl ErrContentionLP0 ErrContentionLP1 MIPI DSI Protocol Layer D PHY Layer System Bus A...

Page 760: ...t header FIFO for I80 I F sub display Sub display for I80 I F image data Payload FIFO 4byte X 512 depth Payload FIFO for I80 I F sub display image Packet Header FIFO 3byte X 16 depth Packet header FIFO for I80 I F command packet Command for I80 I F command Payload FIFO 4byte X 16 depth Payload FIFO for I80 I F command long packet payload Packet Header FIFO 3byte X 16 depth Packet header FIFO for g...

Page 761: ...w Power Data Receiving RxFIFO is an asynchronous FIFO with ByteClk and PCLK as input clock and output clock respectively Rx data is synchronized to RxClk RXBUF has 4 Rx Byte buffer for aligning from byte to word The packet header of all packets stored in RXFIFO are word aligned i e the first byte of a packet is always stored in LSByte For example if a long packet has 7 byte payload the last byte i...

Page 762: ...C RGB_HSYNC RGB_VDEN BLLP BLLP Vsync start packet Hsync start packet BLLP BLLP BLLP BLLP RGB_DATA DSI_channel BLLP BLLP LP BLLP BLLP BLLP BLLP BLLP BLLP Vsync end packet Hsync end packet DSI_channel Burst mode Non burst mode with Sync event Non burst mode with Sync pulses H S A RGB HFP H B P HBP RGB HFP HBP RGB HFP BLLP Figure 8 7 4 Signal Converting Diagram in Video Mode ...

Page 763: ...s 1 3 2 2 RGB I F Vsync Hsync and VDEN have to be active high signals Vsync and Hsync is pulse type that spends several video clocks RGB_VD 23 0 is R 7 0 G 7 0 B 7 0 All sync signals are synchronized to rising edge of RGB_VCLK Display controller has to send minimum 1 horizontal line length of Vsync pulse V back porch and V front porch Hsync pulse width should be longer than 1 byte clock cycle 1 3 ...

Page 764: ... HBP HBP Hsync start packet Hsync end packet HS A RGB HFP RGB HFP RGB HFP BLLP HBP HBP HBP Figure 8 7 7 Block Timing Diagram of HBP mode HBP Mode Reset DSIM_CONFIG 21 0 Burst mode HBPmode Non burst mode with Sync event HBPmode Non burst mode with Sync pulses HBPmode HS A RGB HFP RGB HFP RGB HFP BLLP HS A RGB HFP RGB HFP RGB HFP BLLP Hsync start packet Hsync end packet Figure 8 7 3 Block Timing Dia...

Page 765: ...A RGB HBP RGB HBP BLLP HFP HFP RGB HBP HFP HS A RGB HBP RGB HBP BLLP HFP HFP RGB HBP HFP Figure 8 7 94 Block Timing Diagram of HFP mode HFP Mode Reset DSIM_CONFIG 22 0 Hsync start packet Hsync end packet Burst mode HFPmode Non burst mode with Sync event HFmode Non burst mode with Sync pulses HFPmode H S A RGB HBP RGB HBP RGB HBP BLLP RGB HBP BLLP H S A RGB HBP RGB HBP Figure 8 7 10 Block Timing Di...

Page 766: ... Sync pulses HSAmode Vsync pulse or Vporch area Vsync start packet Vsync end packet Figure 8 7 11 Block Timing Diagram of HSE Mode HSE Mode Reset DSIM_CONFIG 23 0 Hsync start packet Hsync end packet BLLP BLLP LP BLLP BLLP BLLP BLLP BLLP BLLP DSI_channel Non burst mode with Sync pulses HBPmode H S A RGB HFP H S A BLLP H S A BLLP Non burst mode with Sync pulses HSAmode Vsync pulse or Vporch area Vsy...

Page 767: ...r configures the command allowed area Configuration boundary is 4 h0 4 hF in DSIM_MVPORCH Only this area is allowed command transferring start through HS mode or LPDT In LPDT data transferring spends long time about hundreds of us or more In this time Hsync packet does not come out because of LPDT long packet MIPI DSIM has big size FIFO for this lost Hsync packet After LPDT MIPI DSIM transfers the...

Page 768: ...e signals SYS_CS0 CS1 SYS_WE SYS_VD with its internal clock MIPI DSI master decodes the SYS_ADDR Table 8 7 2 describes I80 I F address map Table 8 7 2 I80 I F Address Map SYS_ADDR 1 0 Description 2 b00 Image data 2 b01 Reserved 2 b10 Payload data 2 b11 Packet Header Figure 8 7 15 shows how MIPI DSI Master packetizes the image data stream via i80 I F in Command mode MIPI DSI master packetizes the f...

Page 769: ...1 P2 P h 1 P h P h 1 P h 2 P 2h 1 P 2h P 2h 1 P 2h 2 P 3h 1 P v 1 h P v 1 h 1 P v 1 h 2 P v h 1 PH DCS long write PF CRC PH DCS long write PH DCS long write PH DCS long write PF CRC PF CRC PF CRC I80 I F Input Command mode output Payload DCS command is write_memory_continue Payload DCS command is write_memory_continue Payload DCS command is write_memory_start Payload DCS command is write_memory_co...

Page 770: ...ISPLAY VS SINGLE DISPLAY 1 5 1 Dual Display MIPI DSI Master supports dual display configuration only in command mode That is both main and sub display image should be transmitted via i80 interface 1 5 2 Single Display Use video mode or command mode for single display configuration 1 6 PLL MIPI DSI Master Block needs very high frequency 80MHz 1GHz clock generated by PLL to transmit Image data MIPI ...

Page 771: ...r data lane 1 XmipiDN 1 dedicated MIPI_DP_2 B DP signal for MIPI DPHY Master data lane 1 XmipiDP 2 dedicated MIPI_DN_2 B DN signal for MIPI DPHY Master data lane 1 XmipiDN 2 dedicated MIPI_TXCP B DP signal for MIPI DPHY Master clock lane XmipiTXCP dedicated MIPI_TXCN B DN signal for MIPI DPHY Master clock lane XmipiTXCN dedicated MIPI _REG_CAP B Regulator capacitor connection Connect a 2nF capacit...

Page 772: ...CB0_0x24 R W Main display Sync Area register 0x0000_0000 DSIM_SDRESOL 0xECB0_0x28 R W Sub display Image resolution register 0x0300_0400 DSIM_INTSRC 0xECB0_0x2C R W Interrupt source register 0x0000_0000 DSIM_INTMSK 0xECB0_0x30 R W Interrupt mask register 0xB337_FFFF DSIM_PKTHDR 0xECB0_0x34 W Packet Header FIFO register 0x0000_0000 DSIM_PAYLOAD 0xECB0_0x38 W Payload FIFO register 0x0000_0000 DSIM_RX...

Page 773: ...R 1 Reserved 15 11 Reserved 0 TxReadyHsClk 10 HS clock ready at Clock lane 0 Not ready for transmitting HS data at clock lane 1 Ready for transmitting HS data at clock lane R 0 UlpsClk 9 ULPS indicator at clock lane 0 No ULPS in clock lane 1 ULSP in clock lane R 1 StopstateClk 8 Stop state indicator at clock lane 0 No Stop state in clock lane 1 Stop state in clock lane R 0 UlpsDat 3 0 7 4 ULPS ind...

Page 774: ...I80 nInitSub nInitMD R W 0 Reserved 15 1 Reserved SwRst 0 Software reset High active Software reset reset all of FF in MIPI DSIM except some SFRs STATUS SWRST CLKCTRL PLLCTRL PLLTMR and PHYTUNE 0 Standby 1 Reset R W 0 3 2 3 Clock Control Register DSIM_CLKCTRL R W Address 0xECB0_0x08 DSIM_CLKCTRL Bit Description R W Reset Value TxRequestHsClk 31 HS clock request for HS transfer at clock lane Turn o...

Page 775: ...lock If bit 1 is 1 b0 and bit 0 is 1 b1 External clock source is used bit clock and ByteClk source Generates ByteClk by dividing 4 in MIPI DSIM clock generation module R W 0 ByteClkEn 24 Byte clock enabler 0 Disables 1 Enables R W 0 LaneEscClkEn 23 19 Escape clock enabler for D phy Lane LaneEscClkEn 0 Clock lane LaneEscClkEn 1 Data lane 0 LaneEscClkEn 2 Data lane 1 LaneEscClkEn 3 Data lane 2 0 Dis...

Page 776: ...PI DSI master such as data lane number input I F porch area frame rate BTA LPDT ULPS etc DSIM_CONFIG Bit Description R W Reset Value Reserved 31 29 Reserved TxTypeSfr 28 Packet Header data in SFR FIFO transmitting type 0 If SFR packet header FIFO is not empty 1 If SFR Payload FIFO is filled over threshold level Transmits Packet Header Set threshold level via DSIM_FIFOTHLD register Base_addr 0x44 R...

Page 777: ...ction to transfer Hsync end packet in Vsync pulse and Vporch area 0 Disables to transfer 1 Enables to transfer In command mode this bit is ignored R W 0 HfpMode 22 HFP disable mode If this bit set DSI master ignores HFP area in Video mode 0 Enables 1 Disables In command mode this bit is ignored R W 0 HbpMode 21 HBP disable mode If this bit set DSI master ignores HBP area in Video mode 0 Enables 1 ...

Page 778: ...mmand mode only 001 8bpp for Command mode only 010 12bpp for Command mode only 011 16bpp for Command mode only 100 16 bit RGB 565 for Video mode only 101 18 bit RGB 666 packed pixel stream for Video mode only 110 18 bit RGB 666 loosely packed pixel stream for common 111 24 bit RGB 888 for Common R W 0 Reserved 7 Reserved NumOfDatLane 6 5 Set the using data lane number 00 Data lane 0 1 data lane 01...

Page 779: ...Set 1 protocol layer request to D PHY and MIPI DSI peripheral will be master after BTA sequence This bit clears automatically at receiving BTA acknowledge from MIPI DSI peripheral R W 0 Reserved 15 8 Reserved CmdLpdt 7 LPDT transfers command in SFR FIFO 0 HS Mode 1 LP Mode R W 0 TxLpdt 6 Data transmission in LP mode all data transfer in LPDT 0 HS Mode 1 LP Mode R W 0 Reserved 5 Reserved TxTriggerR...

Page 780: ...splay Vporch register DSIM_MVPORCH R W Address 0xECB0_0x1C DSIM_MVPORCH Bit Description R W Reset Value CmdAllow 31 28 Number of horizontal lines where command packet transmission is allowed after Stable VFP period See Figure 8 7 R W 0xF Reserved 27 Reserved StableVfp 10 0 26 16 Number of horizontal lines where command packet transmission is not allowed after end of active region See Figure 8 7 In...

Page 781: ...a 9 0 31 22 Vertical Sync Pulse width for Video mode line count In command mode these bits are ignored R W 0 Reserved 21 16 Reserved MianHsa 15 0 15 0 Horizontal Sync Pulse width for Video mode HSA is specified using along blank packet These bits are word counts for blank packet in HSA In command mode these bits are ignored R W 0 3 2 11 Sub display Image resolution register DSIM_SDRESOL R W Addres...

Page 782: ...le image frame NOTE When Hsync is not received during 2 line times internal timer is time out and this bit is flagged R W 0 Reserved 23 22 Reserved LpdrTout 21 LP Rx timeout See the time out register 0x10 R W 0 TaTout 20 Turn around Acknowledge Timeout See the time out register 0x10 R W 0 Reserved 19 Reserved RxDatDone 18 Data receiving complete R W 0 RxTE 17 TE Rx trigger received R W 0 RxAck 16 ...

Page 783: ...formation refer to standard d phy specification R W 0 ErrControl1 3 Control Error lane1 For more information refer to standard d phy specification R W 0 ErrControl0 2 Control Error lane0 For more information refer to standard d phy specification R W 0 ErrContentLP0 1 LP0 Contention Error only lane0 because BTA is only occurred at lane0 For more information refer to standard d phy specification R W...

Page 784: ... 0x10 R W 1 MskTaTout 20 Turn around Acknowledge Timeout See the time out register 0x10 R W 1 Reserved 19 Reserved MskRxDatDone 18 Data receiving complete R W 1 MskRxTE 17 TE Rx trigger received R W 1 MskRxAck 16 ACK Rx trigger received R W 1 MskRxECC 15 ECC multi bit error in LPDR R W 1 MskRxCRC 14 CRC error in LPDR R W 1 Reserved 13 Reserved MskEsc2 12 Escape mode entry error lane2 For more info...

Page 785: ... phy specification R W 1 MskContentLP1 0 LP1 Contention Error For more information refer to standard d phy specification R W 1 3 2 14 Packet Header FIFO register DSIM_PKTHDR W Address 0xECB0_0x34 This register is the FIFO for packet header to send DSI packets DSIM_PKTHDR Bit Description R W Reset Value Reserved 31 24 Reserved PacketHeader 23 0 This register is to write the packet header of Tx pack...

Page 786: ...tion R W Reset Value RxDat 31 0 In Rx mode user can read Rx data through this register Note that the CRC in the packet is not stored in RxFIFO R Unknown 3 2 17 FIFO threshold level register DSIM_FIFOTHLD R W Address 0xECB0_0x40 hidden DSIM_FIFOTHLD Bit Description R W Reset Value Reserved 31 9 Reserved WFullLevelSfr 8 0 Almost full level of SFR payload FIFO R W 0x1FF ...

Page 787: ...yload FIFO full R 0 EmptyLI80 16 I80 payload FIFO empty R 1 FullHSub 15 Sub display packet header FIFO full R 0 EmptyHSub 14 Sub display packet header FIFO empty R 1 FullLSub 13 Sub display payload FIFO full R 0 EmptyLSub 12 Sub display payload FIFO empty R 1 FullHMain 11 Main display packet header FIFO full R 0 EmptyHMain 10 Main display packet header FIFO empty R 1 FullLMain 9 Main display paylo...

Page 788: ...DSIM_PLLCTRL R W Address 0xECB0_0x4C This register configures PLL control D PHY clock range indication etc DSIM_PLLCTRL Bit Description R W Reset Value Reserved 31 28 Should be 0 FreqBand 3 0 27 24 Bitclk frequency band indicator for D PHY global timing R W 0 PllEn 23 Enables PLL R W 0 Reserved 22 20 Should be 0 PMS 19 1 19 1 PLL PMS value R W 0 DpDnSwap 0 Set DpDnSwap signal connected to D PHY mo...

Page 789: ...onsidering stability and VCO range 3 Keep range of Fin_pll from 2 5 MHz to 5 MHz by P code setting Table 8 7 5 PMS and frequency constraint Function Value Description Fin Fin 3 200MHz Pll input frequency Fin_pll Fin_pll 2 5 5 MHz Pfd input frequency VCO_out M Fin P 500 1000 MHz VCO output frequency Fout M Fin P 2 S 16 1000 MHz PLL output frequency P 5 0 P 1 63 PMS 19 14 M 9 0 M 100 1023 PMS 13 4 S...

Page 790: ... Case 1 Case 2 Fin 4MHz 80MHz Fin_pll 4MHz 4MHz P 5 0 1 2 M 9 0 250 250 S 2 0 1 1 VCO_out 1000MHz 1000MHz Fout 1000MHz 1000MHz 4 1 4 Sample for Fout 999 MHz Followings are some example to set PMS value for Fout 999 MHz Case 1 Case 2 Fin 3MHz 81MHz Fin_pll 3MHz 3MHz P 5 0 1 27 M 9 0 333 333 S 2 0 1 1 VCO_out 999MHz 999MHz Fout 999MHz 999MHz ...

Page 791: ...1 0 Supports 1 or 2 data lanes Supports 1 channels Supports RAW8 RAW10 RAW12 Embedded byte based long packet and YUV422 8 bit User defined Byte based Data is not supported Interfaces Compatible to PPI Protocol to PHY Interface in MIPI D PHY Specification Version 0 86 Supports AHB Slave I F Supports ISP Output Supports Memory I F DPSRAM_2048X32 for embedded packet or generic short packet ...

Page 792: ... PHY Slave CLK _GEN LANE _ MERGER DE _ PACKETIZER CSI 2_RX DEMUX _OUT ERR _CONTROL 2 ERR _CONTROL 1 CAMIF Wra pper DPSRA M I F AHB I F Slave DPSRAM 2048 X32 Figure 8 8 1 MIPI CSI System Block Diagram 4 INTERFACE PROTOCOL 0 1 2 3 4 0 Byte_clk HValid DValid Data 31 0 Figure 8 8 2 Waveform of Output Data ...

Page 793: ... illustrated in Figure 8 8 3 Table 8 8 1 specifies the data size constraints for YUV422 8 bit format U1 7 0 Y1 7 0 V1 7 0 Y2 7 0 U3 7 0 Y3 7 0 V3 7 0 Y4 7 0 0 1 2 3 4 5 6 7 Figure 8 8 3 YUV422 Data Storing Order 5 2 RAW8 8 bit RAW data is stored as the sequence illustrated in Figure 8 8 3 Table 8 8 1 specifies the data size constraints for RAW8 format P1 7 0 P2 7 0 P3 7 0 P4 7 0 P5 7 0 P6 7 0 P7 7...

Page 794: ...3 9 2 P4 9 2 P3 1 0 P5 7 0 P6 7 0 P7 7 0 0 1 2 3 4 5 6 7 MSB LSB P4 1 0 P1 1 0 P2 1 0 Figure 8 8 5 RAW10 Data Storing Order 5 4 RAW12 12 bit RAW data is stored as the sequence illustrated in Figure 8 8 5 Table 8 8 1 specifies the data size constraints for RAW12 format P1 11 4 P2 11 4 P2 3 2 P3 11 4 P4 3 0 P5 11 4 P6 11 4 0 1 2 3 4 5 6 7 MSB LSB P4 11 4 P1 9 2 P3 3 0 Figure 8 8 6 RAW12 Data Storing...

Page 795: ...I_DP 4 B DP signal for MIPI DPHY slave data lane 1 XmipiDP 4 Dedicated MIPI_DP 4 B DN signal for MIPI DPHY slave data lane 1 XmipiDN 4 Dedicated MIPI_RXCP B DP signal for MIPI DPHY slave clock lane XmipiRXCP Dedicated MIPI_RXCN B DN signal for MIPI DPHY slave clock lane XmipiRXCN Dedicated NOTES 1 I O direction I input O output B bi direction 2 Type field indicates whether pads are dedicated to th...

Page 796: ...EGISTER CSIS_CONTROL R W ADDRESS 0XECC0_0000 CSIS_CONTROL Bit Description Reset Value DpDnSwap 31 Swapping Dp channel and Dn channel 0 Default 1 Swapping 0 Reserved 30 5 Reserved 0 SwRst 4 Software reset 0 No reset 1 Reset All writable registers in CSI2 go back to reset value After this bit is active for 3 cycles this bit is de asserted automatically Note Almost MIPI CSI2 block uses ByteClk from D...

Page 797: ... Enable 0 7 3 CONFIGURATION REGISTER CSIS_CONFIG R W ADDRESS 0XECC0_0008 CSIS_CONFIG Bit Description Reset Value Reserved 31 2 Reserved 0 NumOfDatLane 1 0 Number of data lane 00 1 Data Lane 01 2 Data Lane 10 11 Reserved 0 7 4 DPHY STATE REGISTER CSIS_DPHYSTS R ADDRESS 0XECC0_000C CSIS_DPHYSTS Bit Description Reset Value Reserved 31 6 Reserved 0 StopStateDat 5 4 Data lane 1 0 is in Stop State 5 Dat...

Page 798: ...Image 0 Disables Interrupt 1 Enables Interrupt 0 MSK_OddAfter 28 Non Image data are received at Odd frame and After Image 0 Disables Interrupt 1 Enables Interrupt 0 Reserved 27 13 Reserved 0 MSK_ERR _SOT_HS 12 Start of transmission error 0 Disables Interrupt 1 Enables Interrupt 0 Reserved 11 9 Reserved 0 MSK_ERR_ESC 8 Escape entry error 0 Disables Interrupt 1 Enables Interrupt 0 Reserved 7 5 Reser...

Page 799: ...ceived at odd frame and before image 0 OddAfter 28 Non image data are received at odd frame and after image 0 Reserved 27 14 Reserved 0 ERR_SOT_HS 13 12 Start of transmission error 0 Reserved 11 10 Reserved 0 ERR_ESC 9 8 Escape entry error 0 Reserved 7 6 Reserved 0 ERR_CTRL 5 4 Control error 0 Reserved 3 Reserved 0 ERR_ECC 2 ECC error 0 ERR_CRC 1 CRC error 0 ERR_ID 0 Unknown ID error Writing 1 cle...

Page 800: ...MIPI CSIS S5PC100 USER S MANUAL REV1 0 8 8 10 NOTES ...

Page 801: ...hile the host and other peripherals continue operation Familiarity with the Universal Serial Bus Specification Revision 1 11 and the OHCI specification2 are necessary to fully understand the material contained in this section Refer to the Universal Serial Bus Specification Revision 1 1 and the Open HCI Open Host controller Specification for USB for details of the interface operation 2 FEATURES S5P...

Page 802: ...ed into two categories Periodic Isochronous and Interrupt and Non periodic Control and Bulk Fields inside of the Endpoint Descriptor ED and Transfer Descriptor TD memory structures define what type of transfer is to take place There are two communication channels between the host controller and the host controller driver The first channel uses a set of registers to control status and list pointers...

Page 803: ...ote host wake from sleep is not absolutely USB 1 1 specification compliant The USB host controller may not be able to feed back resume signaling to downstream devices within 100 microseconds 2 In isochronous transfer mode the latency associated with using VLIO and PC Card memory accesses may violate the 10 µs time limit As a result the USB host controller sends a corrupted CRC an OUT packet or not...

Page 804: ... CONTROL ED TD_DATA 32 ED TD STATUS 32 64x8 FIFO Cntl HC_DATA 8 DF_DATA 8 APP_MDATA 32 HCM_ADR DATA 32 CONTROL STATUS CONTROL CTRL CTRL RH_DATA 8 DF_DATA 8 HCF_DATA 8 Addr 6 FIFO_DATA 8 64x8 FIFO ROOT HUB HOST SIE HSIE S M DPLL ROOT HUB HOST SIE OHCI ROOT HUB REGS PORT S M PORT S M PORT S M X V R USB 1 X V R USB 2 HCI BUS EXT FIFO STATUS RCF0_RegData 32 TxEnl TxDpls TxDmns RcvData RcvDpls RcvDmns ...

Page 805: ...lock 30 Mhz USB 2 0 PHY CONTROL USB 2 0 OTG PHY 48Mhz Clock USB 1 1 Transceiver Serial Interface 2 XuhDP XuhDN External USB Host or Device XusbXTI XusbXTO Crystal or Oscillator clk_sel etc Figure 8 9 3 System Level Block Diagram The S5PC100x USB system shown in Figure 8 9 3 is configured as following 1 USB 1 1 Host 1 Port USB 2 0 OTG 1 Port 2 USB 1 1 Host 2 Ports Note To enable Serial Interface 1 ...

Page 806: ...e interrupt controller An OHCI USB interrupts Generated from the Interrupt Status register All other USB host controller event interrupts Buffer access interrupt Remote wake up interrupt Port resume signal interrupt OHCI initiated interface clear signal interrupt transfer abort USB port power over current exception interrupts ...

Page 807: ...ake up controller of the clock unit If a device is not connected to the USB port the host controller cannot be suspended and the port PAD is not in its low power mode To save power if a device is not connected to the USB port PAD the port power enable can be disabled before the USB clock is stopped Refer to OHCI specification 3 2 PROGRAMMING GUIDES Programming the USB host controller is very simil...

Page 808: ...B PHY 4 1 USB PAD Funtion Signal I O Description Pad Type UHOST_DP Input Output USB DP bi directional I O PAD XuhDP Dedicated UHOST_DN Input Output USB DN bi directional I O PAD XuhDN Dedicated 4 2 USB PHY Funtion Signal I O Description Pad Type USB_DP Input Output Data Plus signal form the USB cable XusbDP Dedicated USB_DM Input Output Data Minus signal form the USB cable XusbDM Dedicated ...

Page 809: ...r UHCHDED 0xED40_0020 USB HcControlHeadED Register UHCCONCURRE D 0xED40_0024 USB HcControlCurrentED Register UHCBHDED 0xED40_0028 USB HcBulkHeadED Register UHCBCURRED 0xED40_002C USB HcBulkCurrentED Register UHCDHD 0xED40_0030 R USB HcDoneHead Register UHCFMI 0xED40_0034 R W USB HcFmInterval Register UHCFMRM 0xED40_0038 R USB HcFmRemaining Register UHCFMNUM 0xED40_003C R USB HcFmNumber Register UH...

Page 810: ...s are shown in Table 8 9 2 Table 8 9 1 UHCREV Bit Definitions UHCREV Bit Description R W Reset Value Rev 31 0 OHCI Specification Revision Number This USB host is compliant to OHCI Revision 1 0a therefore this register reads 0x0000_0010 R 5 2 2 USB HcControl Register UHCCON R W Address 0xED40_0004 The USB Host Control UHCCON shown in Table 8 9 3 register defines the operating modes for the host con...

Page 811: ...interrupts generated by events registered in the UHC Interrupt Status register UHCINTS Refer to Section 20 8 4 If clear all interrupts are routed to the normal host bus interrupt mechanism If set interrupts are routed to the system management interrupt SMI The host controller driver clears this bit on a hardware reset but it does not alter this bit on a software reset The host controller driver us...

Page 812: ...t in the next frame R W CLE 4 ControlListEnable The host controller driver sets this bit to enable the processing of the control list in the next frame If cleared by the host controller driver processing of the control list does not occur after the next SOF UHC must check this bit whenever it determines to process the list If disabled the host controller driver modifies the list If HcControlCurren...

Page 813: ...specifies the service ratio between control and bulk EDs Before processing any of the non periodic lists UHC must compare the ratio specified with its internal count on how many non empty control EDs have been processed in determining whether to continue serving another control ED or switching to bulk EDs The internal count is retained if frame boundary is crossed In case of reset the host control...

Page 814: ...heduling overrun error which occurs if the periodic list does not complete before EOF If a scheduling overrun error is detected the host controller increments the counter and sets the SchedulingOverrun field in the UHC Interrupt Status register UHCINTS These bits are incremented on each scheduling overrun error It is initialized to 0b00 and wraps around at 0b11 This is incremented if a scheduling ...

Page 815: ...st it checks the control list filled CLF bit As long as CLF is 0 UHC does not start processing the Control list If CF is 1 UHC starts processing the control list and sets CLF to 0 If UHC finds a TD on the list then UHC sets CLF to 1 causing the control list processing to continue If no TD is found on the control list and if the host controller driver does not set CLF then it is still 0 if UHC comp...

Page 816: ...USB HOST CONTROLLER S5PC100 USER S MANUAL REV1 0 8 9 16 ...

Page 817: ...The HCD needs to take into this delay into consideration C To clear this bit write 1 b1 to it Table 8 9 4 UHCINTSTAT Bit Definitions UHCINTSTAT Bit Description R W Reset Value Reserved 31 Reserved OC 30 OwnershipChange This bit is set by UHC if the host controller driver sets the OwnershipChangeRequest field in HcCommandStatus However this implementation of the OHCI host does not support SMI There...

Page 818: ...C start of each frame and after the update of HccaFrameNumber UHC also generates a SOF token at the same time 1 A start of a frame or an update of HccaFrameNumber has occurred R WC WDH 1 WritebackDoneHead This bit is set immediately after the UHC has written to the value of the UHCDHead to an external the memory location referred to by the OHCI spec as HccaDoneHead Additional updates of the HccaDo...

Page 819: ... this register is returned To clear a bit in this register write 1 b1 to the Interrupt Disable register UHCINTDISB The register organization and individual bit definitions are shown in Table 8 9 6 All reserved bits are read as unknown values and must be written with only a 0 A question mark indicates the value is unknown at reset Table 8 9 5 UHCINTENB Bit Definitions UHCINTENB Bit Description R W ...

Page 820: ...terrupt generation due to resume detect SF 2 Start of Frame 0 Ignore 1 Enables interrupt generation due to start of frame R WS WDH 1 Writeback HcDoneHead 0 Ignore 1 Enables interrupt generation due to HcDoneHead writeback R WS SO 0 Scheduling Overrun 0 Ignore 1 Enables interrupt generation due to scheduling overrun R WS ...

Page 821: ...Table 8 9 6 UHCINTDISB Bit Definitions UHCINTDIS B Bit Description R W Reset Value MIE 31 Master Interrupt Enable 0 Ignore 1 Disables interrupt generation due to events specified in the other bits of this register This field is set after a hardware or software reset R W OC 30 Ownership Change 0 Ignore 1 Disables interrupt generation due to ownership change R W Reserved 29 7 Reserved RHSC 6 Root Hu...

Page 822: ...0 USER S MANUAL REV1 0 8 9 22 UHCINTDIS B Bit Description R W Reset Value 1 Disables interrupt generation due to HcDoneHead Writeback SO 0 Scheduling Overrun 0 Ignore 1 Disables interrupt generation due to scheduling overrun R W ...

Page 823: ...ion 1 0a Specification R W 7 0 Fixed at 0 R 5 2 8 USB HcPeriodCurrentED Register UHCPDCURRED R Address 0xED40_001C The UHCPDCURRED register contains the exact physical address of the current Isochronous or Interrupt Endpoint Descriptor The register organization and individual bit definitions are shown in Table 8 9 9 The lower 4 bits are read as 0 and are unaffected by writes Table 8 9 8 UHCPDCURRE...

Page 824: ...ue CHED 31 4 ControlHead Endpoint Descriptor The UHC traverses the control list starting with the HcControlHeadED pointer the UHCCHED register the content is loaded from the HCCA during the initialization of the UHC This address pointer is 32 byte aligned therefore the lower 4 bits are always 0 R W 3 0 Fixed at 0 R 5 2 10 USB HcControlCurrentED Register UHCCONCURRED Address 0xED40_0024 The UHCCONC...

Page 825: ...HCON CLE is set the HCD only reads the instantaneous value of this register Initially this is set to zero to indicate the end of the Control list This pointer address is 32 byte aligned therefore the lower 4 bits are always 0 R W 3 0 Fixed at 0 R 5 2 11 USB HcBulkHeadED Register UHCBHDED Address 0xED40_0028 The UHCBHDED register contains the physical address of the first Endpoint Descriptor of the...

Page 826: ...ere it left off in the last frame If it reaches the end of the Bulk list the UHC checks the ControlListFilled bit of HcControl UHCHCON CLF If set the UHC copies the content of the UHC Bulk Head ED register to UHC Bulk Current ED and clears the UHCHCON CLF bit If the UHCHCON CLF bit is not set the UHC does nothing The HCD is only allowed to modify this register if the BulkListEnable bit of the UHC ...

Page 827: ...periodically written to the HCCA This address is 32 byte aligned therefore the lower 4 bits are always 0 R 3 0 Fixed at 0 R 5 2 14 USB HcFmInterval Register UHCFMI R W Address 0xED40_0034 The UHC Frame Interval UHCFMI register contains a 14 bit value that indicates the bit time interval in a frame between two consecutive SOFs and a 15 bit value indicating the full speed maximum packet size that th...

Page 828: ...without causing scheduling overrun The field value is calculated by the HCD R W Reserved 15 14 Reserved FI 13 0 FrameInterval This specifies the interval between two consecutive SOFs in bit times The nominal value is set at 11 999 HCD must store the current value of this field before resetting UHC by setting the HostControllerReset field of HcCommandStatus Refer to Section 20 8 3 as this causes th...

Page 829: ...2 16 USB HcFmNumber Register UHCFMNUM R Address 0xED40_003C The UHC Frame Number UHCFMNUM register is a 16 bit counter which provides a timing reference Table 8 9 16 UHCFMNUM Bit Definitions UHCFMNUM Bit Description R W Reset Value Reserved 31 16 Read as unknown and must be written as zero FN 15 0 Frame Number This 16 bit counter provides a timing reference among events happening in the host contr...

Page 830: ...m the UHC frame interval value A typical value is 0x3E67 If UHC Frame Remaining UHCFMR FR value reaches the value specified in this register processing of the periodic lists has priority over Control Bulk processing The UHC therefore starts processing the interrupt list after completing the current control or bulk transaction that is in progress R W 5 2 18 USB HcLSThreshold Register UHCLSTH R W Ad...

Page 831: ... emulated by the HCD All other fields are located in the Root Hub Descriptor A and Root Hub Descriptor B registers Table 8 9 19 UHCRHDA Bit Definitions UHCRHDA Bit Description R W Reset Value POT PGT 31 24 PowerOnToPowerGoodTime The duration that the HCD must wait before accessing a powered on port in 2 ms units R W Reserved 23 13 Read as unknown and must be written as zero NOCP 12 NoOverCurrentPr...

Page 832: ...HDA NPS is clear If UHCRHDA PSM is set each port is powered individually This mode allows port power to be controlled by either the global switch or per port switching If the Port Power Control Mask bit UHCRHDB PPCM is set the port responds only to port power commands Set ClearPortPower to Set Port Power write 0b1 to UHCRHPS1 2 3 PPS to Clear Port Power write 0b1 to UHCRHPS1 2 3 LDA If the port ma...

Page 833: ... power switch Set Clear Global Power If the device is configured to global switching mode UHCRHDA PSM 0 this field is not valid Bit 17 corresponds to ganged power mask on port 1 and bit 18 corresponds to ganged power mask on port 2 and bit 19 corresponds to ganged power mask on port 3 Bits 31 to 20 and bit 16 are not used bit 16 Unused always reads as 0 bit 17 Ganged power mask on port 1 bit 18 Ga...

Page 834: ... field of this register R WC LPSC 16 read LocalPowerStatusChange write SetGlobalPower wake up The root hub does not support the local power status feature thus this bit is always read as 0 In global power mode UHCRHDA PSM is clear this bit is written to 1 to turn on power to all ports set Goal Port Power In per port power mode this bit sets PortPowerStatus UHCRHPS1 2 3 PPS only on ports whose port...

Page 835: ...PSM is clear this bit is set to turn off power to all ports clear PortPowerStatus In per port power mode it clears PortPowerStatus only on ports whose port power control mask bit is not set Clearing to 0 has no effect R W 5 2 22 USB HcRhPortStatus 1 Register UHCRHPSTAT1 Address 0xED40_0054 The UHC Root Hub Port Status 2 1 registers control and report USB ports 1 and 2 events on a per port basis Th...

Page 836: ...mplete This sequence includes the 20 ms resume pulse LS EOP and 3 ms re synchronization delay The HCD writes a 1 to clear this bit Writing a 0 has no effect This bit is cleared if PortResetStatusChange is set 0 Resume is not complete 1 Resume completed R W PESC 17 PortEnableStatusChange This bit is set if events such as over current condition disconnect switched off power or operational bus error ...

Page 837: ...Set Port Power writing a 1 to this bit UHCRHPS1 2 3 PPS or Set Global Power UHCRHS LPSC HCD clears this bit by writing Clear Port Power writing a 1 to UHCRHPS1 2 3 LSDA or Clear Global Power UHCRHS LPS 0 Port power is off 1 Port power is on The HCD writes a 0b1 to set the PortPowerStatus bit Writing 0b0 has no effect R W Reserved 7 5 Read as unknown and must be written as zero PRS 4 read PortReset...

Page 838: ...opagate to the HC The HCD sets the PortSuspendStatus bit by writing a 1 to this bit Writing a 0 has no effect If CurrentConnectStatus is cleared this write does not set PortSuspendStatus instead it sets ConnectStatusChange This informs the driver that it attempted to suspend a disconnected port 0 Port is not suspended 1 Port is suspended R W PES 1 read PortEnableStatus write SetPortEnable This bit...

Page 839: ... of the downstream port If a device is connected this bit reads as 1 and if no device is connected it is 0 The HCD writes a 1 to this bit to clear the PortEnableStatus bit Writing a 0 has no effect The CurrentConnectStatus is not affected by any write NOTE This bit is always read as 1 if the attached device is non removable This bit reflects the current state of the downstream port 0 No device con...

Page 840: ...the 10 ms port reset signal A 1 indicates that the port reset is complete A 0 indicates that the port reset is not yet complete The HCD writes a 1 to clear this bit Writing a 0 has no effect 0 Port reset is not complete 1 Port reset is complete R W POCIC 19 PortOverCurrentIndicatorChange This bit is valid only if over current conditions are reported on a per port basis This bit is set if root hub ...

Page 841: ...inform the system that the device is attached R W Reserved 15 10 Read as unknown and must be written as zero LSDA 9 read LowSpeedDeviceAttached write ClearPortPower If read this bit indicates the speed of the device attached to this port If set a low speed device is attached to this port If clear a fullspeed device is attached to this port This field is valid only if the CurrentConnectStatus is se...

Page 842: ...t signal The HCD writes a 1 to this bit to initiate a resume Writing a 0 has no effect A resume is initiated only if PortSuspendStatus is set 0 No over current condition 1 Over current condition detected R W PSS 2 read PortSuspendStatus write SetPortSuspend This bit indicates if the port is suspended or in the resume sequence 1 If it is a 0 the port is not suspended or in the resume sequence It is...

Page 843: ...us bit has no effect This bit is also set if not already at the completion of a port reset if reset status change UHCRHPS1 2 3 PRSC is set or port suspend if suspend status change UHCRHPS1 2 3 PSSC is set 0 Port is disabled 1 Port is enabled CCS 0 read CurrentConnectStatus write ClearPortEnable This bit reflects the current state of the downstream port If a device is connected this bit reads as 1 ...

Page 844: ...FEATURE The USB2 0 HS OTG features include the following Complies with the On The Go Supplement to the USB 2 0 Specification Revision 1 0a Operates in High Speed 480 Mbps Full Speed 12 Mbps Device only and Low Speed 1 5 Mbps Host only modes Supports UTMI Level 3 interface Revision 1 0 Supports Session Request Protocol SRP and Host Negotiation Protocol HNP Supports only 32 bit data on the AHB 1 Con...

Page 845: ... Oscillator clk_sel etc Figure 8 10 1 System Level Block Diagram USB HS OTG controller is composed of two independent blocks namely USB 2 0 OTG Link Core and USB 2 0 PHY Control Each has an AHB Slave which provides the microcontroller with read and write access to the Control and Status Registers CSRs The OTG Link has an AHB Master to enable the link to transfer data on the AHB The S5PC100x USB sy...

Page 846: ...ication is not interrupted on packet basis 5 POWER MANAGEMENT UNIT SETTING A register in Power Management Unit has to be set for USB to work appropriately OTHERS 0xE010_8200 OTHERS Bit Description Reset Value USB_SIG_MASK 16 The role of this bit is to bypass or block the signals transferred from USB OTG PHY to internal logic In order to start USB transaction This bit is set to 1 and then USB_PHY i...

Page 847: ... and Host Port registers is accessed in both Host and Device modes If the OTG Link is operating in either Device or Host mode the application must not access registers from the other mode If an illegal access occurs a Mode Mismatch interrupt is generated and reflected in the Core Interrupt register If the core switches from one mode to another the registers in the new mode of operation must be rep...

Page 848: ...d to 0 Periodic Tx Packets Non Periodic Tx Packets Rx Packets DPTXFSIZ _n 31 16 DPTXFSIZ _ n 15 0 NPTXFSIZ 31 16 NPTXFSIZ 15 0 RXFSIZ 31 16 Periodic n Tx Packet one Non Periodic Tx Packets Rx Packets Periodic 1 Tx Packet one DPTXFSIZ _1 31 16 DPTXFSIZ _ 1 15 0 DPTXFSIZ _1 15 0 a Host Mode FIFO Address Mapping b Device Mode FIFO Address mapping FIFO Figure 8 10 3 OTG FIFO Mapping ...

Page 849: ...H TX_NPERIO_DFIFO_DEPTH HPTXFSIZ 31 16 TX_PERIOD_DFIFO_DEPTH In Device Mode RXFSIZ 15 0 OTG_RX_DFIFO_DEPTH NPTXFSIZ 15 0 OTG_RX_DFIFO_DEPTH NPTXFSIZ 31 16 OTG_TX_NPERIO_DFIFO_DEPTH DPTXFSIZ_1 15 0 OTG_RX_DFIFO_DEPTH OTG_TX_NPERIO_DFIFO_DEPTH DPTXFSIZ_1 31 16 OTG_TX_DPERIO_DFIFO_DEPTH_1 DPTXFSIZ_2 15 0 DPTXFSIZE_1 15 0 OTG_TX_DPERIO_DFIFO_DEPTH_1 DPTXFSIZ_2 31 16 OTG_TX_DPERIO_DFIFO_DEPTH2 DPTXFSIZ...

Page 850: ...eld is read and written by the application Read and Write set to 1 b1 by the core on certain USB events Self Set and cleared to 1 b0 by the core Self Clear Read Self set and Write Clear R SS_WC Register field is read by the application Read set to 1 b1 by the core on certain internal or USB or AHB event Self Set and cleared to 1 b0 by the application with a register write of 1 b1 Write Clear A reg...

Page 851: ... or disables external charge pump XusbDRVVBU S Dedicated NOTE 1 USB2 0 HS OTG module can operate in device mode when the voltage on USB_VBUS is valid To be valid in device mode the voltage on USB_VBUS is required to be between 4 75V and 5 25V In host mode OTG makes USB_DRVVBUS low if the voltage on USB_VBUS is lower than the threshold voltage The setting value in OPHYTUNE 16 14 can change the thre...

Page 852: ... W Receive FIFO Size Register 0x0000_1800 GNPTXFSIZ 0xED20_0028 R W Non Periodic Transmit FIFO Size Register 0x1800_1800 GNPTXSTS 0xED20_002C R Non Periodic Transmit FIFO Queue Status Register 0x0008_1800 HPTXFSIZ 0xED20_0100 R W Host Periodic Transmit FIFO Size Register 0x0300_5A00 DPTXFSIZ1 0xED20_0104 R W Device Periodic Transmit FIFO 1 Size Register 0x0300_1000 DPTXFSIZ2 0xED20_0108 R W Device...

Page 853: ...l 0 Interrupt Register 0x0000_0000 HCINTMSK0 0xED20_050C R W Host Channel 0 Interrupt Mask Register 0x0000_0000 HCTSIZ0 0xED20_0510 R W Host Channel 0 Transfer Size Register 0x0000_0000 HCDMA0 0xED20_0514 R W Host Channel 0 DMA Address Register 0x0000_0000 HCCHAR1 0xED20_0520 R W Host Channel 1 Characteristics Register 0x0000_0000 HCSPLT1 0xED20_0524 R W Host Channel 1 Spilt Control Register 0x000...

Page 854: ..._0000 HCSPLT6 0xED20_05C4 R W Host Channel 6 Spilt Control Register 0x0000_0000 HCINT6 0xED20_05C8 R W Host Channel 6 Interrupt Register 0x0000_0000 HCINTMSK6 0xED20_05CC R W Host Channel 6 Interrupt Mask Register 0x0000_0000 HCTSIZ6 0xED20_05D0 R W Host Channel 6 Transfer Size Register 0x0000_0000 HCDMA6 0xED20_05D4 R W Host Channel 6 DMA Address Register 0x0000_0000 HCCHAR7 0xED20_05E0 R W Host ...

Page 855: ...CSPLT12 0xED20_0684 R W Host Channel 12 Spilt Control Register 0x0000_0000 HCINT12 0xED20_0688 R W Host Channel 12 Interrupt Register 0x0000_0000 HCINTMSK12 0xED20_068C R W Host Channel 12 Interrupt Mask Register 0x0000_0000 HCTSIZ12 0xED20_0690 R W Host Channel 12 Transfer Size Register 0x0000_0000 HCDMA12 0xED20_0694 R W Host Channel 12 DMA Address Register 0x0000_0000 HCCHAR13 0xED20_06A0 R W H...

Page 856: ...ime Register 0x0000_05B8 DTKNQR3 0xED20_0830 R Device IN Token Sequence Learning Queue Read Register 3 0x0000_0000 DTKNQR4 0xED20_0834 R Device IN Token Sequence Learning Queue Read Register 4 0x0000_0000 Device Logical IN Endpoint Specific Registers DIEPCTL0 0xED20_0900 R W Device Control IN Endpoint 0 Control Register 0x0000_8000 DIEPINT0 0xED20_0908 R W Device IN Endpoint 0 Interrupt Register 0...

Page 857: ...R W Device IN Endpoint 7 Transfer Size Register 0x0000_0000 DIEPDMA7 0xED20_09F4 R W Device IN Endpoint 7 DMA Address Register 0x0000_0000 DIEPCTL8 0xED20_0A00 R W Device Control IN Endpoint 8 Control Register 0x0000_0000 DIEPINT8 0xED20_0A08 R W Device IN Endpoint 8 Interrupt Register 0x0000_0080 DIEPTSIZ8 0xED20_0A10 R W Device IN Endpoint 8 Transfer Size Register 0x0000_0000 DIEPDMA8 0xED20_0A1...

Page 858: ... W Device OUT Endpoint 0 Interrupt Register 0x0000_0000 DOEPTSIZ0 0xED20_0B10 R W Device OUT Endpoint 0 Transfer Size Register 0x0000_0000 DOEPDMA0 0xED20_0B14 R W Device OUT Endpoint 0 DMA Address Register 0x0000_0000 DOEPCTL1 0xED20_0B20 R W Device Control OUT Endpoint 1 Control Register 0x0000_0000 DOEPINT1 0xED20_0B28 R W Device OUT Endpoint 1 Interrupt Register 0x0000_0000 DOEPTSIZ1 0xED20_0B...

Page 859: ... OUT Endpoint 9 Interrupt Register 0x0000_0000 DOEPTSIZ9 0xED20_0C30 R W Device OUT Endpoint 9 Transfer Size Register 0x0000_0000 DOEPDMA9 0xED20_0C34 R W Device OUT Endpoint 9 DMA Address Register 0x0000_0000 DOEPCTL10 0xED20_0C40 R W Device Control OUT Endpoint 10 Control Register 0x0000_0000 DOEPINT10 0xED20_0C48 R W Device OUT Endpoint 10 Interrupt Register 0x0000_0000 DOEPTSIZ10 0xED20_0C50 R...

Page 860: ...0000 DOEPCTL15 0xED20_0CE0 R W Device Control OUT Endpoint 15 Control Register 0x0000_0000 DOEPINT15 0xED20_0CE8 R W Device OUT Endpoint 15 Interrupt Register 0x0000_0000 DOEPTSIZ15 0xED20_0CF0 R W Device OUT Endpoint 15 Transfer Size Register 0x0000_0000 DOEPDMA15 0xED20_0CF4 R W Device OUT Endpoint 15 DMA Address Register 0x0000_0000 Power and Clock Gating Register PCGCCTL 0xED20_0E00 R W Power ...

Page 861: ...G block power down in PHY2 0 1 b0 OTG block power up 1 b1 OTG block power down If the application does not use OTG functionality set this input high to save power 1 b1 Analog _powerdown 3 Analog block power down in PHY2 0 1 b0 Analog block power up Normal Operation 1 b1 Analog block power down R W 1 b1 Reserved 2 1 2b force_suspend 0 Apply Suspend signal to save power 1 b0 Disables Normal Operatio...

Page 862: ... 1 b0 External crystal 1 b1 External clock Oscillator R W 1 b0 common_on_n 4 Force XO Bias Bandgap and PLL to Remain Powered During a Suspend This bit controls the power down signals of sub blocks in the Common block if the USB 2 0 OTG PHY is suspended 1 b0 48MHz clock on clk48m_ohci is available at all times except in Suspend mode 1 b1 48MHz clock on clk48m_ohci is available at all times even in ...

Page 863: ... ORSTCON R W address 0xED30_0008 ORSTCON Bit Description R W Reset Value Reserved 31 3 29 h0 phylnk_sw_rst 2 OTG Link Core phy_clock domain S W Reset R W 1 b0 link_sw_rst 1 OTG Link Core hclk domain S W Reset R W 1 b0 phy_sw_rst 0 OTG PHY 2 0 S W Reset The phy_sw_rst signal must be asserted for at least 10us R W 1 b1 ...

Page 864: ... 17 Disconnect Threshold Adjustment This bit field adjusts the voltage level for the threshold used to detect a disconnect event at the host 111 6 110 4 5 101 3 100 1 5 011 Design default 010 3 001 4 000 6 R W 3 b011 otgtune 16 14 VBUS Valid Threshold Adjustment This bit field adjusts the voltage level for the VBUS Valid threshold 111 9 110 6 101 3 100 Design default 4 75V 011 3 010 6 001 9 000 12...

Page 865: ...high speed waveform 1 8 0 Design default R W 1 b0 txhsxvtune 5 4 Transmitter High Speed Crossover adjustment This bit field adjusts the voltage at which the DP and DM signals cross while transmitting in HS mode 11 The crossover voltage is increased by 15mV 10 The crossover voltage is increased by 30mV 01 Default setting 00 Reserved R W 2 b01 txvreftune 3 0 HS DC Voltage Level Adjustment This bit f...

Page 866: ...es the Debounce time of a detected connection 1 b0 Long Debounce time used for physical connections 1 b1 Short Debounce time used for soft connections R 1 b0 ConIDSts 16 Connector ID Status Indicates the connector ID status 1 b0 The OTG core is in A device mode 1 b1 The OTG core is in B device mode R 1 b1 Reserved 15 12 4 h0 DevHNPEn 11 Device HNP Enable The application sets the bit if it successf...

Page 867: ... b0 Host negotiation failure 1 b1 Host negotiation success R 1 b0 Reserved 7 2 6 h0 SesReq 1 Session Request The application sets this bit to initiate a session request on the USB The core clears this bit if the HstNegSucStsChng bit is cleared 1 b0 No session request 1 b1 Session request R W 1 b0 SesReqScs 0 Session Request Success The core sets this bit if a session request initiation is successf...

Page 868: ...g 18 A Device Timeout Change The core sets this bit to indicate that the A device has timed out while waiting for the B device to connect R_SS_ WC 1 b0 HstNegDet 17 Host Negotiation Detected The core sets this bit if it detects a host negotiation request on the USB R_SS_ WC 1 b0 Reserved 16 10 7 h0 HstnegSuc StsChng 9 Host Negotiation Success Status Change The core sets this bit on the success or ...

Page 869: ...PTxFEmp interrupt indicates that the Periodic TxFIFO is completely empty R W 1 b0 NPTxFEmp Lvl 7 Non Periodic TxFIFO Empty Level Indicates if the Non Periodic TxFIFO Empty Interrupt bits in the Core Interrupt register GINSTS NPTxFEmp is triggered This bit is used only in Slave mode 1 b0 GINTSTS NPTxFEmp interrupt indicates that the Non Periodic TxFIFO is half empty 1 b1 GINTSTS NPTxFEmp interrupt ...

Page 870: ...HY usually operate on a 48 MHz clock to save power 1 b0 480 MHz Internal PLL clock 1 b1 48 MHz External clock Note This bit must be configured with OPHYPWR pll_powerdown 1 b0 Reserved 14 10 5 h5 HNPCap 9 HNP Capable The application uses this bit to control the OTG cores s HNP capabilities 1 b0 HNP capability is not enabled 1 b1 HNP capability is enabled R W 1 b0 SRPCap 8 SRP Capable The applicatio...

Page 871: ...l transmit FIFOs but cannot flush if the core is in the middle of a transaction The application must only write this bit after checking that the core is neither writing to the TxFIFO nor reading from the TxFIFO The application must wait until the core clears this bit before performing any operations This bit takes 8 clocks to clear R_WS _SC 1 b0 RxFFlsh 4 RxFIFO Flush The application flushes the e...

Page 872: ...ll the CSR registers except the following register bits HCFG FSLSPclkSel DCFG DevSpd All module state machines except the AHB Slave Unit are reset to the IDLE state and all the transmit FIFOs and the receive FIFO are flushed Any transactions on the AHB Master are terminated as soon as possible after gracefully completing the last data phase of an AHB transfer Any transactions on the USB are termin...

Page 873: ...pty Asserted if the Periodic Transmit FIFO is either half or completely empty and there is space for at least one entry to be written in the Periodic Request Queue The half or completely empty status is determined by the Periodic TxFIFO Empty Level bit in the Core AHB Configuration register R 1 b1 HChInt 25 Host Channels Interrupt The core sets this bit to indicate that an interrupt is pending on ...

Page 874: ...ompIP 21 Incomplete Periodic Transfer In Host mode the core sets this interrupt bit if there are incomplete periodic transactions still pending which are scheduled for the current microframe R_SS _WC 1 b0 incompl SOOUT Incomplete Isochronous OUT Transfer The Device mode the core sets this interrupt to indicate that there is at least one isochronous OUT endpoint on which the transfer is not complet...

Page 875: ...ic Frame Interrupt Indicates that the period specified in the Periodic Frame Interval field of the Device Configuration register DCFG PerFrInt has been reached in the current microframe R_SS _WC 1 b0 ISOutDrop 14 Isochronous OUT Packet Dropped Interrupt The core sets this bit if it fails to write an isochronous OUT packet into the RxFIFO because the RxFIFO does not have enough space to accommodate...

Page 876: ...one entry to be written to the Non Periodic Transmit Request Queue The half or completely empty status is determined by the Non Periodic TxFIFO Empty Level bit in the Core AHB Configuration register GAHBCFG NPTxFEmpLvl R 1 b1 RxFLvl 4 RxFIFO Non Empty Indicates that there is at least one packet pending to be read from the RxFIFO R 1 b0 Sof 3 Start of micro Frame In Host mode the core sets this bit...

Page 877: ...SB2 0 HS OTG S5PC100 USER S MANUAL REV1 0 8 10 34 GINTSTS Bit Description R W Reset Value CurMod 0 Current Mode Of Operation Indicates the current mode of operation 1 b0 Device mode 1 b1 Host mode R 1 b0 ...

Page 878: ...tIntMsk 24 Host Port Interrupt Mask R W 1 b0 Reserved 23 1 b0 FetSuspMsk 22 Data Fetch Suspended Mask R W 1 b0 Incomplete Periodic Transfer Mask R W incomplPMsk incompISOOUTMsk 21 Incomplete Isochronous OUT Transfer Mask 1 b0 incompISOINMsk 20 Incomplete Isochronous IN Transfer Mask R W 1 b0 OEPIntMsk 19 OUT Endpoints Interrupt Mask R W 1 b0 INEPIntMsk 18 IN Endpoints Interrupt Mask R W 1 b0 EPMis...

Page 879: ...USB2 0 HS OTG S5PC100 USER S MANUAL REV1 0 8 10 36 GINTMSK Bit Description R W Reset Value OTGIntMsk 2 OTG Interrupt Mask R W 1 b0 ModeMisMsk 1 Mode Mismatch Interrupt Mask R W 1 b0 Reserved 0 1 b0 ...

Page 880: ...mpty bit of the Core Interrupt register GINTSTS RxFLvl is asserted 8 2 13 Host Mode Receive Status Debug Read Status Read and Pop Registers GRXSTSR GRXSTSP R Address 0xED20_001C 0xED20_0020 GRXSTSR GRXSTSP Bit Description R W Reset Value Reserved 31 21 PktSts 20 17 Packet Status Indicates the status of the received packet 4 b0010 IN data packet received 4 b0011 IN transfer completed triggers an in...

Page 881: ...hF PktSts 20 17 Packet Status Indicates the status of the received packet 4 b0001 Global OUT NAK triggers an interrupt 4 b0010 OUT data packet received 4 b0011 OUT transfer completed triggers an interrupt 4 b0100 SETUP transaction completed triggers an interrupt 4 b0110 SETUP data packet received others Reserved R 4 b1111 DPID 16 15 Data PID Indicates the Data PID of the received OUT data packet 2...

Page 882: ... 0xED20_0028 The application programs the RAM size and the memory start address for the Non Periodic TxFIFO GNPTXFSIZ Bit Description R W Reset Value NPTxFDep 31 16 Non Periodic TxFIFO Depth This value is in terms of 32 bit words Minimum value is 16 Maximum value is 32768 The power on reset value of this register is specified as the Largest Non Periodic Tx Data FIFO Depth 6144 A new value must be ...

Page 883: ...annel halt command Bit 24 Terminate last entry for selected channel endpoint R 7 h0 NPTxQSpcAvail 23 16 Non Periodic Transmit Request Queue Space Available Indicates the amount of free space available in the Non Periodic Transmit Request Queue This queue holds both IN and OUT requests in Host mode Device mode has only IN requests 8 h0 Non Periodic Transmit Request Queue is full 8 h1 1 location ava...

Page 884: ... of 32 bit words Minimum value is 16 Maximum value is 6144 A new value must be written to this field Programmed values must not exceed the Maximum value R W 16 h0300 PTxFStAddr 15 0 Host Periodic TxFIFO Start Address The power on reset value of this register is sum of the Largest Rx Data FIFO Depth and Largest Non Periodic Tx Data FIFO Depth specified If you have programmed new values for the RxFI...

Page 885: ... 16 h300 n 2 16 h300 n 3 16 h300 n 4 16 h300 n 5 16 h300 n 6 16 h300 n 7 16 h300 n 8 16 h300 n 9 16 h300 n 10 16 h300 n 11 16 h300 n 12 16 h300 n 13 16 h300 n 14 16 h300 n 15 16 h300 DPTxFStAddr 15 0 Device Periodic TxFIFO RAM Start Address Holds the start address in the RAM for this periodic FIFO The power on reset value of this register is sum of the Largest Rx Data FIFO Depth Largest Non Period...

Page 886: ...scription R W Reset Value Reserved 31 3 29 h0040000 FSLSSupp 2 FS and LS Only Support The application uses this bit to control the core s enumeration speed Using this bit the application makes the core enumerate as a FS host even if the connected device supports HS traffic Do not make changes to this field after initial programming 1 b0 HS FS LS based on the maximum speed supported by the connecte...

Page 887: ...o value is programmed the core calculates the value based on the PHY clock specified in the FS LS PHY Clock Select field of the Host Configuration register HCFG FSLSPclkSel Do not change the value of this field after the initial configuration 125 μs PHY clock frequency for HS 1 ms PHY clock frequency for FS LS R W 16 h17D7 8 2 22 Host Frame Number Frame Time Remaining Register HFNUM R Address 0xED...

Page 888: ...int number Bits 26 25 Type 2 b00 IN OUT 2 b01 Zero length packet 2 b10 CSPLIT 2 b11 Disable channel command Bit 24 Terminate R 8 h0 PTxQSpcAvai l 23 16 Periodic Transmit Request Queue Space Available Indicates the number of free locations available to be written in the Periodic Transmit Request Queue This queue holds both IN and OUT requests 8 h0 Periodic Transmit Request Queue is full 8 h1 1 loca...

Page 889: ...rupt register HAINT Bit Description R W Reset Value Reserved 31 16 16 h0 HAINT 15 0 Channel Interrupts One bit per channel Bit 0 for Channel 0 bit 15 for Channel 15 R 16 h0 8 2 25 Host All Channels Interrupt Mask Register HAINTMSK R W Address 0xED20_0418 The Host All Channel Interrupt Mask register works with the Host All Channel Interrupt register to interrupt the application if an event occurs o...

Page 890: ...he interrupt HPRT Bit Description R W Reset Value Reserved 31 19 13 h0 PrtSpd 18 17 Port Speed Indicates the speed of the device attached to this port 2 b00 High speed 2 b01 Full speed 2 b10 Low speed 2 b11 Reserved R 2 b0 PrtTstCtl 16 13 Port Test Control The application writes a nonzero value to this field to put the port into a Test mode and the corresponding pattern is signaled on the port 4 b...

Page 891: ...re after a remote wakeup signal is detected or the application sets the Port Reset bit or Port Resume bit in this register or the Resume Remote Wakeup Detected Interrupt bit or Disconnect Detected Interrupt bit in the Core Interrupt register 1 b0 Port not in Suspend mode 1 b1 Port in Suspend mode R_WS _SC 1 b0 PrtRes 6 Port Resume The application sets this bit to drive resume signaling on the port...

Page 892: ... bit The application cannot set this bit by a register write It clears it to disable the port This bit does not trigger any interrupt to the application 1 b0 Port disabled 1 b1 Port enabled R_SS_ SC_ WC 1 b0 PrtConn Det 1 Port Connect Detected The core sets this bit if a device connection is detected to trigger an interrupt to the application using the Host Port Interrupt bit of the Core Interrupt...

Page 893: ...ons 1 b0 Even micro frame 1 b1 Odd micro frame R W 1 b0 DevAddr 28 22 Device Address This field selects the specific device serving as the data source or sink R W 7 h0 MC EC 21 20 Multi Count Error Count If the Split Enable bit of the Host Channel n Split Control register is reset 1 b0 this field indicates to the host the number of transactions that must be executed per microframe for this endpoin...

Page 894: ...rved 16 1 b0 EPDir 15 Endpoint Direction Endpoint Type Indicates the transfer type selected 1 b0 OUT 1 b1 IN R W 1 b0 EPNum 14 11 Endpoint Number Indicates the endpoint number on the device serving as the data source or sink R W 4 h0 MPS 10 0 Maximum Packet Size Indicates the maximum packet size of the associated endpoint R W 11 h0 ...

Page 895: ...m a complete split transaction R W 1 b0 XactPos 15 14 Transaction Position This field is used to determine whether to send all first middle or last payloads with each OUT transaction 2 b11 All This is the entire data payload is of this transaction 2 b10 Begin This is the first data payload of this transaction 2 b00 Mid This is the middle payload of this transaction 2 b01 End This is the last paylo...

Page 896: ...n R W Reset Value Reserved 31 11 21 h0 DataTglErr 10 Data Toggle Error R_SS_WC 1 b0 FrmOvrun 9 Frame Overrun R_SS_WC 1 b0 BblErr 8 Babble Error R_SS_WC 1 b0 XactErr 7 Transaction Error R_SS_WC 1 b0 NYET 6 NYET Response Received Interrupt R_SS_WC 1 b0 ACK 5 ACK Response Received Interrupt R_SS_WC 1 b0 NAK 4 NAK Response Received Interrupt R_SS_WC 1 b0 STALL 3 STALL Response Received Interrupt R_SS_...

Page 897: ...ed 31 11 21 h0 DataTglErrMsk 10 Data Toggle Error Mask R W 1 b0 FrmOvrunMsk 9 Frame Overrun Mask R W 1 b0 BblErrMsk 8 Babble Error Mask R W 1 b0 XactErrMsk 7 Transaction Error Mask R W 1 b0 NyetMsk 6 NYET Response Received Interrupt Mask R W 1 b0 AckMsk 5 ACK Response Received Interrupt Mask R W 1 b0 NakMsk 4 NAK Response Received Interrupt Mask R W 1 b0 StallMsk 3 STALL Response Received Interrup...

Page 898: ...o the application is interrupted to indicate normal completion R W 10 b0 XferSize 18 0 Transfer Size For an OUT this field is the number of data bytes the host sends during the transfer For an IN this field is the buffer size that the application has reserved for the transfer The application is expected to program this field as an integer multiple of the maximum packet size for IN transactions R W...

Page 899: ...ever there is a match or if the counter expires The width of this counter depends on the depth of the Token Queue R W 5 h8 Reserved 17 13 5 h0 PerFrInt 12 11 Periodic Frame Interval Indicates the time within a micro frame at which the application must be notified using the End Of Periodic Frame Interrupt This can be used to determine if all the isochronous traffic for that micro frame is complete ...

Page 900: ... However the actual bus speed is determined only after the chirp sequence is complete and is based on the speed of the USB host to which the core is connected 2 b00 High speed USB 2 0 PHY clock is 30 MHz or 60 MHz 2 b01 Full speed USB 2 0 PHY clock is 30 MHz or 60 MHz 2 b10 Low speed USB 1 1 transceiver clock is 6 MHz If you select 6 MHz LS mode you must do a soft reset 2 b11 Full speed USB 1 1 tr...

Page 901: ...to this field clears the Global Non Periodic IN NAK W 1 b0 SGNPInNAK 7 Set Global Non Periodic IN NAK A write to this field sets the Global Non Periodic IN NAK The application uses this bit to send a NAK handshake on all non periodic IN endpoints The core sets this bit if a timeout condition is detected on a non periodic endpoint The application must set this bit only after making sure that the Gl...

Page 902: ... restarts device enumeration 1 b1 The core drives the opmode signal on the UTMI to 2 b01 which generates a device disconnect event to the USB host R W 1 b0 RmtWkUpSig 0 Remote Wakeup Signaling If the application sets this bit the core initiates remote signaling to wake up the USB host The application must set this bit to instruct the core to exit the Suspend state As specified in the USB 2 0 speci...

Page 903: ... the application with Early Suspend bit of the Core Interrupt register If the early suspend is asserted due to an erratic error the application performs a soft disconnect recover R 1 b0 EnumSpd 2 1 Enumerated Speed Indicates the speed at which the OTG core has come up after speed detection through a chirp sequence 2 b00 High speed PHY clock is 30 MHz or 60 MHz 2 b01 Full speed PHY clock is 30 MHz ...

Page 904: ... Disabled Interrupt Mask R W 1 b0 XferComplMsk 0 Transfer Completed Interrupt Mask R W 1 b0 8 2 37 Device OUT Endpoint Common Interrupt Mask Register DOEPMSK R W Address 0xED20_0814 This register works with each of the Device OUT Endpoint Interrupt registers for all endpoints to generate an interrupt per OUT endpoint The OUT endpoint interrupts for a specific status in the DOEPINTn register is mas...

Page 905: ...eset Value OutEPInt 31 16 OUT Endpoint Interrupt Bits One bit per OUT endpoint Bit 16 for OUT endpoint 0 bit 31 for OUT endpoint 15 R 16 h0 InEpInt 15 0 IN Endpoint Interrupt Bits One bit per IN endpoint Bit 0 for IN endpoint 0 bit 15 for endpoint 15 R 16 h0 8 2 39 Device ALL Endpoints Interrupt Mask Register DAINTMSK R W Address 0xED20_081C The Device Endpoint Interrupt Mask register works with t...

Page 906: ... 27 24 Endpoint number of Token 4 Bits 15 12 Endpoint number of Token 1 Bits 11 8 Endpoint number of Token 0 R 24 h0 WrapBit 7 Wrap Bit This bit is set if the write pointer wraps It is cleared if the learning queue is cleared R 1 b0 Reserved 6 5 R 2 h0 INTKnWPtr 4 0 IN Token QUEUE Write Pointer R 5 h0 8 2 41 Device IN Token Sequence Learning Queue Read Register 2 DTKNQR2 R Address 0xED20_0824 Read...

Page 907: ...4 R Address 0xED20_0834 Read from this register returns the next 8 endpoint entries of the learning queue DTKNQR4 Bit Description R W Reset Value EPTkn 31 0 Endpoint Token Four bits per token represent the endpoint number of the token Bits 31 28 Endpoint number of Token 29 Bits 27 24 Endpoint number of Token 28 Bits 7 4 Endpoint number of Token 23 Bits 3 0 Endpoint number of Token 22 R 32 h0 8 2 4...

Page 908: ...LSE R W Address 0xED20_082C This register specifies the VBUS discharge time during SRP DVBUSPULSE Bit Description R W Reset Value Reserved 31 12 16 h0 DVBUSPulse 11 0 Device VBUS Pulsing Time Specifies the VBUS pulsing time during SRP This value equals VBUS pulse time in PHY clocks 1 024 R W 12 h5B8 ...

Page 909: ...ransmitting data on an endpoint even before the transfer for that endpoint is complete The application must wait for the Endpoint Disabled interrupt before treating the endpoint as disabled The core clears this bit before setting the Endpoint Disabled Interrupt The application must set this bit only if Endpoint Enable is already set for this endpoint R_WS_ SC 1 b0 Reserved 29 28 2 b0 SetNAK 27 Set...

Page 910: ...0 Reserved 16 1 b0 USBActEP 15 USB Active Endpoint This bit is always set to 1 indicating that control endpoint 0 is always active in all configurations and interfaces R 1 b1 NextEp 14 11 Next Endpoint Applies to non periodic IN endpoints only Indicates the endpoint number to be fetched after the data for the current endpoint is fetched The core accesses this field even if the Endpoint Enable bit ...

Page 911: ...d 29 28 2 b0 SetNAK 27 Set NAK A write to this bit sets the NAK bit for the endpoint Using this bit the application controls the transmission of NAK handshakes on an endpoint The core sets this bit on a Transfer Completed interrupt or after a SETUP is received on the endpoint W 1 b0 CNAK 26 Clear NAK A write to this bit clears the NAK bit for the endpoint W 1 b0 Reserved 25 22 4 h0 Stall 21 STALL ...

Page 912: ...pace in the RxFIFO to accommodate the incoming packet Irrespective of this bit s setting the core always responds to SETUP data packets with an ACK handshake R 1 b0 Reserved 16 1 b0 USBActEP 15 USB Active Endpoint This bit is always set to 1 indicating that a control endpoint 0 is always active in all configurations and interfaces R 1 b1 Reserved 14 2 13 h0 MPS 1 0 Maximum Packet Size The maximum ...

Page 913: ...t even before the transfer for that endpoint is complete The application must wait for the Endpoint Disabled interrupt before treating the endpoint as disabled The core clears this bit before setting the Endpoint Disabled Interrupt The application must set this bit only if Endpoint Enable is already set for this endpoint R_WS _SC 1 b0 SetD1PID 29 Set DATA1 PID Applies to interrupt bulk IN and OUT ...

Page 914: ...he STALL bit takes priority Only the application clears this bit never the core R W 1 b0 Applies to control endpoints only The application sets this bit and the core clears it if a SETUP token is received for this endpoint If a NAK bit Global Non Periodic IN NAK or Global OUT NAK is set along with this bit the STALL bit takes priority Irrespective of this bit s setting the core always responds to ...

Page 915: ...lies to isochronous IN and OUT endpoints only Indicates the micro frame number in which the core transmits receives isochronous data for this endpoint The application must program the even odd micro frame number in which it intends to transmit receive isochronous data for this endpoint using the SetEvnFr and SetOddFr fields in this register 1 b0 Even micro frame 1 b1 Odd micro frame USBActEP 15 US...

Page 916: ...ecessarily mean that a NAK handshake is sent on the USB A STALL bit takes priority over a NAK bit R 1 b0 Back2Back SETup Back to Back SETUP Packets Received Applies to Control OUT endpoints only This bit indicates that core has received more than three back to back SETUP packets for this particular endpoint R W INTknEPMis 5 IN Token Received with EP Mismatch Applies to periodic IN endpoints only I...

Page 917: ... AHB Error Applies to IN and OUT endpoints This is generated only in Internal DMA mode if there is an AHB error during an AHB read write The application reads the corresponding endpoint DMA address register to get the error address R_SS _WC 1 b0 EPDisbld 1 Endpoint Disabled Interrupt Applies to IN and OUT endpoints This bit indicates that the endpoint is disabled per the application s request R_SS...

Page 918: ...t Value Reserved 31 21 11 h0 PktCnt 20 19 Packet Count Indicates the total number of USB packets that constitute the Transfer Size amount of data for endpoint 0 This field is decremented every time a packet is read from the TxFIFO R W 2 b0 Reserved 18 7 12 h0 XferSize 6 0 Transfer Size Indicates the transfer size in bytes for endpoint 0 The core interrupts the application only after it has exhaust...

Page 919: ...ts R W 2 h0 Reserved 28 20 9 h0 PktCnt 19 Packet Count This field is decremented to zero after a packet is written into the RxFIFO R W 1 b0 Reserved 18 7 12 h0 XferSize 6 0 Transfer Size Indicates the transfer size in bytes for endpoint 0 The core interrupts the application only after it has exhausted the transfer size amount of data The transfer size can be set to the maximum packet size of the e...

Page 920: ...dpoints 2 b01 1 packet 2 b10 2 packets 2 b11 3 packets R W For non periodic IN endpoints this field is valid only in Internal DMA mode It specifies the number of packets the core must fetch for an IN endpoint before it switches to the endpoint pointed to by the Next Endpoint field of the Device Endpoint n Control register R Received Data PID Applies to isochronous OUT endpoints only This is the da...

Page 921: ...nd written to the external memory R W 19 h0 NOTE Transfer Size for a Device Endpoint must equal Packet Count Max Packet Size for accurate data transfer 8 2 54 Device Endpoint N DMA Address DIEPDMAn DOEPDMAn R W Address 0xED20_0914 n 20h 0xED20_0B14 n 20h Endpoint_number 0 n 15 The starting DMA address must be DWORD aligned DIEPDMAn DOEPDMAn Bit Description R W Reset Value DMAAddr 31 0 DMA Address ...

Page 922: ...ses this register to control OTG s clock gating DIEPTSIZ0 Bit Description R W Reset Value Reserved 31 1 31 h0 StopPclk 0 STOP Pclk The application sets this bit to stop the PHY clock if the USB is suspended the session is not valid or the device is disconnected The application clears this bit if the USB is resumed or a new session starts R W 1 b0 ...

Page 923: ...RAM buffer is 16 KB For the buffer status and Interrupt Requests this specification also specifies a few pre defined special addresses The Modem chip writes data in the data buffer and writes interrupt control data to the interrupt port address for the interrupt request to the AP The AP reads that data if an interrupt request is accepted and the interrupt is cleared if AP accesses the interrupt po...

Page 924: ...le interface Supports both Standard mode and Address Muxed mode Supports 16 bit parallel bus for data transfer Supports 16 KB internal dual port SRAM buffer Supports Interrupt request for data exchange Programmable interrupt port address Supports DMA for data transfer without intervention of CPU ...

Page 925: ... ADR For example 0x3FFC at AHB bus is 0x1FFE at ADR Figure 8 11 2 helps you to understand it This is default value It can be set to other value by the SFR INT2AP and INT2MSM 2 Modem interface block has one Interrupt Clear Registers MSMINTCLR Level type interrupt request is generated by modem interface block and is sustained until the AP clears the interrupt clear registers by writing any value to ...

Page 926: ...MODEM INTERFACE S5PC100 USER S MANUAL REV1 0 8 11 4 4 ADDRESS MAPPING Figure 8 11 2 MODEM I F Address Mapping ...

Page 927: ... Figure 8 11 3 Modem Interface Write Timing Diagram Standard Mode Table 8 11 2 Modem Interface Write Timing Standard mode Parameter Description Min ns Max ns Notes tAVWR Address Valid to Address Invalid 16 ns tCSVWR Chip Select Active 16 ns tAWR Address Valid to Write Active 4 ns tWR Write Active 8 ns tDSUWR Write Data Setup 8 ns tDHWR Write Data Hold 4 ns ...

Page 928: ...ead timing Standard Mode Parameter Description Min ns Max ns Notes tAVRD Address Valid to Address Invalid 50 ns tADH Address Hold 0 ns tCSVRD Chip Select Active 50 ns tCSRD Chip Select Active to Read Active 14 ns tRD Read Active 36 ns tRDDV Read Active to Data Valid 35 ns tRDH Read Data Hold 6 ns tACSDV Address and Chip Select Active to Data Valid 49 ns NOTE Output load is 30pF at room temperature...

Page 929: ...ode Table 8 11 4 Modem Interface Write Timing Address Muxed Mode Parameter Description Min ns Max ns Notes tAVDS Address Valid Setup 15 ns tAVDH Address Valid Hold 5 ns tAV Address Valid duration 15 ns tAVWR Address Valid to Write Enable 0 ns tCSV Chip Select duration 20 ns tWR Write Enable duration 5 ns tDSWR Write Data Setup 8 ns tDHWR Write Data Hold 4 ns ...

Page 930: ...ad timing Address Muxed Mode Parameter Description Min ns Max ns Notes tAVDS Address Valid Setup 15 ns tAVDH Address Valid Hold 5 ns tAV Address Valid duration 15 ns tAVOE Address Valid to Read Enable 5 ns tCSVOE Chip Select duration Read mode 45 ns tOE Output Enable Read Active to Data Valid 35 ns NOTE Output load is 30pF at room temperature 25 Degree ...

Page 931: ...st to MODEM Chip XmsmIRQn muxed ADVn Input Address Valid from MODEM Chip Only Address Muxed mode XmsmADDR 4 muxed NOTE Type field indicates whether pads are dedicated to the signal or pads are connected to the multiplexed signals 7 SOFTWARE INTERFACE AND REGISTERS This modem interface provides a generic data exchange method This interface does not implement any other complex features except for th...

Page 932: ...W DMA RX Request Address Register 0x1FFE_1BFE 8 1 INTERRUPT REQUEST TO AP REGISTER INT2AP R W ADDRESS 0XED50_8000 INT2AP Bit Description Reset Value Reserved 31 14 Reserved 0 INT2AP_ADR 13 0 Modem interface requests the interrupt to AP if modem chip writes this address This interrupt is cleared by the interrupt controller of AP and write access to the MSMINTCLR register 0x3FFE 8 2 INTERRUPT REQUES...

Page 933: ... Reserved 15 4 Reserved 0 INT2MSMEN 3 Enables Interrupt to MSM Modem MSM_nIRQ is interrupt signal enable 0 Disable 1 Enable 1 INT2APEN 2 Enables MSM Modem write interrupt to AP 0 Disable 1 Enable 0 Reserved 1 Reserved 0 Fixed 0 Fixed to 0 0 8 4 MODEM INTERFACE PORT CONTROL REGISTER MIFPCON R W ADDRESS 0XED50_800C MIFCON Bit Description Reset Value Reserved 31 7 Reserved 0 ADM_MODE 6 Address Muxed ...

Page 934: ... ADDRESS 0XED50_8014 INT2AP Bit Description Reset Value Reserved 31 30 Reserved 0 DMA_TX_ADR_1 29 16 Modem interface requests the DMA to AP DMA Controller if modem chip reads this address Source DMA_MSM_Req 1 0x17FE Reserved 15 14 Reserved 0 DMA_TX_ADR_0 13 0 Modem interface requests the DMA to AP DMA Controller if modem chip reads this address Source DMA_MSM_Req 0 0x13FE 8 7 DMA REQUEST RX ADDRES...

Page 935: ...S5PC100 USER S MANUAL REV1 0 MODEM INTERFACE 8 11 13 NOTES ...

Page 936: ...ecification You can interface your system with SD card and MMC card The performance of this host is very powerful as clock rate is 48 MHz and access 8 bit data pin simultaneously 2 FEATURES The High Speed MMC controller supports SD Standard Host Specification Version 2 0 standard SD Memory Card Specification Version 2 0 High Speed MMC Specification Version 4 2 standard SDIO Card Specification Vers...

Page 937: ... SFR SDCLK Domain HCLK Domain System Bus AHB CMD ARG Control Status AHB slave I F DMA controller AHB master FIFO DATA packet Status Control CMDRSP packet Status Control RSP Line Control Pad I F INTREQ BaseCLK Clock Control DPSRAM Control Figure 8 12 1 HSMMC Block Diagram ...

Page 938: ...d Insertion Status Enable ENSTACARDNS in the Normal Interrupt Status Enable register Card Insertion Signal Enable ENSIGCARDNS in the Normal Interrupt Signal Enable register Card Removal Status Enable ENSTACARDREM in the Normal Interrupt Status Enable register Card Removal Signal Enable ENSIGCARDREM in the Normal Interrupt Signal Enable register 2 If Host Driver detects the card insertion or remova...

Page 939: ...wn in Figure 8 12 3 are explained below 1 Calculate a divisor to determine SD Clock frequency for SD Clock by reading Base Clock Frequency Refer to clock control register 2 Set Internal Clock Enable ENINTCLK and SDCLK Frequency Select in the Clock Control register in accordance with the calculated result of step 1 3 Check Internal Clock Stable STBLINTCLK in the Clock Control register Repeat this s...

Page 940: ...and Inhibit CMD in the Present State register is set to 1 1 Set SD Clock Enable ENSDCLK in the Clock Control register to 0 After ENSDCLK is set the Host Controller stops SD Clock 4 4 SD CLOCK FREQUENCY CHANGE SEQUENCE Figure 8 12 5 SD Clock Change Sequence The sequence for changing SD Clock frequency is shown in Figure 8 12 5 If SD Clock is still off skip step 1 The steps shown in Figure 8 12 5 ar...

Page 941: ...ternal power regulator optional with maximum voltage that the Host Controller supports 3 Set SD Bus Power PWRON in the Power Control register to 1 4 Get the OCR value of all function internal of SD card 5 Judge whether SD Bus voltage must be changed or not If SD Bus voltage must be changed continue with step 6 If SD Bus voltage is not to be changed go to End 6 Set SD Bus Power in the Power Control...

Page 942: ...e of other card go to step 3 3 Set IENM of the CCCR in a SDIO or SD combo card to 0 by CMD52 4 Change the bit mode for a SD card Set Bus Width of Bus Interface Control register in CCCR to change SD memory card bus width by ACMD6 Set bus width and SDIO card bus width 5 If you want to change to 4 bit mode set Data Transfer Width WIDE4 to 1 in the Host Control register In another case 1 bit mode set ...

Page 943: ...e sequence to generate and control various kinds of SD transactions SD transactions are classified into three cases 1 Transactions that do not use the DAT line 2 Transactions that use the DAT line for the busy signal 3 Transactions that use the DAT line for transferring data In this specification the first and the second case s transactions are classified as Transaction Control without Data Transf...

Page 944: ...S5PC100 USER S MANUAL REV1 0 SD MMC CONTROLLER 8 12 9 4 9 SD COMMAND ISSUE SEQUENCE Figure 8 12 9 Timeout Setting Sequence ...

Page 945: ... Interrupt If the Command Complete Interrupt occurs go to step 2 2 Write 1 to Command Complete STACMDCMPLT in the Normal Interrupt Status register to clear this bit 3 Read the Response register and get necessary information in accordance with the issued command 4 Judge whether the command uses the Transfer Complete Interrupt or not If it uses Transfer Complete proceed with step 5 If not go to step...

Page 946: ...ommand Complete Status Get Response Data Command with Transfer Complete Int Wait for Transfer Complete Int Clear Transfer Complete Status Transfer Complete Int occur Check Response Data no No error Return Status No Error Return Status Response Contents Error Error END 1 2 3 4 5 6 7 8 9 Figure 8 12 10 Command Complete Sequence ...

Page 947: ...of classification are as follows 1 Single Block Transfer The number of blocks is specified to the Host Controller before the transfer The number of blocks specified is always one 2 Multiple Block Transfer The number of blocks is specified to the Host Controller before the transfer The number of blocks specified is one or more 3 Infinite Block Transfer The number of blocks is not specified to the H...

Page 948: ...S5PC100 USER S MANUAL REV1 0 SD MMC CONTROLLER 8 12 13 4 12 NOT USING DMA Figure 8 12 11 Transaction Control with Data Transfer Using DAT Line Sequence Not using DMA ...

Page 949: ...d proceed to step 10 W If read from a card go to step 10 R 10 W Wait for Buffer Write Ready Interrupt 11 W Write 1 to the Buffer Write Ready STABUFWTRDY in the Normal Interrupt Status register to clear this bit 12 W Write block data in according to the number of bytes specified at the step 1 to Buffer Data Port register 13 W Repeat until all blocks are sent and then go to step 14 10 R Wait for the...

Page 950: ...orresponding to the executed data block count in the Block Count register BLKCNT 4 Set the value corresponding to the issued command in the Argument register ARGUMENT 5 Set the values for Multi Single Block Select and Block Count Enable At this time set the value corresponding to the issued command for Data Transfer Direction Auto CMD12 Enable and DMA Enable 6 Set the value corresponding to the is...

Page 951: ...ransfer is executing There are two ways to issue an Abort Command The first is an asynchronous abort The second is a synchronous abort In an asynchronous abort sequence the Host Driver issues an Abort Command at anytime unless Command Inhibit CMD in the Present State register is set to 1 In a synchronous abort the Host Driver issues an Abort Command after the data transfer stopped by using Stop At...

Page 952: ...f 64 bit address registers Support of SDMA and ADMA are optional for the Host Controller ADMA improves the restriction so that data of any location and any size can be transferred in system memory The format of Descriptor Table is different between them The Host Controller Specification Ver2 00 defines ADMA as standard ADMA 7 1 BLOCK DIAGRAM OF ADMA Figure 8 12 13 Block Diagram of ADMA Figure 8 12...

Page 953: ... be terminated In this case the transfer should be aborted by data timeout Block Count register is defined as 16 bit register and it limits the maximum of 65535 blocks transfer If ADMA operation is less than or equal 65535 blocks transfer Block Count register can be used In this case total length of Descriptor Table shall be equivalent to multiply block size and block count If ADMA operation is mo...

Page 954: ...operation is used to connect separated two descriptors The address field of link points to next Descriptor Table The combination of Act2 0 and Act1 1 is reserved and defined the same operation as Nop A future version of controller may use this field and redefine a new operation 32 bit address is stored in the lower 32 bit of 64 bit address registers Address field shall be set on 32 bit boundary Lo...

Page 955: ...descriptor line If End 0 go to ST_TFR state ADMA shall not be stopped at this state even if some errors occur ST_TFR Transfer Data Data transfer of one descriptor line is executed between system memory and SD card If data transfer continues End 0 go to ST_FDS state If data transfer completes go to ST_STOP state ST_STOP Stop DMA ADMA stays in this state in following cases 1 After Power on reset or ...

Page 956: ...0DATA 0 muxed SD_0_D 1 IN OUT Data for HSMMC0 Xmmc0DATA 1 muxed SD_0_D 2 IN OUT Data for HSMMC0 Xmmc0DATA 2 muxed SD_0_D 3 IN OUT Data for HSMMC0 Xmmc0DATA 3 muxed SD_0_D 4 IN OUT Data for HSMMC0 Xmmc0DATA 4 muxed SD_0_D 5 IN OUT Data for HSMMC0 Xmmc0DATA 5 muxed SD_0_D 6 IN OUT Data for HSMMC0 Xmmc0DATA 6 muxed SD_0_D 7 IN OUT Data for HSMMC0 Xmmc0DATA 7 muxed SD_0_CDn INPUT Card Detect for HSMMC...

Page 957: ...IZE0 0xED80_0004 R W Host DMA Buffer Boundary and Transfer Block Size Register Channel 0 0x0 BLKCNT0 0xED80_0006 R W Blocks count for current transfer channel 0 0x0 ARGUMENT0 0xED80_0008 R W Command Argument Register Channel 0 0x0 TRNMOD0 0xED80_000C R W Transfer Mode Setting Register Channel 0 0x0 CMDREG0 0xED80_000E R W Command Register Channel 0 0x0 RSPREG0_0 0xED80_0010 ROC Response Register 0...

Page 958: ...terrupt Register Error Interrupt Channel 0 0x0000 ADMAERR0 0xED80_0054 R W ADMA Error Status Register Channel 0 0x00 ADMASYSADDR0 0xED80_0058 R W ADMA System Address Register Channel 0 0x00 CONTROL2_0 0xED80_0080 R W Control register 2 Channel 0 0x0 CONTROL3_0 0xED80_0084 R W FIFO Interrupt Control Control Register 3 Channel 0 0x7F5F3F1F CONTROL4_0 0xED80_008C R W Control register 4 Channel 0 0x0 ...

Page 959: ...0036 R W Error Interrupt Status Enable Register Channel 1 0x0 NORINTSIGEN1 0xED90_0038 R W Normal Interrupt Signal Enable Register Channel 1 0x0 ERRINTSIGEN1 0xED90_003A R W Error Interrupt Signal Enable Register Channel 1 0x0 ACMD12ERRSTS1 0xED90_003C ROC Auto CMD12 error status register channel 1 0x0 CAPAREG1 0xED90_0040 HWInit Capabilities Register Channel 1 0x05E80080 MAXCURR1 0xED90_0048 HWIn...

Page 960: ...rol Register Channel 2 0x0 BLKGAP2 0xEDA0_002A R W Block Gap Control Register Channel 2 0x0 WAKCON2 0xEDA0_002B R W Wakeup Control Register Channel 2 0x0 CLKCON2 0xEDA0_002 C R W Clock Control Register Channel 2 0x0 TIMEOUTCON2 0xEDA0_002E R W Timeout Control Register Channel 2 0x0 SWRST2 0xEDA0_002F R W Software Reset Register Channel 2 0x0 NORINTSTS2 0xEDA0_0030 ROC RW1C Normal Interrupt Status ...

Page 961: ...t Value SDMASYSAD 31 0 SDMA System Address This register contains the system memory address for a DMA transfer If the Host Controller stops a DMA transfer this register points to the system address of the next contiguous data position It is accessed if no transaction is executing i e after a transaction has stopped Read operations during transfers may return an invalid value The Host Driver initia...

Page 962: ...pt to request the Host Driver to update the SDMA System Address register At the end of transfer the Host Controller issue or not issue DMA Interrupt In particular DMA Interrupt is not issued after Transfer Complete Interrupt is issued If this register is set to 0 buffer size 4K bytes lower 12 bit of byte address points data in the contiguous buffer and the upper 20 bit points the location of the b...

Page 963: ...lues ranging from 1 up to maximum buffer size are set In case of memory it is set up to 512 bytes It is accessed only if no transaction is executing i e after a transaction has stopped Read operations during transfers return an invalid value and write operations are ignored 0200h 512 Bytes 01FFh 511 Bytes 0004h 4 Bytes 0003h 3 Bytes 0002h 2 Bytes 0001h 1 Byte 0000h No data transfer 0 ...

Page 964: ...d the maximum block count The Host Controller decrements the block count after each block transfer and stops if the count reaches zero Setting the block count to 0 results in no data blocks being transferred This register must be accessed if no transaction is executing i e after transactions are stopped During data transfer read operations on this register returns an invalid value and write operat...

Page 965: ...and The Host Driver saves the value of this register if data transfer is suspended as a result of a Suspend command and restore it before issuing a Resume command To prevent data loss the Host Controller implements write protection for this register during data transactions Writes to this register is ignored if the Command Inhibit DAT in Present State register is 1 TRNMOD Bit Description Reset Val...

Page 966: ...register which is only relevant for multiple block transfers If this bit is 0 the Block Count register is disabled which is useful in executing an infinite transfer Refer to the Table below Determination of Transfer Type 1 Enable 0 Disable 0 ENDMA 0 DMA Enable This bit enables DMA functionality DMA is enabled if it is supported as indicated in the DMA Support in the Capabilities register If DMA is...

Page 967: ...ommand If the Suspend command succeeds the Host Controller assumes that the SD Bus has been released and it is possible to issue the next command which uses the DAT line The Host Controller de asserts Read Wait for read transactions and stops checking busy for write transactions The interrupt cycle starts in 4 bit mode If the Suspend command fails the Host Controller maintains its current state an...

Page 968: ... response If an error is detected it is reported as a Command CRC Error If this bit is set to 0 the CRC field is not checked The number of bits checked by the CRC field value changes according to the length of the response 1 Enable 0 Disable Reserved 2 Reserved RSPTYP 1 0 Response Type Select 00 No Response 01 Response Length 136 10 Response Length 48 11 Response Length 48 check Busy after respons...

Page 969: ...el 1 RSPREG2_1 ROC Address 0xED90_0018 Response Register 3 Channel 1 RSPREG3_1 ROC Address 0xED90_001C Response Register 0 Channel 2 RSPREG0_2 ROC Address 0xEDA0_0010 Response Register 1 Channel 2 RSPREG1_2 ROC Address 0xEDA0_0014 Response Register 2 Channel 2 RSPREG2_2 ROC Address 0xEDA0_0018 Response Register 3 Channel 2 RSPREG3_2 ROC Address 0xEDA0_001C RSPREG Bit Description Reset Value CMDRSP...

Page 970: ...esponse data in one read cycle on a 32 bit bus system Parts of the response the Index field and the CRC are checked by the Host Controller as specified by the Command Index Check Enable and the Command CRC Check Enable bits in the Command register and generate an error interrupt if an error is detected The bit range for the CRC check depends on the response length If the response length is 48 the ...

Page 971: ...alid if Card State Stable is set to 1 but it is not guaranteed because of propagation delay Use of this bit is limited to testing since it must be debounced by software 1 Card present SDCD 0 0 No card present SDCD 1 Note SDCD port is mapped to SD0_nCD pin SD2_nCD Channel 2 port is fixed to LOW Line State STBLCARD 17 Card State Stable RO This bit is used for testing If this bit is 0 the Card Detect...

Page 972: ...he buffer and generates the Buffer Read Ready interrupt 1 Enables Read 0 Disables Read 0 BUFWTRDY 10 Buffer Write Enable ROC This status is used for non DMA write transfers The Host Controller implements multiple buffers to transfer data efficiently This read only flag indicates if space is available for write data If this bit is 1 data is written to the buffer A change of this bit from 1 to 0 occ...

Page 973: ...ndicates whether one of the DAT line on SD Bus is in use a In the case of read transactions This status indicates if a read transfer is executing on the SD Bus Change in this value from 1 to 0 between data blocks generates a Block Gap Event interrupt in the Normal Interrupt Status register This bit is set in either of the following cases 1 After the end bit of the read command 2 If 1 is written to...

Page 974: ...sfer Complete interrupt in the Normal Interrupt Status register Note The SD Host Driver saves registers in the range of 000 00Dh for a suspend transaction after this bit has changed from 1 to 0 1 Cannot issue command which uses the DAT line 0 Issues command which uses the DAT line 0 CMDINHCMD 0 Command Inhibit CMD ROC If this bit is 0 it indicates the CMD line is not in use and the Host Controller...

Page 975: ...1 0 8 12 40 Reset Power ON Debouncing Once debouncing clock becomes valid Card Inserted No Card SDCD 1 SDCD 0 Stable Stable Figure 8 12 17 Card Detect State The above Figure 8 12 17 shows the state definitions of hardware that handles Debouncing ...

Page 976: ... 41 Figure 8 12 18 Timing of Command Inhibit DAT and Command Inhibit CMD with Data Transfer Figure 8 12 19 Timing of Command Inhibit DAT for the Case of Response with Busy Figure 8 12 20 Timing of Command Inhibit CMD for the Case of No Response Command ...

Page 977: ...A Enable of the Transfer Mode register 00 Selects SDMA 01 Reserved 10 Selects 32 bit Address ADMA2 11 Selects 64 bit Address ADMA2 Not supported 0 ENHIGHSPD 2 High Speed Enable This bit is optional Before setting this bit the Host Driver checks the High Speed Support in the Capabilities register If this bit is set to 0 default the Host Controller outputs CMD line and DAT lines at the falling edge ...

Page 978: ... voltage level for the SD card Before setting this register the Host Driver checks the Voltage Support bits in the Capabilities register If an unsupported voltage is selected the Host System does not supply SD Bus voltage 111b 3 3V Typ 110b 3 0V Typ 101b 1 8V Typ 100b 000b Reserved 0 PWRON 0 SD Bus Power Before setting this bit the SD Host Driver sets SD Bus Voltage Select If the Host Controller d...

Page 979: ...l to stop read data using the DAT 2 line Otherwise the Host Controller has to stop the SD Clock to hold read data which restricts commands generation If the Host Driver detects an SD card insertion it sets this bit according to the CCCR of the SDIO card If the card does not support read wait this bit will never be set to 1 otherwise DAT line conflict might occur If this bit is set to 0 Suspend Res...

Page 980: ...r Active DAT Line Active and Command Inhibit DAT in the Present State register Regarding detailed control of bits D01 and D00 RW 1 Stop 0 Transfer There are three cases to restart the transfer after stop at the block gap Appropriate case depends on whether the Host Controller issues a Suspend command or the SD card accepts the Suspend command Cases are as follows 1 If the Host Driver does not issu...

Page 981: ... Card Interrupt Stop mode Wakeup Event Occurred ROC RW1C 1 Wakeup Interrupt Occurred 0 Wakeup Interrupt Not occurred or Cleared 0 ENWKUPREM 2 Wakeup Event Enable On SD Card Removal This bit enables wakeup event via Card Removal assertion in the Normal Interrupt Status register FN_WUS Wake Up Support in CIS does not affect this bit RW 1 Enables 0 Disable s 0 ENWKUPINS 1 Wakeup Event Enable On SD Ca...

Page 982: ...Setting 00h specifies the highest frequency of the SD Clock Setting multiple bits the most significant bit is used as the divisor But multiple bits must not be set The two default divider values are calculated by the frequency that is defined by the Base Clock Frequency For SD Clock in the Capabilities register 1 25MHz divider value 2 400kHz divider value According to the SD Physical Specification...

Page 983: ...ars the bit RW 1 Enables 0 Disables 0 STBLINTCLK 1 Internal Clock Stable This bit is set to 1 if SD Clock is stable after writing to Internal Clock Enable in this register to 1 The SD Host Driver waits to set SD Clock Enable until this bit is set to 1 Note This is useful if PLL is used for a clock oscillator that requires setup time ROC 1 Ready 0 Not Ready 0 ENINTCLK 0 Internal Clock Enable This b...

Page 984: ...ed 7 4 Reserved 0 TIMEOUTCON 3 0 Data Timeout Counter Value This value determines the interval by which DAT line timeouts are detected Refer to the Data Timeout Error in the Error Interrupt Status register for information on factors that dictate timeout generation Timeout clock frequency is generated by dividing the base clock TMCLK value by this value While setting this register prevent inadverte...

Page 985: ... by this bit Buffer Data Port register Buffer is cleared and initialized Present State register Buffer Read Enable Buffer Write Enable Read Transfer Active Write Transfer Active DAT Line Active Command Inhibit DAT Block Gap Control register Continue Request Stop At Block Gap Request Normal Interrupt Status register Buffer Read Ready Buffer Write Ready DMA Interrupt Block Gap Event Transfer Complet...

Page 986: ...ts initialization the Host Driver sets this bit to 1 to reset the Host Controller The Host Controller reset this bit to 0 if capabilities registers are valid and the Host Driver reads them If this bit is set to 1 the SD card resets itself and must be reinitialized by the Host Driver RWAC 1 Reset 0 Work ...

Page 987: ...s bit is set Therefore the Host Driver checks this bit first to efficiently tests for an error This bit is read only ROC 0 No Error 1 Error 0 STAFIA3 14 FIFO SD Address Pointer Interrupt 3 Status RW1C 0 Occurred 1 Not Occurred If the FIFO Address of the SD clock side reaches the FIFO Interrupt Address register 3 values this status bit is asserted 0 STAFIA2 13 FIFO SD Address Pointer Interrupt 2 St...

Page 988: ...status latched in the Host Controller and to stop driving the interrupt signal to the Host System After completion of the card interrupt service It must reset interrupt factors in the SD card and the interrupt signal may not be asserted write to one clear to this register field RW1C and set Card Interrupt Signal Enable to 1 to re start sampling the interrupt signal The Card Interrupt Status Enable...

Page 989: ...s set this bit is set if both read write transaction is stopped at a block gap If Stop At Block Gap Request is not set to 1 this bit is not set to 1 RW1C 1 In the case of a Read Transaction This bit is set at the falling edge of the DAT Line Active Status When the transaction is stopped at SD Bus timing The Read Wait must be supported in order to use this function 2 Case of Write Transaction This ...

Page 990: ...plete STACMDCMP LT 0 Command Complete This bit is set when get the end bit of the command response Except Auto CMD12 Refer to Command Inhibit CMD in the Present State register The table below shows that Command Timeout Error has higher priority than Command Complete If both bits are set to 1 it is considered that the response was not received correctly RW1C Command Complete Command Timeout Error M...

Page 991: ...er In addition the Host Controller generates this Interrupt if it detects invalid descriptor data Valid 0 at the ST_FDS state ADMA Error State in the ADMA Error Status indicates that an error occurs in ST_FDS state The Host Driver may find that Valid bit is not set at the error descriptor 1 Error 0 No Error 0 STAACMDERR 8 Auto CMD12 Error Occurs if it detects that one of the bits in Auto CMD12 Err...

Page 992: ... Error is set to 0 indicating no timeout this bit is set to 1 if it detects a CRC error in the command response 2 The Host Controller detects a CMD line conflict by monitoring the CMD line if a command is issued If the Host Controller drives the CMD line to 1 level but detects 0 levels on the CMD line at the next SDCLK edge then the Host Controller aborts the command Stop driving CMD line and set ...

Page 993: ...en Command CRC Error and Command Timeout Error is shown in Table below The relation between Command CRC Error and Command Timeout Error Command CRC Error Command Timeout Error Kinds of error 0 0 No Error 0 1 Response Timeout Error 1 0 Response CRC Error 1 1 CMD line conflict ...

Page 994: ...IA1 12 FIFO SD Address Pointer Interrupt 1 Status Enable 1 Enabled 0 Masked 0 ENSTAFIA0 11 FIFO SD Address Pointer Interrupt 0 Status Enable 1 Enabled 0 Masked 0 ENSTARWAIT 10 Read Wait interrupt status enable 1 Enabled 0 Masked 0 ENSTACCS 9 CCS Interrupt Status Enable 1 Enabled 0 Masked 0 ENSTACARDINT 8 Card Interrupt Status Enable If this bit is set to 0 the Host Controller clears interrupt requ...

Page 995: ...r Read Ready Status Enable 1 Enabled 0 Masked 0 ENSTABUFWTRDY 4 Buffer Write Ready Status Enable 1 Enabled 0 Masked 0 ENSTADMA 3 DMA Interrupt Status Enable 1 Enabled 0 Masked 0 ENSTABLKGAP 2 Block Gap Event Status Enable 1 Enabled 0 Masked 0 ENSTASTANSCMPLT 1 Transfer Complete Status Enable 1 Enabled 0 Masked 0 ENSTACMDCMPLT 0 Command Complete Status Enable 1 Enabled 0 Masked 0 ...

Page 996: ...le 1 Enabled 0 Masked 0 ENSTACURERR 7 Current Limit Error Status Enable This function is not implemented in this version 1 Enabled 0 Masked 0 ENSTADENDERR 6 Data End Bit Error Status Enable 1 Enabled 0 Masked 0 ENSTADATCRCERR 5 Data CRC Error Status Enable 1 Enabled 0 Masked 0 ENSTADATTOUTERR 4 Data Timeout Error Status Enable 1 Enabled 0 Masked 0 ENSTACMDIDXERR 3 Command Index Error Status Enable...

Page 997: ...rror Interrupt Signal Enable register 0 ENSIGFIA3 14 FIFO SD Address Pointer Interrupt 3 Signal Enable 1 Enabled 0 Masked 0 ENSIGFIA2 13 FIFO SD Address Pointer Interrupt 2 Signal Enable 1 Enabled 0 Masked 0 ENSIGFIA1 12 FIFO SD Address Pointer Interrupt 1 Signal Enable 1 Enabled 0 Masked 0 ENSIGFIA0 11 FIFO SD Address Pointer Interrupt 0 Signal Enable 1 Enabled 0 Masked 0 ENSIGRWAIT 10 Read Wait ...

Page 998: ...bled 0 Masked 0 ENSIGBUFWTRDY 4 Buffer Write Ready Signal Enable 1 Enabled 0 Masked 0 ENSIGDMA 3 DMA Interrupt Signal Enable 1 Enabled 0 Masked 0 ENSIGBLKGAP 2 Block Gap Event Signal Enable 1 Enabled 0 Masked 0 ENSIGSTANSCMPLT 1 Transfer Complete Signal Enable 1 Enabled 0 Masked 0 ENSIGCMDCMPLT 0 Command Complete Signal Enable 1 Enabled 0 Masked 0 ...

Page 999: ...led 0 Masked 0 ENSIGACMDERR 8 Auto CMD12 Error Signal Enable 1 Enabled 0 Masked 0 ENSIGCURERR 7 Current Limit Error Signal Enable This function is not implemented in this version 1 Enabled 0 Masked 0 ENSIGDENDERR 6 Data End Bit Error Signal Enable 1 Enabled 0 Masked 0 ENSIGDATCRCERR 5 Data CRC Error Signal Enable 1 Enabled 0 Masked 0 ENSIGDATTOUTERR 4 Data Timeout Error Signal Enable 1 Enabled 0 M...

Page 1000: ...r occurs in response to a command 1 Error 0 No Error 0 STACMDEBITAER 3 Auto CMD12 End Bit Error Occurs it detects that the end bit of command response is 0 1 End Bit Error Generated 0 No Error 0 STACMDCRCAER 2 Auto CMD12 CRC Error Occurs if it detects a CRC error in the command response 1 CRC Error Generated 0 No Error 0 STACMDTOUTAER 1 Auto CMD12 Timeout Error Occurs if no response is returned wi...

Page 1001: ... Set D00 to 0 if Auto CMD12 is issued 2 At the end bit of an Auto CMD12 response Check received responses by checking the error bits D01 D02 D03 and D04 Set to 1 if error is detected Set to 0 if error is not detected 3 Before reading the Auto CMD12 Error Status bit D07 Set D07 to 1 if there is a command cannot be issued Set D07 to 0 if there is no command to issue Timing to generate the Auto CMD12...

Page 1002: ...ted 0 CAPAV33 24 Voltage Support 3 3V HWInit 1 3 3V Supported 0 3 3V Not Supported 1 CAPASUSRES 23 Suspend Resume Support HWInit This bit indicates whether the Host Controller supports Suspend Resume functionality If this bit is 0 the Suspend and Resume mechanism are not supported and the Host Driver does not issue either Suspend or Resume commands 1 Supported 0 Not Supported 1 CAPADMA 22 DMA Supp...

Page 1003: ... 17MHz because the Host Driver use this value to calculate the clock divider value Refer to the SDCLK Frequency Select in the Clock Control register and it does not exceed upper limit of the SD Clock frequency The supported clock range is 10MHz to 63MHz If these bits are all 0 the Host System has to get information via another method Not 0 1MHz to 63MHz 000000b Get information via another method 0...

Page 1004: ... register If this information is supplied by the Host System via another method all Maximum Current Capabilities register will be 0 MAXCURR Bit Description Reset Value Reserved 31 24 Reserved MAXCURR18 23 16 Maximum Current for 1 8V HWInit 0 MAXCURR30 15 8 Maximum Current for 3 0V HWInit 0 MAXCURR33 7 0 Maximum Current for 3 3V HWInit 0 This register measures current in 4mA steps Each voltage leve...

Page 1005: ...g 0 no effect D15 D12 FEAER Bit Description Reset Value Reserved 15 8 Reserved 0x0 FENCMDAER 7 Force Event for Command Not Issued By Auto CMD12 Error 1 Generates Interrupt 0 No Interrupt 0 Reserved 6 5 Reserved 0 FECMDIDXERR 4 Force Event for Auto CMD12 Index Error 1 Interrupt 0 No Interrupt 0 FECMDEBITAER 3 Force Event for Auto CMD12 End Bit Error 1 Generates Interrupt 0 No Interrupt 0 FECMDCRCAE...

Page 1006: ...rder to generate interrupt signal both the Error Interrupt Status Enable and Error Interrupt Signal Enable shall be set FEERR Bit Description Reset Value Reserved 15 12 Reserved 0x0 Reserved 11 10 Reserved 0x0 FEADMAERR 9 Force Event for ADMA Error 1 Generates Interrupt 0 No Interrupt 0 FEACMDERR 8 Force Event for Auto CMD12 Error 1 Generates Interrupt 0 No Interrupt 0 Reserved 7 Reserved 0 FEDEND...

Page 1007: ...erates the ADMA Error Interrupt if it detects invalid descriptor data Valid 0 at the ST_FDS state In this case ADMA Error State indicates that an error occurs at ST_FDS state The Host Driver finds that the Valid bit is not set in the error descriptor ADMAERR Bit Description Reset Value Reserved 31 11 Reserved 0x00 STAADMAFINBLK 10 ADMA Final Block Transferred ROC In ADMA operation mode this field ...

Page 1008: ...urred during ADMA data transfer This field never indicates 10 because ADMA never stops in this state D01 D00 ADMA Error State when error is occurred Contents of SYS_SDR register 00 ST_STOP Stop DMA Points next of the error descriptor 01 ST_FDS Fetch Descriptor Points the error descriptor 10 Never set this state Not used 11 ST_TFR Transfer Data Points the next of the error descriptor 0 ...

Page 1009: ...Host Driver sets start address of the Descriptor table The ADMA increments this register address which points to next line if every fetching a Descriptor line If the ADMA Error Interrupt is generated this register holds valid Descriptor address depending on the ADMA state The Host Driver programs Descriptor Table on 32 bit boundary and set 32 bit boundary address to this register ADMA2 ignores low...

Page 1010: ...be 1 b0 0 SELCARDO UT 28 Card Removed Condition Selection 0 Card Removed condition is Not Card Insert State When the transition from Card Inserted state to Debouncing state in Figure 8 12 17 1 Card Removed state is Card Out State If the transition from Debouncing state to No Card state in Figure 8 12 17 0 FLTCLKSEL 27 24 Filter Clock iFLTCLK Selection Filter Clock period 2 FltClkSel 5 x iSDCLK per...

Page 1011: ...In this case the buffer memory is read through memory area Debug purpose 0 SELBASE CLK 5 4 Base Clock Source Select 00 or 01 HCLK 10 SCLK_MMC0 SCLK_MMC1 SCLK_MMC2 from CLKCON 11 SCLK_MMC0_48 SCLK_MMC1_48 SCLK_MMC2_48 XTI or XEXTCLK 00 SDINPSIGPC 3 SD Input Signal Power Control Support If set this field enables input CMD and DAT referencing SD Bus Power bit in the PWRCON register 0 No Sync no switc...

Page 1012: ...2 0x0 FIA1 14 8 FIFO Interrupt Address register 1 FIFO 512Byte Buffer memory word address unit Initial value 0x3F generates at 256 byte 64 word position 0x3F FCSEL0 7 Feedback Clock Select 0 Reference Note 2 0x0 FIA0 6 0 FIFO Interrupt Address register 0 FIFO 512Byte Buffer memory word address unit Initial value 0x1F generates at 128 byte 32 word position 0x1F NOTES 1 FCSel 3 2 Tx Feedback Clock D...

Page 1013: ... Reserved 0 SELCLKPADDS 17 16 SD Clock Output PAD Drive Strength Select 00 2mA 01 4mA 10 7mA 11 9mA Note This setting is for HSMMC Controller Channel 0 and 1 For HSMMC Channel 2 SELCLKPADDS is located in SPCON Special Port Control register bit 19 18 DRVCON_SPICLK 1 in GPIO module 0 Reserved 15 1 Reserved STABUSY 0 Status Busy This bit is High if the clock domain crossing HCLK to SDCLK operation is...

Page 1014: ...scription Reset Value VENVER 15 8 Vendor Version Number This status is reserved for the vendor version number The Host Driver should not use this status 0x04 SDMMC4 0 Host Controller 0x04 SPECVER 7 0 Specification Version Number This status indicates the Host Controller Specification Version The upper and lower 4 bits indicate the version 00 SD Host Specification Version 1 0 01 SD Host Specificati...

Page 1015: ...ing variable window size and etc The display controller supports various color formats as RGB 1bpp to 24 bpp and YCbCr 4 4 4 only local bus The display controller are programmed to support the different requirements on the screen related to the number of horizontal and vertical pixels data line width for the data interface interface timing and refresh rate The display controller transfers the vide...

Page 1016: ...ut from Local Bus FIMC0 Supports RGB 8 8 8 local input from Local Bus FIMC0 Window 1 Supports 1 2 4 or 8 bpp bit per pixel palettized color Supports 16 18 or 24 bpp non palettized color Supports YCbCr 4 4 4 local input from Local Bus FIMC1 Supports RGB 8 8 8 local input from Local Bus FIMC1 Supports YCbCr 4 4 4 local input from Local Bus Video Processor Window 2 Supports 1 2 4 or 8 bpp bit per pix...

Page 1017: ... S MANUAL REV1 0 DISPLAY CONTROLLER 9 1 3 Transparent Overlay Supports Transparent Overlay Color Key Chroma Key Supports Color key function Partial Display Supports LCD partial display fuction through i80 interface ...

Page 1018: ...erates RGB_VSYNC RGB_HSYNC RGB_VCLK RGB_VDEN VEN_VSYNC VEN_HSYNC VEN_FIELD VEN_HREF V601CLK V656CLK and SYS_CS0 SYS_CS1 SYS_WE and so on 3 2 DATA FLOW FIFO is present in the VDMA If FIFO is empty or partially empty VDMA requests data fetching from the frame memory based on the burst memory transfer mode The data transfer rate determines size of FIFO The display controller has five FIFOs because it...

Page 1019: ...S5PC100 USER S MANUAL REV1 0 DISPLAY CONTROLLER 9 1 5 Figure 9 1 2 Block Diagram of the Data Flow ...

Page 1020: ... status indicating signal This type of LCD driver contains a frame buffer and has the function of self refresh so display controller updates one still image by writing only one time to the LCD The Third and fourth types are ITU interfaces including both ITU R BT 601 interface which uses YUV data Vertical horizontal sync optional Field signal data valid signal and data sync clock and ITU R BT 656 i...

Page 1021: ...P3 P4 P5 LCD Panel NOTE 1 AEN Transparency value selection bit AEN 0 Select ALPHA0 AEN 1 Select ALPHA1 If per pixel blending is set then this pixel blends with alpha value selected by AEN Alpha value is selected by SFR value as ALPHA0_R ALPHA0_G ALPHA0_B ALPHA1_R ALPHA1_G ALPHA1_B For more information refer to Section SFR NOTE 2 D 23 16 Red data D 15 8 Green data D 7 0 Blue data NOTE 3 32BPP 8888 ...

Page 1022: ...election bit AEN 0 Select ALPHA0 AEN 1 Select ALPHA1 If per pixel blending is set then this pixel blends with alpha value selected by AEN Alpha value is selected by sfr value as ALPHA0_R ALPHA0_G ALPHA0_B ALPHA1_R ALPHA1_G ALPHA1_B For more information refer to Section SFR NOTE 2 D 22 15 Red data D 14 7 Green data D 6 0 Blue data ...

Page 1023: ...S5PC100 USER S MANUAL REV1 0 DISPLAY CONTROLLER 9 1 9 24BPP display 888 P1 P2 P3 P4 P5 LCD Panel NOTE D 23 16 Red data D 15 8 Green data D 7 0 Blue data ...

Page 1024: ...value selection bit AEN 0 Select ALPHA0 AEN 1 Select ALPHA1 If per pixel blending is set then this pixel belnds with alpha value selected by AEN SFR selects Alpha value as ALPHA0_R ALPHA0_G ALPHA0_B ALPHA1_R ALPHA1_G ALPHA1_B For more information refer to Section SFR NOTE 2 D 17 12 Red data D 11 6 Green data D 5 0 Blue data ...

Page 1025: ...S5PC100 USER S MANUAL REV1 0 DISPLAY CONTROLLER 9 1 11 18BPP display 666 P1 P2 P3 P4 P5 LCD Panel NOTE 1 D 17 12 Red data D 11 6 Green data D 5 0 Blue data ...

Page 1026: ...selection bit AEN 0 Select ALPHA0 AEN 1 Select ALPHA1 If per pixel blending is set then this pixel blends with alpha value selected by AEN Alpha value is selected by SFR value as ALPHA0_R ALPHA0_G ALPHA0_B ALPHA1_R ALPHA1_G ALPHA1_B For more information refer to Section SFR NOTE 2 D 14 10 Red data D 9 5 Green data D 4 0 Blue data ...

Page 1027: ...S5PC100 USER S MANUAL REV1 0 DISPLAY CONTROLLER 9 1 13 16BPP display 1555 P1 P2 P3 P4 P5 LCD Panel NOTE 1 D 14 10 D 15 Red data D 9 5 D 15 Green data D 4 0 D 15 Blue data ...

Page 1028: ...DISPLAY CONTROLLER S5PC100 USER S MANUAL REV1 0 9 1 14 6BPP display 565 P1 P2 P3 P4 P5 LCD Panel NOTE 1 D 15 11 Red data D 10 5 Green data D 4 0 Blue data ...

Page 1029: ...8H D 61 49 P1 P5 P9 D 62 AEN1 AEN5 AEN9 D 44 32 P2 P6 P10 D 45 AEN2 AEN6 AEN10 D 27 15 P3 P7 P11 D 28 AEN3 AEN7 AEN11 D 14 0 P4 P8 P12 D 15 AEN4 AEN8 AEN12 D 63 61 Dummy Dummy Dummy D 48 46 Dummy Dummy Dummy D 31 29 Dummy Dummy Dummy D 31 29 Dummy Dummy Dummy P1 P2 P3 P4 P5 LCD Panel NOTE 1 If per pixel blending is set then this pixel blends with alpha value selected by D 31 24 D 31 24 AR AG AB de...

Page 1030: ...sparency value selection bit AEN 0 Select ALPHA0 AEN 1 Select ALPHA1 If per pixel blending is set then this pixel blends alpha value selected by AEN Alpha value is selected by SFR value as ALPHA0_R ALPHA0_G ALPHA0_B ALPHA1_R ALPHA1_G ALPHA1_B For more information refer to Section SFR NOTE 2 D 6 5 Red data D 4 2 Green data D 1 0 Blue data ...

Page 1031: ...P10 P11 P12 P9 NOTE 1 AEN Transparency value selection bit AEN 0 Select ALPHA0 AEN 1 Select ALPHA1 If per pixel blending is set then this pixel blends with alpha value selected by AEN SFR value selects Alpha value as ALPHA0_R ALPHA0_G ALPHA0_B ALPHA1_R ALPHA1_G ALPHA1_B For more information refer to Section SFR ...

Page 1032: ...ansparency value selection bit AEN 0 Select ALPHA0 AEN 1 Select ALPHA1 If per pixel blending is set then this pixel blends with alpha value selected by AEN Alpha value is selected by SFR value as ALPHA0_R ALPHA0_G ALPHA0_B ALPHA1_R ALPHA1_G ALPHA1_B For more information refer to Section SFR ...

Page 1033: ...8 D 27 26 D 25 24 D 23 22 D 21 20 D 19 18 D 17 16 000H 008H D 15 14 D 13 12 D 11 10 D 9 8 D 7 6 D 5 4 D 3 2 D 1 0 000H 008H P17 P49 P18 P50 P19 P51 P20 P52 P21 P53 P22 P54 P23 P55 P24 P56 P25 P57 P26 P58 P27 P59 P28 P60 P29 P61 P30 P62 P31 P63 P32 P64 NOTE1 If ALPHAPAL is enabled then the MSB of Palette memory is acting as AEN bit AEN 0 Select ALPHA0 AEN 1 Select ALPHA1 If per pixel blending is se...

Page 1034: ...t SPSRAM Palette supports 8 8 8 6 6 6 5 6 5 R G B etc format For example of A 5 5 5 format write palette as shown in Table 9 1 2 and then connect VD pin to TFT LCD panel R 5 VD 23 19 G 5 VD 15 11 and B 5 VD 7 3 The AEN bit controls the blending function enable or disable At the end Set WPALCON W1PAL case window0 register to 0 b101 Specially 32 bit 8 8 8 8 format has an alpha value directly without...

Page 1035: ... 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0 00h 01h FFh Number of VD R 4 R 3 R 2 R 1 R 0 2 3 2 2 2 1 2 0 1 9 1 5 1 4 1 3 1 2 1 1 7 6 5 4 3 G 4 G 3 G 2 G 1 G 0 B 4 B 3 B 2 B 1 B 0 A E N R 4 R 3 R 2 R 1 R 0 G 4 G 3 G 2 G 1 G 0 B 4 B 3 B 2 B 1 B 0 A E N R 4 R 3 R 2 R 1 R 0 G 4 G 3 G 2 G 1 G 0 B 4 B 3 B 2 B 1 B 0 A E N ...

Page 1036: ...24 A 23 A 22 A 21 A 20 A 19 A 18 A 17 A 16 R4 R3 R2 R1 R0 G4 G3 G2 G1 G0 R4 B3 B2 B1 B0 I A 15 A 14 A 13 A 12 A 11 A 10 A 9 A 8 A 7 A 6 A 5 A 4 A 3 A 2 A 1 A 0 R4 R3 R2 R1 R0 G4 G3 G2 G1 G0 R4 B3 B2 B1 B0 I 1 2 3 4 5 LCD Panel 16BPP 5 6 5 Format Non Palette A 31 A 30 A 29 A 28 A 27 A 26 A 25 A 24 A 23 A 22 A 21 A 20 A 19 A 18 A 17 A 16 A 15 A 14 A 13 A 12 A 11 A 10 A 9 A 8 A 7 A 6 A 5 A 4 A 3 A 2 ...

Page 1037: ...tc win1 as a small next channel TV screen with win2 as a memu win3 as a caption win 4 as a channel information Win3 and win4 has the color limitation by using color index with Color LUT This feature enhances the system performance by reducing the data rate of total system Total 5 window example y win 0 base Local YCbCr RGB without palette y win 1 Overlay1 RGB with palette y win 2 Overlay2 RGB with...

Page 1038: ...ion1 factor a1 Foreground s Data blending equation1 factor b2 Background s Data blending equation2 factor a2 Foreground s Data blending equation2 factor Alpha value blending AR G B 01 AR G B 0 x q1 AR G B 1 x p1 AR G B 012 AR G B 01 x q2 AR G B 2 x p2 AR G B 0123 AR G B 012 x q3 AR G B 3 x p3 Where AR0 Window 0 s Red blending factor AG0 Window 0 s Green blending factor AB0 Window 0 s Blue blending...

Page 1039: ...p1 Foreground s Alpha value blending equation1 factor q2 Background s Alpha value blending equation2 factor p2 Foreground s Alpha value blending equation2 factor Figure 9 1 5 Blending Equation Default blending equation Data blending B B x 1 alphaA A x alphaA Alpha value blending alphaB 0 alphaB x 0 alphaA x 0 ...

Page 1040: ...le AEN value 1 the other is alpha value for transparnacy disable AEN value 0 If WINEN_F is enabled and BLD_PIX is enabled then AR will be choosen by the below equation AR Pixel R s AEN value 1 b1 Reg ALPHA1_R Reg ALPHA0_R AG Pixel G s AEN value 1 b1 Reg ALPHA1_G Reg ALPHA0_G AB Pixel B s AEN value 1 b1 Reg ALPHA1_B Reg ALPHA0_B where BLD_ PIX 1 If WINEN_F is enabled and BLD_PIX is disabled then AR...

Page 1041: ...ample Window n s blending factor decision n 0 1 2 3 4 For more information refer to Section SFR Figure 9 1 7 Blending Factor Decision NOTE Alpha value is DATA 15 12 DATA 15 12 4bit 8bit expanding if DATA 15 12 BPPMODE_F b 1110 ARGB4444 format is used to blend ...

Page 1042: ...OR KEY register specifying Color image of OSD layer substitutes by background image for special functionality as cursor image or pre view image of the camera OSD Image 180x100 Back Ground 320x240 Window3 Window1 Blended Apha f Window3 Window1 Window1 Window3 Window1 Window1 Window3 Blended Apha 9 Blended Apha 0 Color Key Enable Figure 9 1 8 Color Key Function Configurations ...

Page 1043: ...ntrol signals suitable for the support of many different types of display device The RGB_VSYNC signal asserts to cause the LCD s line pointer to start over at the top of the display The configuration of both HOZVAL field and LINEVAL registers controls pulse generation of RGB_VSYNC and RGB_HSYNC The size of the LCD panel according to the following equations determines HOZVAL and LINEVAL y HOZVAL Ho...

Page 1044: ...ontrol signals For more information refer to Figure 9 1 13 for Timing Diagram Their timing parameters LCD_CS_SETUP LCD_WR_SETUP LCD_WR_ACT and LCD_WR_HOLD are set through I80IFCONA0 and I80IFCONA1 SFRs 3 6 4 Partial Display Control Although partial display is a main feature of CPU style LDI VTIME_I80 does not support this function in H W logic SFR setting LINEVAL HOZVAL OSD_LeftTopX_F OSD_LeftTopY...

Page 1045: ...commands are available 3 7 2 Normal Command 1 Put commands into LDI_CMD0 11 maximum 12 commands 2 Set CMDx_EN in LDI_CMDCON0 to enable normal command x For example if you want to enable command 4 you have to set CMD4_EN to 0x01 3 Set NORMAL_CMD_ST in I80IFCONB0 1 y DISPLAY Controller has the following miscellaneous traits for command operations y Auto Normal Auto and Normal command mode is possibl...

Page 1046: ... RSPOL 0 1 Auto Command C0 VD 17 0 NORMAL_CMD_START SFR VD 17 0 pending C1 C3 C0 C1 C3 RS 2 Normal Command ENVIDS auto clear auto clear F n F n 1 F n 2 F n 3 F n 4 F n 5 F n 6 F n 7 C4 C3 C2 C1 F m C4 C3 C2 C1 F n F n 1 RS F m 1 F n 9 F n 8 Figure 9 1 9 Sending Command Indirect I80 Interface Trigger VTIME_I80 starts its operation if an S W trigger occurs There are two kinds of triggers S W trigger...

Page 1047: ...e VIDCON0 register value BPP BUS width Split DATA Command DSI_EN 1 24 24 X R 7 0 G 7 0 B 7 0 CMD 23 0 L0 1_DATA 000 16 16 X R 7 3 G 7 2 B 7 3 CMD 15 0 001 18 16 O 1st 2nd R 7 2 G 7 2 B 7 4 14 b0 B 3 2 CMD 15 0 010 18 9 O 1st 2nd R 7 2 G 7 5 G 4 2 B 7 2 CMD 17 9 CMD 8 0 011 24 16 O 1st 2nd R 7 0 G 7 0 B 7 0 8 b0 100 18 18 X R 7 2 G 7 2 B 7 2 CMD 17 0 101 16 8 O 1st 2nd R 7 3 G 7 5 G 4 2 B 7 3 CMD 1...

Page 1048: ...ne 9 of virtual screen This is the data of line 10 of virtual screen This is the data of line 10 of virtual screen This is the data of line 11 of virtual screen This is the data of line 11 of virtual screen Before Scrolling View Port The same size of LCD panel LINEVAL 1 OFFSIZE PAGEWIDTH This is the data of line 1 of virtual screen This is the data of line 1 of virtual screen This is the data of l...

Page 1049: ...ntrol signal 4 I80IFCONx CPU I F control signal 5 ITUIFCON ITU I F control signal 6 VIDTCONx Configures Video output Timing and determine the size of display 7 WINCONx Sets Each window format 8 VIDOSDxA VIDOSDxB Window position setting 9 VIDOSDxD Sets OSD size 10 VIDWxALPHA0 1 Sets Alpha value 11 BLENDEQx Sets Blending equation 12 VIDWxxADDx Sets Source image address setting 13 WxKEYCONx Color key...

Page 1050: ...D Video Clock XvVCLK Muxed LCD_VDEN Output Data Enable XvVDEN Muxed LCD_VD 23 0 Output YCbCr data output XvVD 23 0 Muxed NOTE Type field indicates whether pads are dedicated to the signal or pads are connected to the multiplexed signals 5 1 2 Timing V S Y N C H S Y N C V D E N V S P W 1 V B P D 1 V F P D 1 L IN E V A L 1 1 F R A M E V D E N H S P W 1 H B P D 1 H F P D 1 H O Z V A L 1 H S Y N C V C...

Page 1051: ...Muxed SYS_CS1 Output Chip select for LCD1 XvVSYNC Muxed SYS_WE Output Write enable XvVCLK Muxed SYS_OE Output Output Enable XvVD 23 Muxed SYS_RS SYS_ADD 0 Output Address Output SYS_ADD 0 is Register State select XvVDEN Muxed NOTE Type field indicates whether pads are dedicated to the signal or pads are connected to the multiplexed signals MIPI DSI mode when VIDCON0 30 1 SYS_ADD 1 SYS_ST 0 when VDO...

Page 1052: ...NC Output ITU601 Horizontal Sync Signal XvHSYNC Muxed VEN_FIELD Output ITU601 FIELD Signal option XvVD 23 Muxed VEN_DATA 7 0 Output ITU601 YUV422 format data output XvVD 7 0 Muxed V656_CLK Output ITU 656 data clock XvVD 22 Muxed V656_DATA 7 0 Output ITU656 YUV422 format data output XvVD 15 8 Muxed NOTE Type field indicates whether pads are dedicated to the signal or pads are connected to the multi...

Page 1053: ...DISPLAY CONTROLLER 9 1 39 VSYNC HSYNC Delay cycle Field 1 Field 2 VSYNC HSYNC FIELD Field 1 Field 2 When SELVSYNC 0 0 Figure 9 1 13 ITU R BT 601 Controllable Vsync Y Cb Y Cr Y Cb Y Cr Cb Figure 9 1 14 ITU R BT 601 Interface Timing ...

Page 1054: ...B VBPD 1 line Progressive Odd Field Interlaced VF VBPDE 1 line Even Field Interlaced HACT HOZVAL 1 x2 VCLK HS HSPW 1 x2 VCLK HB HBPD 1 x2 VCLK HF HFPD 1 x2 VCLK VFPD 1 line Progressive Odd Field Interlaced VFPDE 1 line Even Field Interlaced HFPD should be greater than 1 CLK V656_DATA 00 XY Y Cb Cr Y 00 00 XY 00 FF Y Y Cr FF SAV Active Data EAV 1 F V H P3 P2 P1 P0 8bit 80 10 Cb 80 10 10 Blanking Da...

Page 1055: ...D 2 VD 19 R 3 R 1 R 0 D 3 D 1 VD 18 R 2 R 0 D 2 D 0 VD 17 R 1 D 1 VD 16 R 0 D 0 VD 15 G 7 G 5 G 5 VD 14 G 6 G 4 G 4 VD 13 G 5 G 3 G 3 VD 12 G 4 G 2 G 2 VD 11 G 3 G 1 G 1 VD 10 G 2 G 0 G 0 VD 9 G 1 VD 8 G 0 VD 7 B 7 B 5 B 4 VEN_DATA 7 V656_DATA 7 VD 6 B 6 B 4 B 3 VEN_DATA 6 V656_DATA 6 VD 5 B 5 B 3 B 2 VEN_DATA 5 V656_DATA 5 VD 4 B 4 B 2 B 1 VEN_DATA 4 V656_DATA 4 VD 3 B 3 B 1 B 0 VEN_DATA 3 V656_D...

Page 1056: ...st 2nd VD 23 VD 22 VD 21 VD 20 VD 19 VD 18 VD 17 R 5 VD 16 R 4 VD 15 R 4 R 5 R 7 B 7 R 3 VD 14 R 3 R 4 R 6 B 6 R 2 VD 13 R 2 R 3 R 5 B 5 R 1 VD 12 R 1 R 2 R 4 B 4 R 0 VD 11 R 0 R 1 R 3 B 3 G 5 VD 10 G 5 R 0 R 2 B 2 G 4 VD 9 G 4 G 5 R 1 B 1 G 3 VD 8 G 3 G 4 R 5 G 2 R 0 B 0 G 2 VD 7 G 2 G 3 R 4 G 1 G 7 G 1 R 4 G 2 VD 6 G 1 G 2 R 3 G 0 G 6 G 0 R 3 G 1 VD 5 G 0 G 1 R 2 B 5 G 5 B 5 R 2 G 0 VD 4 B 4 G 0...

Page 1057: ...o Window 1 s position control register 0x0000_0000 VIDOSD1B 0xEE00_0054 R W Video Window 1 s position control register 0x0000_0000 VIDOSD1C 0xEE00_0058 R W Video Window 1 s alpha control register 0x0000_0000 VIDOSD1D 0xEE00_005C R W Video Window 1 s size control register 0x0000_0000 VIDOSD2A 0xEE00_0060 R W Video Window 2 s position control register 0x0000_0000 VIDOSD2B 0xEE00_0064 R W Video Windo...

Page 1058: ... size register 0x0000_0000 VIDW04ADD2 0xEE00_0110 R W Window 4 s buffer size register 0x0000_0000 VP1TCON0 0xEE00_0118 R W VP 1 interface timing control 0 register 0x0000_0000 VP1TCON1 0xEE00_011c R W VP 1 interface timing control 1 register 0x0000_0000 VIDINTCON0 0xEE00_0130 R W Indicate the Video interrupt control register 0x0000_0000 VIDINTCON1 0xEE00_0134 R W Video Interrupt Pending register 0...

Page 1059: ...ha value 0 register 0x0000_0000 VIDW1ALPHA1 0xEE00_020c R W Window 1 s alpha value 1 register 0x0000_0000 VIDW2ALPHA0 0xEE00_0210 R W Window 2 s alpha value 0 register 0x0000_0000 VIDW2ALPHA1 0xEE00_0214 R W Window 2 s alpha value 1 register 0x0000_0000 VIDW3ALPHA0 0xEE00_0218 R W Window 3 s alpha value 0 register 0x0000_0000 VIDW3ALPHA1 0xEE00_021c R W Window 3 s alpha value 1 register 0x0000_000...

Page 1060: ...face LDI Command 10 0x0000_0000 LDI_CMD11 0xEE00_02AC R W I80 Interface LDI Command 11 0x0000_0000 PalRam Palette Memory Start address End address R W Description Reset value Win0 PalRam 0xEE00_2400 0xEE00_0400 0xEE00_27FC 0xEE00_07FC R W 0 255 entry palette data Undefined Win1 PalRam 0xEE00_2800 0xEE00_0800 0xEE00_2BFC 0xEE00_0BFC R W 0 255 entry palette data Undefined Win2 PalRam 0xEE00_2C00 0xE...

Page 1061: ...output data format mode of Indirect I80 I F LDI1 If VIDOUT 1 0 2 b11 000 16 bit mode 16 bpp 001 16 2 bit mode 18 bpp 010 9 9 bit mode 18 bpp 011 16 8 bit mode 24 bpp 100 18 bit mode 18bpp 101 8 8 bit mode 16bpp 000 L0_DATA16 22 20 Selects output data format mode of Indirect I80 I F LDI0 If VIDOUT 1 0 2 b10 000 16 bit mode 16 bpp 001 16 2 bit mode 18 bpp 010 9 9 bit mode 18 bpp 011 16 8 bit mode 24...

Page 1062: ...e 0 HCLK 1 SCLK_LCD 0 ENVID 1 Video output and the logic immediately enable disable 0 Disables the video output and the Display control signal 1 Enables the video output and the Display control signal 0 ENVID_F 0 Video output and the logic enable disable at current frame end 0 Disables the video output and the Display control signal 1 Enables the video output and the Display control signal If this...

Page 1063: ... HSYNC pulse polarity 0 Normal 1 Inverted 0 IVSYNC 5 This bit indicates the VSYNC pulse polarity 0 Normal 1 Inverted 0 IVDEN 4 This bit indicates the VDEN signal polarity 0 Normal 1 Inverted 0 Reserved 3 0 Reserved 0x0 6 3VIDEO MAIN CONTROL 2 REGISTER VIDCON2 R W ADDRESS 0XEE00_ 0008 VIDCON2 Bit Description Reset Value Reserved 31 24 Reserved 0 EN601 23 Control ITU601 output enable 0 Disables 1 En...

Page 1064: ... number of inactive lines at the start of a frame after vertical synchronization period 0x00 VFPD 15 8 Vertical front porch is the number of inactive lines at the end of a frame before vertical synchronization period 0x00 VSPW 7 0 Vertical sync pulse width determines the VSYNC pulse s high level width by counting the number of inactive lines 0x00 6 6VIDEO TIME CONTROL 1 REGISTER VIDTCON1 R W ADDRE...

Page 1065: ...ESS 0XEE00_ 0018 VIDTCON2 Bit Description Reset Value LINEVAL 21 11 These bits determine the vertical size of display In Interlace mode LINEVAL 1 should have even value 0 HOZVAL 10 0 These bits determine the horizontal size of display 0 NOTE HOZVAL Horizontal display size 1 LINEVAL Vertical display size 1 ...

Page 1066: ...ENWIN_F disable state 0 BUFSTATUS 21 Buffer Status Read Only 0 buffer set 0 1 buffer set 1 0 BUFSEL 20 Select Buffer set 0 1 0 buffer set 0 1 buffer set 1 0 BUFAUTOEN 19 Double Buffer Auto control bit 0 Fixed by BUFSEL 1 Auto changed by Trigger Input 0 BITSWP 18 Bit swap control bit 0 Disables Swap 1 Enables Swap 0 BYTSWP 17 Byte swaps control bit 0 Disables Swap 1 Enables Swap 0 HAWSWP 16 Half Wo...

Page 1067: ... 8 B 7 1101 unpacked 25 bpp non palletized A 1 R 8 G 8 B 8 1110 unpacked 13 bpp non palletized A 1 R 4 G 4 B 4 1111 unpacked 15 bpp non palletized R 5 G 5 B 5 Note 1101 supports unpacked 32 bpp non palletized A 8 R 8 G 8 B 8 for per pixel blending 1110 support 16 bpp non palletized A 4 R 4 G 4 B 4 for per pixel blending 16 level blending 0 ALPHA_SEL 1 Select Alpha value by If Per plane blending ca...

Page 1068: ... that the source of CAMIF1 must be memory not external camera MS DMA transfers from memory to CAMIF1 0 ENLOCAL 22 Select Data access method 0 Dedicated DMA 1 Local Path Note This register must be disabled at the ENWIN_F disable state 0 BUFSTATUS 21 Buffer Status Read Only 0 buffer set 0 1 buffer set 1 0 BUFSEL 20 Select Buffer set 0 1 0 buffer set 0 1 buffer set 1 0 BUFAUTOEN 19 Double Buffer Auto...

Page 1069: ...pp non palletized A 1 R 5 G 5 B 5 0111 16 bpp non palletized I 1 R 5 G 5 B 5 1000 unpacked 18 bpp non palletized R 6 G 6 B 6 1001 unpacked 18 bpp non palletized A 1 R 6 G 6 B 5 1010 unpacked 19 bpp non palletized A 1 R 6 G 6 B 6 1011 unpacked 24 bpp non palletized R 8 G 8 B 8 1100 unpacked 24 bpp non palletized A 1 R 8 G 8 B 7 1101 unpacked 25 bpp non palletized A 1 R 8 G 8 B 8 1110 unpacked 13 bp...

Page 1070: ... Selects Data access method 0 Dedicated DMA 1 Local Path CAMIF2 FIFO Out This register must be disabled at the ENWIN_F disable state 0 Reserved 21 19 Reserved BITSWP 18 Bit swap control bit 0 Disables Swap 1 Enables Swap 0 BYTSWP 17 Byte swaps control bit 0 Disables Swap 1 Enables Swap 0 HAWSWP 16 Half Word swap control bit 0 Disables Swap 1 Enables Swap 0 WSWP 15 Word swap control bit 0 Disables ...

Page 1071: ...ed A 1 R 6 G 6 B 6 1011 unpacked 24 bpp non palletized R 8 G 8 B 8 1100 unpacked 24 bpp non palletized A 1 R 8 G 8 B 7 1101 unpacked 25 bpp non palletized A 1 R 8 G 8 B 8 1110 unpacked 13 bpp non palletized A 1 R 4 G 4 B 4 1111 unpacked 15 bpp non palletized R 5 G 5 B 5 Note 1101 supports unpacked 32 bpp non palletized A 8 R 8 G 8 B 8 for per pixel blending 1110 support 16 bpp non palletized A 4 R...

Page 1072: ... 1 ALPHA_SEL 1 and BPPMODE_F 5 2 4 b1101 or 4 b1110 Note i Alpha value alpha_pixel from data ALPHA0_R G B ii In this mode you can only select two cases BLENDEQ3 A_FUNC alphaA B_FUNC 1 alphaA A_FUNC alphaA B_FUNC max pre multiplied 0 BLD_PIX 6 Select blending category 0 Per plane blending 1 Per pixel blending 0 BPPMODE_F 5 2 Select the BPP Bits Per Pixel mode Window image 0000 1 bpp 0001 2 bpp 0010...

Page 1073: ...l blending 16 level blending ALPHA_SEL 1 Select Alpha value by If Per plane blending case BLD_PIX 0 0 using ALPHA0_R G B values 1 using ALPHA1_R G B values If Per pixel blending BLD_PIX 1 0 selected by AEN A value or chroma key 1 using DATA 31 24 data in word boundary only when BPPMODE_F 4 b1101 DATA 31 28 15 12 data in word boundary only when BPPMODE_F 4 b1110 0 ENWIN_F 0 Video output and the log...

Page 1074: ... 1 ALPHA_SEL 1 and BPPMODE_F 5 2 4 b1101 or 4 b1110 Note i Alpha value alpha_pixel from data ALPHA0_R G B ii In this mode you can only select two cases BLENDEQ4 A_FUNC alphaA B_FUNC 1 alphaA A_FUNC alphaA B_FUNC max pre multiplied 0 BLD_PIX 6 Select blending category 0 Per plane blending 1 Per pixel blending 0 BPPMODE_F 5 2 Select the BPP Bits Per Pixel mode Window image 0000 1 bpp 0001 2 bpp 0010...

Page 1075: ...l blending 16 level blending ALPHA_SEL 1 Select Alpha value by If Per plane blending case BLD_PIX 0 0 using ALPHA0_R G B values 1 using ALPHA1_R G B values If Per pixel blending BLD_PIX 1 0 selected by AEN A value or chroma key 1 using DATA 31 24 data in word boundary only when BPPMODE_F 4 b1101 DATA 31 28 15 12 data in word boundary only when BPPMODE_F 4 b1110 0 ENWIN_F 0 Video output and the log...

Page 1076: ...to half of the original screen y coordinate The original screen y coordinate MUST be odd value 0 NOTE Registers must have word boundary X position So 24 BPP mode must have X position by 1 pixel Ex X 0 1 2 3 16 BPP mode must have X position by 2 pixel Ex X 0 2 4 6 8 BPP mode must have X position by 4 pixel Ex X 0 4 8 12 6 15 WINDOW 0 POSITION CONTROL C REGISTER VIDOSD0C R W ADDRESS 0XEE00_ 0048 VID...

Page 1077: ...X position by 4 pixel Ex X 0 4 8 12 NOTE2 In case of VP interface window s height should be greater than 1 RigthBotY LeftTopY 0 6 18 WINDOW 1 POSITION CONTROL C REGISTER VIDOSD1C R W ADDRESS 0XEE00_ 0058 VIDOSD1C Bit Description Reset Value Reserved 24 Reserved 0 ALPHA0_R_H 23 20 Red Alpha upper value case AEN 0 0 ALPHA0_G_H 19 16 Green Alpha upper value case AEN 0 0 ALPHA0_B_H 15 12 Blue Alpha up...

Page 1078: ...rdinate The original screen y coordinate MUST be odd value 0 NOTE Registers must have word boundary X position Therefore 24 BPP mode must have X position by 1 pixel Ex X 0 1 2 3 16 BPP mode must have X position by 2 pixel Ex X 0 2 4 6 8 BPP mode must have X position by 4 pixel Ex X 0 4 8 12 6 22 WINDOW 2 POSITION CONTROL C REGISTER VIDOSD2C R W ADDRESS 0XEE00_ 0068 VIDOSD2C Bit Description Reset V...

Page 1079: ...reen coordinate for right bottom pixel of OSD image For interlace TV output this value MUST be set to half of the original screen y coordinate The original screen y coordinate MUST be odd value 0 NOTE Registers must have word boundary X position Therefore 24 BPP mode must have X position by 1 pixel Ex X 0 1 2 3 16 BPP mode must have X position by 2 pixel Ex X 0 2 4 6 8 BPP mode must have X positio...

Page 1080: ...reen coordinate for right bottom pixel of OSD image For interlace TV output this value MUST be set to half of the original screen y coordinate The original screen y coordinate MUST be odd value 0 NOTE Registers must have word boundary X position Therefore 24 BPP mode must have X position by 1 pixel Ex X 0 1 2 3 16 BPP mode must have X position by 2 pixel Ex X 0 2 4 6 8 BPP mode must have X positio...

Page 1081: ...1 24 of the bank location for the video buffer in the system memory 0 VBASEU_F 23 0 These bits indicate A 23 0 of the start address of the Video frame buffer 0 6 31 FRAME BUFFER ADDRESS 1 REGISTER VIDW y VIDW00ADD1B0 R W Address 0xEE00_ 00D0 y VIDW00ADD1B1 R W Address 0xEE00_ 00D4 y VIDW01ADD1B0 R W Address 0xEE00_ 00D8 y VIDW01ADD1B1 R W Address 0xEE00_ 00DC y VIDW02ADD1 R W Address 0xEE00_ 00E0 ...

Page 1082: ...r value than the burst size and the size must be aligned word boundary 0 NOTE PAGEWIDTH OFFSET should be aligned double word aligned 8 byte 6 33 VP 1 INTERFACE TIMING CONTROL 0 REGISTER VP1TCON0 R W ADDRESS 0XEE00_ 0118 VP1TCON0 Bit Description Reset Value VP1_RATECON_ EN 31 RATE Register control enable VP FIMD clk ratio 0 auto control when FIMD VCLK is determined by CLKVAL_F and HCLK 1 rate contr...

Page 1083: ...rrupt Enable control only for I80 Interface mode 0 Disables Interrupt 1 Enables Interrupt Note This bit is meaningful if INTEN is high 0 FRAMESEL0 16 15 Video Frame Interrupt 0 at start of 00 BACK Porch 01 VSYNC 10 ACTIVE 11 FRONT Porch 0 FRAMESEL1 14 13 Video Frame Interrupt 1 at start of 00 None 01 BACK Porch 10 VSYNC 11 FRONT Porch 0 INTFRMEN 12 Video Frame interrupts Enable control bit 0 Disab...

Page 1084: ... and LCD 3 Refer to 4 1 VECTORED INTERRUPT CONTROLLER LCD 0 is FIFO Level interrupt LCD 1 is video frame sync interrupt LCD 2 is i80 done interface interrupt LCD 3 is VP under run interrupt 6 36 VIDEO INTERRUPT CONTROL 1 REGISTER VIDINTCON1 R W ADDRESS 0XEE00_ 0134 VIDINTCON1 Bit Description Reset Value INTVPPEND 5 VP under run interrupt Write 1 to clear this bit 0 Interrupt has not been requested...

Page 1085: ...ble control 0 Disables color key 1 Enables color key 0 DIRCON 24 Color key Chroma key direction control 0 If the pixel value match fore ground image with COLVAL pixel from back ground image is displayed only in OSD area 1 If the pixel value match back ground with COLVAL pixel from fore ground image is displayed only in OSD area 0 COMPKEY 23 0 Each bit is corresponding to the COLVAL 23 0 If some po...

Page 1086: ...able control 0 Disables color key 1 Enables color key 0 DIRCON 24 Color key Chroma key direction control 0 If the pixel value matches fore ground image with COLVAL pixel from back ground image is displayed only in OSD area 1 If the pixel value matches back ground with COLVAL pixel from fore ground image is displayed only in OSD area 0 COMPKEY 23 0 Each bit corresponds to the COLVAL 23 0 If some po...

Page 1087: ...to use alpha blending using color key 6 42 WIN3 COLOR KEY 1 REGISTER W3KEYCON1 R W ADDRESS 0XEE00_ 0154 W3KEYCON1 Bit Description Reset Value COLVAL 23 0 Color key value for the transparent pixel effect 0 6 43 WIN4 COLOR KEY 0 REGISTER W4KEYCON0 R W ADDRESS 0XEE00_ 0158 W4KEYCON0 Bit Description Reset Value KEYBLEN_F 26 Color Key Chroma key Enable control 0 Disables Disables blending operation dis...

Page 1088: ...e BPP24 mode 24 bit color value is valid A COLVAL y Red COLVAL 23 17 y Green COLVAL 15 8 y Blue COLVAL 7 0 B COMPKEY y Red COMPKEY 23 17 y Green COMPKEY 15 8 y Blue COMPKEY 7 0 BPP16 5 6 5 mode 16 bit color value is valid A COLVAL y Red COLVAL 23 19 y Green COLVAL 15 10 y Blue COLVAL 7 3 B COMPKEY y Red COMPKEY 23 19 y Green COMPKEY 15 10 y Blue COMPKEY 7 3 y COMPKEY 18 16 must be 0x7 y COMPKEY 9 ...

Page 1089: ...ithering Enable bit 0 Disables dithering 1 Enables dithering 0 6 46 WIN0 COLOR MAP WIN0MAP R W ADDRESS 0XEE00_ 0180 WIN0MAP Bit Description Reset Value MAPCOLEN_F 24 Window s color mapping control bit If this bit is enabled then Video DMA will stop and MAPCOLOR will be appear on back ground image instead of original image 0 Disables 1 Enables 0 MAPCOLOR 23 0 Color Value 0 6 47 WIN1 COLOR MAP WIN1M...

Page 1090: ...IN3MAP R W ADDRESS 0XEE00_ 018C WIN3MAP Bit Description Reset Value MAPCOLEN_F 24 Window s color mapping control bit If this bit is enabled then Video DMA stops and MAPCOLOR appears on background image instead of original image 0 Disables 1 Enables 0 MAPCOLOR 23 0 Color Value 0 6 50 WIN4 COLOR MAP WIN4MAP R W ADDRESS 0XEE00_ 0190 WIN4MAP Bit Description Reset Value MAPCOLEN_F 24 Window s color map...

Page 1091: ...served 0 PALUPDATEEN 9 0 Normal Mode 1 Enable Palette Update 0 W4PAL_L 8 W4PAL 0 0 W3PAL_L 7 W3PAL 0 0 W2PAL_L 6 W2PAL 0 0 W1PAL_L 5 3 W1PAL 2 0 0 W0PAL_L 2 0 W0PAL 2 0 0 NOTE WPALCON WPALCON_H WPALCON_L WPALCON Description Reset Value PALUPDATEEN 0 Normal Mode 1 Enable Palette Update 0 W4PAL 3 0 This bit determines the size of the palette data format of Window 4 000 16 bit 5 6 5 001 16 bit A 5 5 ...

Page 1092: ... 25 bit A 8 8 8 111 32 bit 8 8 8 8 A 8bit 0 W1PAL 2 0 This bit determines the size of the palette data format of Window 1 000 25 bit A 8 8 8 001 24 bit 8 8 8 010 19 bit A 6 6 6 011 18 bit A 6 6 5 100 18 bit 6 6 6 101 16 bit A 5 5 5 110 16 bit 5 6 5 111 32 bit 8 8 8 8 A 8bit 0 W0PAL 2 0 This bit determines the size of the palette data format of Window 0 000 25 bit A 8 8 8 001 24 bit 8 8 8 010 19 bi...

Page 1093: ...1 Buffer Software Triggering Command Write Only 0 Reserved 5 3 Reserved 0 SWFRSTATUS 2 I80 Frame Done Status Read Only 0 Not Requested 1 Requested Clear Condition Read or New Frame Start Only when TRGMODE is 1 0 SWTRGCMD 1 1 i80 Software Triggering Command Write Only If TRGMODE is 1 0 TRGMODE 0 0 i80 Software Trigger Disable 1 i80 Software Trigger Enable 0 NOTE Two continuous SW trigger inputs whi...

Page 1094: ...dard 0 Reserved 15 10 Reserved 0 I656FIELD 9 The polarity of the F value in timing reference code 0 normal 1 inverted 0 I656CLK 8 The polarity of the V656_CLK active edge 0 normal 1 inverted 0 Reserved 7 Reserved 0 I601HREF 6 The polarity of the VEN_HREF Signal 0 normal 1 inverted 0 I601VSYNC 5 The polarity of the VEN_VSYNC Signal 0 normal 1 inverted 0 I601HSYNC 4 The polarity of the VEN_HSYNC Sig...

Page 1095: ...ignal enable to the chip select enable 0 LCD_WR _SETUP 15 12 Numbers of clock cycles for the active period of the CS signal enable to the write signal enable 0 LCD_WR_ACT 11 8 Numbers of clock cycles for the active period of the chip select enable 0 LCD_WR _HOLD 7 4 Numbers of clock cycles for the active period of the chip select disable to the write signal disable 0 Reserved 3 Reserved RSPOL 2 Th...

Page 1096: ...t Description Reset Value Reserved 11 10 Reserved 0 NORMAL_CMD_ST 9 1 Normal Command Start Auto clear after sending one set of commands 0 Reserved 8 7 Reserved FRAME_SKIP 6 5 I80 Interface Output Frame Decimation Factor 00 1 No Skip 01 2 10 3 00 Reserved 4 Reserved 0 AUTO_CMD_RATE 3 0 0000 Disables auto command 0001 per 2 Frames 0010 per 4 Frames 0011 per 6 Frames 1111 per 30 Frames 0000 ...

Page 1097: ... 17 16 00 Disables 01 Enables Normal Command 10 Enables Auto Command 11 Enables Normal and Auto Command 00 CMD7_EN 15 14 00 Disables 01 Enables Normal Command 10 Enables Auto Command 11 Enables Normal and Auto Command 00 CMD6_EN 13 12 00 Disables 01 Enables Normal Command 10 Enables Auto Command 11 Enables Normal and Auto Command 00 CMD5_EN 11 10 00 Disables 01 Enables Normal Command 10 Enables Au...

Page 1098: ...d 00 6 58 LCD I80 INTERFACE COMMAND CONTROL 1 LDI_CMDCON1 R W ADDRESS 0XEE00_ 01D4 LDI_CMDCON1 Bit Description Reset Value Reserved 31 10 Reserved 0 CMD11_RS 11 Command 11 RS control 0 CMD10_RS 10 Command 10 RS control 0 CMD9_RS 9 Command 9 RS control 0 CMD8_RS 8 Command 8 RS control 0 CMD7_RS 7 Command 7 RS control 0 CMD6_RS 6 Command 6 RS control 0 CMD5_RS 5 Command 5 RS control 0 CMD4_RS 4 Comm...

Page 1099: ... Signal control 0 Disables High 1 Enables Low 0 SYS_nOE_CON 2 LCD i80 System Interface nOE Signal control 0 Disables High 1 Enables Low 0 SYS_nWE_CON 1 LCD i80 System Interface nWE Signal control 0 Disables High 1 Enables Low 0 SCOMEN 0 LCD i80 System Interface Command Mode Enable 0 Disables Normal Mode 1 Enables Manual Command Mode 6 60 I80 SYSTEM INTERFACE MANUAL COMMAND CONTROL 1 SIFCCON1 R W A...

Page 1100: ...et Value Reserved 24 Reserved 0 ALPHA1_R 23 16 Red Alpha value case AEN 1 0 ALPHA1_G 15 8 Green Alpha value case AEN 1 0 ALPHA1_B 7 0 Blue Alpha value case AEN 1 0 6 64 WINDOW 1 ALPHA0 CONTROL REGISTER VIDW1ALPHA0 R W ADDRESS 0XEE00_ 0208 VIDW1ALPHA0 Bit Description Reset Value Reserved 24 Reserved 0 Reserved 23 20 Reserved 0 ALPHA0_R_L 19 16 Red Alpha lower value case AEN 0 0 Reserved 15 12 Reser...

Page 1101: ...t Value Reserved 24 Reserved 0 Reserved 23 20 Reserved 0 ALPHA0_R_L 19 16 Red Alpha lower value case AEN 0 0 Reserved 15 12 Reserved 0 ALPHA0_G_L 11 8 Green Alpha lower value case AEN 0 0 Reserved 7 4 Reserved 0 ALPHA0_B_L 3 0 Blue Alpha lower value case AEN 0 0 NOTE ALPHA0_R G B 7 4 ALPHA0_R G B _H 3 0 VIDOSD2C ALPHA0_R G B 3 0 ALPHA0_R G B _L 3 0 VIDW2ALPHA0 6 67 WINDOW 2 ALPHA1 CONTROL REGISTER...

Page 1102: ...t Value Reserved 24 Reserved 0 Reserved 23 16 Reserved 0 ALPHA1_R_L 19 16 Red Alpha lower value case AEN 1 0 Reserved 15 12 Reserved 0 ALPHA1_G_L 11 8 Green Alpha lower value case AEN 1 0 Reserved 7 4 Reserved 0 ALPHA1_B_L 3 0 Blue Alpha lower value case AEN 1 0 NOTE ALPHA1_R G B 7 4 ALPHA1_R G B _H 3 0 VIDOSD3C ALPHA1_R G B 3 0 ALPHA1_R G B _L 3 0 VIDW3ALPHA1 6 70 WINDOW 4 ALPHA0 CONTROL REGISTER...

Page 1103: ...NDEQ1 Bit Description Reset Value reserved 31 22 reserved 0x000 Q_FUNC 21 18 Constant used in alphaB alpha value of background 0000 0 zero 0001 1 max 0010 alphaA alpha value of foreground 0011 1 alphaA 0100 alphaB 0101 1 alphaB 011x reserved 100x reserved 1010 A foreground color data 1011 1 A 1100 B background color data 1101 1 B 111x reserved 0x0 reserved 17 16 Reserved 00 P_FUNC 15 12 Constant u...

Page 1104: ...erved 100x reserved 1010 A foreground color data 1011 1 A 1100 B background color data 1101 1 B 111x reserved 0x0 Reserved 17 16 Reserved 00 P_FUNC 15 12 Constant used in alphaA Same as above refer the COEF_Q 0x0 Reserved 11 10 Reserved 00 B_FUNC 9 6 Constant used in B Same as above refer the COEF_Q 0x3 Reserved 5 4 Reserved 00 A_FUNC 3 0 Constant used in A Same as above refer the COEF_Q 0x2 NOTE ...

Page 1105: ...erved 100x reserved 1010 A foreground color data 1011 1 A 1100 B background color data 1101 1 B 111x reserved 0x0 Reserved 17 16 Reserved 00 P_FUNC 15 12 Constant used in alphaA Same as above refer the COEF_Q 0x0 Reserved 11 10 Reserved 00 B_FUNC 9 6 Constant used in B Same as above refer the COEF_Q 0x3 Reserved 5 4 Reserved 00 A_FUNC 3 0 Constant used in A Same as above refer the COEF_Q 0x2 NOTE ...

Page 1106: ...d 0x0 Reserved 17 16 Reserved 00 P_FUNC 15 12 Constant used in alphaA Same as above refer the COEF_Q 0x0 Reserved 11 10 Reserved 00 B_FUNC 9 6 Constant used in B Same as above refer the COEF_Q 0x3 Reserved 5 4 Reserved 00 A_FUNC 3 0 Constant used in A Same as above refer the COEF_Q 0x2 NOTE Refer to Figure 5 Blending equation background Window 0123 foreground Window 4 in Blend Equation 4 alphaA al...

Page 1107: ...ddress 0xEE00_ 02AC I80IFCONx Bit Description Reset Value LDI_CMD 23 0 LDI command 0 6 78 WIN0 PALETTE RAM ACCESS ADDRESS NOT SFR Register Address R W Description Reset Value 00 0xEE00_2400 0xEE00_0400 R W Window 0 Palette entry 0 address undefined 01 0xEE00_2404 0xEE00_0404 R W Window 0 Palette entry 1 address undefined FF 0xEE00_27FC 0xEE00_07FC R W Window 0 Palette entry 255 address undefined 6...

Page 1108: ...PALETTE RAM ACCESS ADDRESS NOT SFR Register Offset R W Description Reset Value 00 0xEE00_3000 R W Window 3 Palette entry 0 address undefined 01 0xEE00_3004 R W Window 3 Palette entry 1 address undefined FF 0xEE00_33FC R W Window 3 Palette entry 255 address undefined 6 82 WIN4 PALETTE RAM ACCESS ADDRESS NOT SFR Register Offset R W Description Reset Value 00 0xEE00_3400 R W Window 4 Palette entry 0 ...

Page 1109: ...ed as follows 2 FEATURES The features of image rotator include y Image format YCbCr 4 2 2 interleave YCbCr 4 2 0 non interleave RGB565 and RGB888 unpacked y Rotate degree 90 180 and 270 flip vertical and flip horizontal y Image size 64K by 64K 3 BLOCK DIAGRAM The Figure 9 2 1 shows the block diagram of Image Rotator Slave Bus Interface Master Bus Interface Register Bank Rotate FSM Roate Buffer Sys...

Page 1110: ...IMAGE ROTATOR S5PC100 USER S MANUAL REV1 0 9 2 2 3 1 ORIGINAL IMAGE 3 2 FLIP VERTICAL 3 3 FLIP HORIZONTAL ...

Page 1111: ...S5PC100 USER S MANUAL REV1 0 IMAGE ROTATOR 9 2 3 3 4 180 DEGREE ROTATION ...

Page 1112: ...IMAGE ROTATOR S5PC100 USER S MANUAL REV1 0 9 2 4 3 5 90 AND 270 DEGREE ROTATION ...

Page 1113: ... 4 1ROTATOR CONTROL REGISTER CTRLREG R W ADDRESS 0XEE10_0000 CTRLREG Bit Description Reset Value Reserved 31 25 Reserved 000_0000b Enable Int 24 Interrupt Enable 0 Disables interrupt 1 Enables interrupt 0b Reserved 23 16 Reserved 0x00 Input Image format 15 13 Input image format to be rotated 000 YCbCr 4 2 0 non interleave 001 Reserved 010 Reserved 011 YCbCr 4 2 2 interleave 100 RGB 565 101 RGB888 ...

Page 1114: ... Bit Description Reset Value Source Address 31 0 Address of source image 0x0000_0000 4 5ROTATOR SOURCE IMAGE SIZE REGISTER SRCSIZEREG R W ADDRESS 0XEE10_0010 SRCSIZEREG Bit Description Reset Value Vertical Size 31 16 Vertical Image size of source image 0x0000 Horizontal Size 15 0 Horizontal Image size of source image 0x0000 4 6ROTATOR DESTINATION IMAGE ADDRESS REGISTER 0 RGB OR Y COMPONENT CONFIGR...

Page 1115: ...002C STATREG Bit Description Reset Value Current line number 31 16 Indicates from where rotator accesses image This value shows the line number of image handled 0 Reserved 15 9 Reserved 0x00 Interrupt Pending 8 This bit is set if an image rotation is complete Writing 1 makes this bit clear 0 Reserved 7 1 Reserved 0x00 Rotator status 0 This bits show the rotator operation status 00 No work in progr...

Page 1116: ...s as HREF and VSYNC Capture is the capturing signal and window cut Use register setting to invert Video sync signals and pixel clock polarity in the camera interface side Scaler generates various sizes for useful image Input DMA read only reads from the memory image data Output DMA write only writes image data to memory CAMIF has image rotator 90 clockwise and image effect These features are very ...

Page 1117: ... end of the Chapter Max Size Item CAMIF0 CAMIF1 CAMIF2 Scaler input Hsize PreDstWidth 3264 pixels 1280 pixels 1440 pixels Scaler Scaler bypass mode 8192 pixels 8192 pixels 8192 pixels TargetHsize without output rotation 3264 pixels 1280 pixels NA Output Rotator TargetHsize with output rotation 1280 pixels 768 pixels NA REAL_WIDTH without input rotation 8192 pixels 8192 pixels NA Input Rotator REAL...

Page 1118: ...S5PC100 USER S MANUAL REV1 0 CAMERA INTERFACE 9 3 3 Figure 9 3 2 Camera Interface Overview ...

Page 1119: ...essor A XciRESET Muxed CAM_A_FIELD O FIELD signal driven by the external Camera processor A XciFIELD Muxed CAM_A_CLKOUT O Clock for a external ISP XciCLKenb Muxed External video player interface signal CAM_B_D 7 0 I Pixel Data driven by the external Camera processor B XEINT 23 16 Muxed CAM_B_PCLK I Pixel Clock driven by the external Camera processor B XEINT 24 Muxed CAM_B_VSYNC I Frame Sync driven...

Page 1120: ...CLK DATA 7 0 Vertical lines Horizontal width 1 frame 8 bit mode Figure 9 3 3 ITU R BT 601 Input Timing Diagram ITU 601 VSYNC FIELD Field 1 Field 2 VSYNC HSYNC Field 1 Field 2 Delay cycle FieldMode 1 Field port connects with FIELD FieldMode 0 Field port connects with HSYNC Figure 9 3 4 ITU R BT 601 Interlace Handling Diagram ...

Page 1121: ...ference Codes of ITU 656 8Bit Format Data bit number First word Second word Third word Fourth word 7 MSB 1 0 0 1 6 1 0 0 F 5 1 0 0 V 4 1 0 0 H 3 1 0 0 P3 2 1 0 0 P2 1 1 0 0 P1 0 1 0 0 P0 NOTE F 0 during field 1 1 during field 2 V 0 elsewhere 1 during field blanking H 0 in SAV Start of Active Video 1 in EAV End of Active Video P0 P1 P2 P3 protection bit Camera interface logic catches the video sync...

Page 1122: ... Sync Signal Timing Requirement Minimum Maximum t1 12 cycles of Pixel clock t2 12 cycles of Pixel clock t3 2 cycles of Pixel clock t4 12 cycles of Pixel clock NOTE If rotator is enabled t4 t1 must be long enough to finish DMA transactions It is because DMA transaction for rotator line buffer are delayed by 4 or 8 horizontal lines ...

Page 1123: ... CONNECTION GUIDE All Camera Interface input signals must not occur inter skewing to pixel clock line Recommend next pin location and routing Chip IO CAMCLK CAMRST VSYNC_A HREF_A PCLK_A DATA 7 0 Camera CAMIF No Skew No Skew No Skew Figure 9 3 7 IO Connection Guide ...

Page 1124: ...DMA port read the image data from memory The Output DMA port stores the image data into memory These two master ports support the variable applications like Digital Steel Camera DSC MPEG 4 video conference video recording etc CAMIF Input DMA port OutputDMA port Frame Memory YCbCr4 2 0 YCbCr4 2 2 RGB16 18 24bit YCbCr4 2 0 YCbCr4 2 2 RGB16 18 24bit Frame Memory Figure 9 3 8 Two DMA Ports ...

Page 1125: ...uld be floated It is not necessary for three clock domains to be synchronized Other signals as PCLK should be similarly connected to Schmitt triggered level shifter CAM_MCLK External Camera Processor XciPCLK CAMIF MPLL or APLL APLL MPLL EPLL HPLL BUS clock External MCLK Normally use Core clock Schmit triggered Level shifter Variable Freq Divide Counter 1 1 1 2 1 3 1 16 Variable Freq Divide Counter...

Page 1126: ...cluding CAMIF must be higher than others If bus is traffic enough that DMA operation is not ending during one horizontal period plus blank it might mal function Therefore the priority of CAMIF must be separated to other round robin or circular arbitration priorities It is recommended that bus which includes CAMIF should have higher priority than any other buses in memory matrix system The CAMIF sh...

Page 1127: ... Y7 Y6 Y5 Y4 Y3 Y2 Y1 Cb8 Cb7 Cb6 Cb5 Cb4 Cb3 Cb2 Cb1 Little endian method Cr8 Cr7 Cr6 Cr5 Cr4 Cr3 Cr2 Cr1 Little endian method RGB frame memory 24 18 bit RGB1 RGB2 RGB3 RGB4 RGB5 RGB6 RGB7 RGB8 RGB frame memory 16 bit 2 64 bit 1 R 5 G 6 B 5 16 bit YCbCr 4 2 2 1plane frame memory Cr2 Y4 Cb2 Y3 Cr1 Y2 Cb1 Y1 Little endian method CbCr frame memory Cr4 Cb4 Cr3 Cb3 Cr2 Cb2 Cr1 Cb1 Little endian method...

Page 1128: ... that except first SFR setting all command should be programmed in Interrupt Service Routine ISR Size image mirror or rotation windowing and Zoom In settings are allowed to change in capturing operation In case od DMA input mode all command should be programmed after InputDMA and OutputDMA operation end VVALID HVALID INTERRUPT SFR setting ImgCptEr Multi frame capturing Reserved Image Capture Frame...

Page 1129: ...input Read Memory SFR setting Image Capture Enable SEL_DMA_CAM SFR setting SEL_DMA_CAM New command valid timing diagram for DMA input SFR setting ENVID Image Capture Read Memory data New command SFR setting New command OuputDMA end InputDMA end Read start In capturing Figure 9 3 12 Timing Diagram for Register Setting ...

Page 1130: ...e is aware of starting point by user s SFR setting ENVID_M 0 1 Therefore this mode does not need IRQ of starting point and LastIRQ FrameCnt is increased by 1 at ENVID_M InputDMA start low to rising 0 1 and ImgCptEn_SC 1 ISR region ISR region ISR region VSYNC ISR region ImgCptEn cmd LastIRQEn Capture O Capture O Capture O Capture X IRQ Last IRQ High ISR region ISR region ISR region FrameCnt 0 1 2 3...

Page 1131: ...rame_2 Frame_3 Capture O Frame_1 ImgCptEn_SC FrameCnt Figure 9 3 15 Timing Diagram for IRQ Input DMA Path 7 8 INPUT DMA FEATURE Input DMA supports memory data scaling Especially two different image data is required for Picture in Picture PIP operation First image is saved memory by some codec H 264 Camera MPEG4 etc Second image is saved memory through input DMA path The input DMA path has YCbCr RG...

Page 1132: ...sive mode all the input data is stored in four buffers Ping pong memory which is designated by SFR sequentially by the unit of frame For more information refer to Figure 9 3 14 7 9 2 Interlaced Input In interlace mode the input data is stored in four buffers Ping pong memory which is designated by SFR In this mode even field frame data and odd field frame data are stored in turn Therefore even fie...

Page 1133: ...CAMERA CAMERA CAMERA FIMC FIMC FIMC FIMC Frame mem 1st Frame mem 2nd Frame mem 3rd Frame mem 4st Through Through Through Through DMA DMA DMA DMA pingpong pingpong pingpong 4st frame Odd field 3rd frame Even field 2nd frame Odd field 1st frame Even field Even line Even Odd line Odd Even line Even Odd line Odd Figure 9 3 17 Frame Buffer Control ...

Page 1134: ... address for output DMA 0x0000_0000 CIOCRSA1n 0x38 R W Cr 1st frame start address for output DMA 0x0000_0000 CIOCRSA2n 0x3c R W Cr 2nd frame start address for output DMA 0x0000_0000 CIOCRSA3n 0x40 R W Cr 3rd frame start address for output DMA 0x0000_0000 CIOCRSA4n 0x44 R W Cr 4th frame start address for output DMA 0x0000_0000 CITRGFMTn 0x48 R W Target image format 0x0000_0000 CIOCTRLn 0x4c R W Out...

Page 1135: ..._0000 ORGISIZEn 0x180 R W Input DMA original image size 0x0000_0000 ORGOSIZEn 0x184 R W Output DMA original image size 0x0000_0000 CIEXTENn 0x188 R W Real Output DMA image size 0x0000_0000 CIDMAPARAMn 0x18c R W DMA Parameter register 0x0000_0000 CSIIMGFMTn 0x194 R W MIPI CSI image format register 0x0000_001E NOTE The last L column means that SFR can change at vsync edge during camera capturing O p...

Page 1136: ... 30 Cb Cr value offset control 1 Cb Cb 128 Cr Cr 128 0 0 normally used 0 X X Reserved 29 Should be 0 0 X X SrcHsize_CAM 28 16 Source horizontal pixel number 16 s multiple Must be 4 s multiple of PreHorRatio if WinOfsEn is 0 Refer to the gathering extension register SrcHsize_CAM_ext 0 X O Order422_CA M 15 14 Camera Input YCbCr order inform for 8 bit mode 8 bit mode Data Flow 00 Y0Cb0Y1Cr0 01 Y0Cr0Y...

Page 1137: ... offset 0 X O ClrOvFiY 30 1 Clears the overflow indication flag of input FIFO Y 0 Normal 0 X X ClrOvRLB 29 Clears the overflow indication flag of Line Buffer for Rotation 0 X X Reserved 28 27 Reserved 0 X X WinHorOfst 26 16 Window horizontal offset by pixel unit It should be 2 s multiple Caution SourceHsize WinHorOfst WinHorOfst2 should be 16 s multiple Refer to the gathering extension register Wi...

Page 1138: ...y at first SFR setting Next sequence is recommended ITU601 case ITU601_656n 1 SwRst 1 SwRst 0 for first SFR setting ITU656 case ITU601_656n 1 SwRst 1 SwRst 0 ITU601_656n 0 for first SFR setting 0 X X CamRst_A 30 External camera processor A Reset or Power Down control 0 X X SelCam_ITU 29 External multiple ITU camera select 1 ITU Camera A select 0 ITU Camera B select 1 X X TestPattern 28 27 This reg...

Page 1139: ...18 17 Reserved 0 X X IRQ_Enable 16 1 Enables Interrupt default 0 Disables Interrupt 1 X X Reserved 15 8 Reserved 0 X X Reserved 7 Should be 1 1 Reserved 6 5 Reserved 0 X X InvPolHSYNC 4 1 Inverse the polarity of HSYNC this bit is useful only delay count interlace mode and FIELD port is connected HSYNC 0 Normal 0 X X SelCam_CAMIF 3 External camera select 1 Selects MIPI Camera 0 Selects ITU Camera 0...

Page 1140: ...et Register 2 CIWDOFST2n y CIWDOFST20 R W Address 0xEE20_0014 y CIWDOFST21 R W Address 0xEE30_0014 y CIWDOFST22 R W Address 0xEE40_0014 CIWDOFST2n Bit Description Reset Value M L Reserved 31 28 Reserved 0 X X WinHorOfst2 27 16 Window horizontal offset2 by pixel unit It should be 2 s multiple Caution Camera SourceHsize WinHorOfst WinHorOfst2 should be 16 s multiple and minimum 16 0 X O Reserved 15 ...

Page 1141: ... R W Address 0xEE20_001C y CIOYSA21 R W Address 0xEE30_001C y CIOYSA22 R W Address 0xEE40_001C CIOYSA2n Bit Description Reset Value M L CIOYSA2 31 0 Output format YCbCr 2 3 plane Y 2nd frame start address Output format YCbCr 1 plane YCbCr 2nd frame start address Output format RGB RGB 2nd frame start address 0 O X 8 7 Output DMA Y3 Start Address Register CIOYSA3n y CIOYSA30 R W Address 0xEE20_0020 ...

Page 1142: ...Start Address Register CIOCBSA1n y CIOCBSA10 R W Address 0xEE20_0028 y CIOCBSA11 R W Address 0xEE30_0028 y CIOCBSA12 R W Address 0xEE40_0028 CIOCBSA1n Bit Description Reset Value M L CIOCBSA1 31 0 Output format YCbCr 3 plane Cb 1st frame start address Output format YCbCr 2 plane CbCr 1st frame start address 0 O X 8 10 Output DMA Cb2 Start Address Register CIOCBSA2n y CIOCBSA20 R W Address 0xEE20_0...

Page 1143: ... DMA Cb4 Start Address Register CIOCBSA4n y CIOCBSA40 R W Address 0xEE20_0034 y CIOCBSA41 R W Address 0xEE30_0034 y CIOCBSA42 R W Address 0xEE40_0034 CIOCBSA4n Bit Description Reset Value M L CIOCBSA4 31 0 Output format YCbCr 3 plane Cb 4th frame start address Output format YCbCr 2 plane CbCr 4th frame start address 0 O X 8 13 Output DMA Cr1 Start Address Register CIOCRSA1n y CIOCRSA10 R W Address...

Page 1144: ... DMA Cr3 Start Address Register CIOCRSA3n y CIOCRSA30 R W Address 0xEE20_0040 y CIOCRSA31 R W Address 0xEE30_0040 y CIOCRSA32 R W Address 0xEE40_0040 CIOCRSA3n Bit Description Reset Value M L CIOCRSA3 31 0 Output format YCbCr 3 plane Cr 3rd frame start address 0 O X 8 16 Output DMA Cr4 Start Address Register CIOCRSA4n y CIOCRSA40 R W Address 0xEE20_0044 y CIOCRSA41 R W Address 0xEE30_0044 y CIOCRS...

Page 1145: ... CITRGFMT1 R W Address 0xEE30_0048 y CITRGFMT2 R W Address 0xEE40_0048 Original image 0 0 0 Rot90 FlipMd 0 MSB LSB X axis flip 0 0 1 Y axis flip 0 1 0 0 1 1 90 clockwise 1 0 0 90 X axis flip 1 0 1 90 Y axis flip 1 1 0 90 XY axis flip 270 clockwise XY axis flip 180 clockwise FlipMd 1 1 1 1 Figure 9 3 20 Image Mirror and Rotation ...

Page 1146: ...output DMA 00 Normal 01 X axis mirror 10 Y axis mirror 11 180 rotation 0 O O OutRot90 13 1 Rotate clockwise 90 Using the Output Rotator 0 Output Rotator bypass 0 O O TargetVsize 12 0 Vertical pixel number of target image Minimum number is 4 Refer to gathering extension register TargetVsize_ext 0 O O TargetHsize and TargetVsize should not be larger than Camera SourceHsize and Camera SourceVsize Inp...

Page 1147: ...23 4 Reserved 0 X X C_INT_OUT 3 1 YCbCr 4 2 0 or 4 2 2 2plane output format 0 YCbCr 4 2 0 or 4 2 2 3plane output format 0 O O LastIRQEn 2 1 enable last IRQ at the end of frame capture It is recommended to check the done signal of capturing image for JPEG 0 normal 0 X X Order422_out 1 0 YCbCr 4 2 2 1plane output memory storing style order bit MSB LSB 00 Cr1Y3Cb1Y2Cr0Y1Cb0Y0 01 Cb1Y3Cr1Y2Cb0Y1Cr0Y0 ...

Page 1148: ...RC_Width SourceHsize WinHorOfst WinHorOfst2 SRC_Height SourceVsize WinVerOfst WinVerOfst2 DST_Width TargetHsize DST_Height TargetVsize SRC_Width SourceHsize SRC_Height SourceVsize Figure 9 3 22 Scaling Scheme The other control registers of pre scaled image size pre scale ratio pre scale shift ratio and main scale ratio are defined according to the following equations If SRC_Width 64 DST_Width Exit...

Page 1149: ..._Shift 0 PreDstHeight SRC_Height PreVerRatio MainVerRatio SRC_Height 8 DST_Height V_Shift SHfactor 10 H_Shift V_Shift Caution In Zoom In case you should check the next equation CAM In case SourceHsize WinHorOfst WinHorOfst2 PreHorRatio Max scaler line buffer size width 8 19 Pre Scaler Control Register 1 CISCPRERATIOn y CISCPRERATIO0 R W Address 0xEE20_0050 y CISCPRERATIO1 R W Address 0xEE30_0050 y...

Page 1150: ... be 1 Generally this mode uses large image size upper scaler maximum size This mode is intended to capture JPEG input image for DSC application In this case input pixel buffering depends on only input FIFOs therefore system bus should not be busy in this mode ScalerBypass has some restriction Size scaling color space conversion Input DMA mode and any RGB format are not allowed If input format is Y...

Page 1151: ... 0 O X MainHorRatio 24 16 Horizontal scale ratio for main scaler 0 O O ScalerStart 15 Scaler start 1 Scaler start 0 Scaler stop or scaler bypass 0 O O InRGB_FMT 14 13 Input DMA RGB format 00 RGB565 01 RGB666 10 RGB888 11 Reserved 0 O X OutRGB_FMT 12 11 Output DMA RGB format 00 RGB565 01 RGB666 10 RGB888 11 Reserved 0 O O Ext_RGB 10 Input RGB data extension enable bit for the conversion of RGB565 6...

Page 1152: ...ion Normal mode DMA Input DMA Output Source image format is one of YCbCr420 YCbCr422 and RGB16 18 24 bit format Destination image format is one of YCbCr420 YCbCr422 and RGB 16 18 24 bit format All source and destination image data need to be stored in memory system aligned with double word boundary Supports DMA operation Therefore the width of source and destination image should be selected to sat...

Page 1153: ...r Register Files Lists The interlace control bit is available if LCDPathEn 1 otherwise its value is unaffected to DMA mode operation which support only progressive Even if an interlaced scan mode is enable LCDPathEn 1 and Interlace 1 per frame management which consists of even field and odd filed is automic This means that user interruption is unnecessary to inter field switching in the same frame...

Page 1154: ... 9 3 23 I O Timing Diagram for Direct Path Video Graphic 1 Frame Video Graphic 1 Frame FIMC CAMIF Display Controller FIFO Video Graphic DMA FIFO FIFO Full Data Valid Progressive AXI Bus Memory Memory Camera Progressive Figure 9 3 24 Input Output Modes in CAMIF ...

Page 1155: ...t Area Register CITAREAn y CITAREA0 R W Address 0xEE20_005C y CITAREA1 R W Address 0xEE30_005C y CITAREA2 R W Address 0xEE40_005C CITAREAn Bit Description Reset Value M L Reserved 31 28 Reserved 0 X X CITAREA 27 0 Target area for output DMA Target H size x Target V size 0 O O ...

Page 1156: ...f scaler path R 0 X X VSYNC_A 20 External camera A VSYNC Polarity inversion was not adopted R X X X VSYNC_B 19 External camera B VSYNC Polarity inversion was not adopted R X X X OvRLB 18 Overflow status of Line Buffer for Rotation R 0 X X FrameEnd 17 When frame operation finish FrameEnd is generated and FrameEnd is clear by user setting 0 R W 0 X X LastCaptureEnd 16 Last frame capture status LastC...

Page 1157: ...rame control mode 1 Apply Cpt_FrCnt mode capture Cpt_FrCnt frames along the Cpt_FrSeq after capture dma frame control becomes enable If Cpt_FrCnt 0 then no more capture 0 Apply Cpt_FrEn mode capture frames along the Cpt_FrSeq during Cpt_FrEn is high This sequence repeats until capture frame control disables 0 X X Cpt_ FrCnt 17 10 Wanted number of frames to be captured If register read you will see...

Page 1158: ...AMERA INTERFACE 9 3 43 1 1 0 1 0 1 Cpt _ FrPtr 3 1 3 0 2 9 1 0 Cpt _ DMA _ Seq 31 0 Repeat Capture No Capture Capture Capture Figure 9 3 25 Capture Frame Control For skipped frames IRQ is not generated and FrameCnt is not increased ...

Page 1159: ...u camera image should be applied In case of Before scaling it applies image effect even though it is in scalar bypass mode 0 O O FIN 28 26 Image Effect selection 3 d0 Bypass 3 d1 Arbitrary Cb Cr 3 d2 Negative 3 d3 Art Freeze 3 d4 Embossing 3 d5 Silhouette 0 O O Reserved 25 21 Reserved 0 X X PAT_Cb 20 13 It is used only for FIN is Arbitrary Cb Cr PAT_Cb Cr 8 d128 for GRAYSCALE Wide CSC Range 0 PAT_...

Page 1160: ...it Description Reset Value M L CIIYSA0 31 0 Input format YCbCr 2 3 plane Y frame start address Input format YCbCr 1 plane YCbCr frame start address Input format RGB RGB frame start address 0 O X 8 28 Input DMA Cb0 Start Register y CIICBSA00 R W Address 0xEE20_00D8 y CIICBSA01 R W Address 0xEE30_00D8 y CIICBSA02 R W Address 0xEE40_00D8 CIICBSA0n Bit Description Reset Value M L CIICBSA0 31 0 Input f...

Page 1161: ...t the first frame start it requires ENVID_M start setting After first frame next frame does not need ENVID_M setting If autoload function is running size format value should be fixed 0 Disables AutoLoad 1 Enables AutoLoad 0 O X ADDR_CH_DIS 30 Input DMA Address Change Disable Only Software trigger mode At the first frame start needs ADDR_CH_DIS 0 0 Address change enable 1 Address change disable 0 O...

Page 1162: ...1 Reserved 10 Reserved 11 Reserved R W 0 O X C_INT_IN 15 1 YCbCr 4 2 0 or 4 2 2 2plane input format 0 YCbCr 4 2 0 or 4 2 2 3plane input format R W 0 O X InFlipMd 14 13 Image mirror and rotation for Input DMA 00 Normal 01 X axis mirror 10 Y axis mirror 11 180 rotation XY axis mirror R W 0 O X Reserved 12 7 Reserved 0 X X EOF_M 6 If Input DMA operation is complete it generates End Of Frame read only...

Page 1163: ...ENVID_M 0 Input DMA operation start Software setting triggers Low to High Hardware clears automatically 1 SEL_DMA_CAM 0 ENVID_M don t care using external camera signal 2 SEL_DMA_CAM 1 ENVID_M is set 0 1 then Input DMA operation start R W 0 O X NOTE ENVID_M SFR must be set at last Starting order for using DMA input path SEL_DMA_CAM others SFR setting Image Capture Enable Scaler start SFR setting EN...

Page 1164: ... 1 setting MODE DMA input FIFO progressive output ENVID_M Next Frame start Frame start 0 1 setting Auto Clear Frame end 0 1 setting MODE DMA input FIFO interlace output Auto Clear Even field end Auto Start Odd field start ENVID_M Next frame start Frame start 0 1 setting Auto Clear Frame end Auto Start if autoload enable 1 MODE DMA input AutoLoad enable mode Figure 9 3 27 ENVID_M SFR Setting When I...

Page 1165: ...on Done IRQ signal generation SFR SFR RGB start address Target format OutDMA Control etc Figure 9 3 28 SFR Operation Related Each DMA When Selected Input DMA Path ENVID_M ADDR_CH_DIS Start End ADDRESS 0 user setting A 0 F A F Start End ADDRESS for real operation 0 A F Frame start Frame start address change Frame start address change Figure 9 3 29 Address Change Timing Related Input DMA ...

Page 1166: ...tal offset for Y component Output format YCbCr 2 3 plane Y width offset Output format YCbCr 1 plane YCbCr width offset Output format RGB RGB width offset 0 O O 8 33 Output DMA Cb Offset Register CIOCBOFFn y CIOCBOFF0 R W Address 0xEE20_016C y CIOCBOFF1 R W Address 0xEE30_016C y CIOCBOFF2 R W Address 0xEE40_016C CIOCBOFFn Bit Description Reset Value M L Reserved 31 Reserved 0 X X OCBOFF_V 30 16 Out...

Page 1167: ...tput format YCbCr 3 plane Cr width offset 0 O O 8 35 Input DMA Y Offset Register CIIYOFFn y CIIYOFF0 R W Address 0xEE20_0174 y CIIYOFF1 R W Address 0xEE30_0174 y CIIYOFF2 R W Address 0xEE40_0174 CIIYOFFn Bit Description Reset Value M L Reserved 31 Reserved 0 X X IYOFF_V 30 16 Input DMA vertical offset for Y component Input format YCbCr 2 3 plane Y height offset Input format YCbCr 1 plane YCbCr hei...

Page 1168: ...ved 15 Reserved 0 X X ICBOFF_H 14 0 Input DMA horizontal offset for Cb component Input format YCbCr 3 plane Cb width offset Input format YCbCr 2 plane CbCr width offset 0 O X 8 37 Input DMA Cr Offset Register CIICROFFn y CIICRFF0 R W Address 0xEE20_017C y CIICRFF1 R W Address 0xEE30_017C y CIICRFF2 R W Address 0xEE40_017C CIICROFFn Bit Description Reset Value M L Reserved 31 Reserved 0 X X ICROFF_...

Page 1169: ... Original image height ORG_OUT_V Original image width ORG_OUT_H Real Image width TargetH size Figure 9 3 31 Output DMA Offset Image Size DMA Start Address Start address of ADDRStart_Y Cb Cr RGB points the first address where the corresponding component of Y Cb Cr RGB is read or written Each one should be aligned with double word boundary i e ADDRStart_X 2 0 3 b000 ADDRStart_Cb is valid only for th...

Page 1170: ...ntal offset ByteSize_Per_Pixel Cf ByteSize_Per_Pixel 1 2 for YCbCr420 3plane YCbCr422 3plane 1 for YCbCr420 2plane YCbCr422 2plane y Offset_H_ Cr Memory size for Cr offset per a horizontal line 8 s multiple Number of pixel or sample in horizontal offset ByteSize_Per_Pixel Cf ByteSize_Per_Pixel 1 2 for YCbCr420 3plane YCbCr422 3plane y Offset_V_Y Number of vertical Y offset y Offset_V_Cb Number of ...

Page 1171: ...t be less than REAL_WIDTH register 0 O X 8 39 Original Output DMA Image Size ORGOSIZEn y ORGOSIZE0 R W Address 0xEE20_0184 y ORGOSIZE1 R W Address 0xEE30_0184 y ORGOSIZE2 R W Address 0xEE40_0184 ORGOSIZEn Bit Description Reset Value M L Reserved 31 30 Reserved 0 X X ORG_OUT_V 29 16 Output DMA original image vertical pixel size Minimum 8 This size should not be less than TargetVsize register If out...

Page 1172: ...t_ext WinHorOfst 11 10 0 Thus total window horizontal offset size 11 0 0 O O Reserved 27 Reserved TargetHsize_ext 26 Bit value 13 of the target image horizontal pixel number register TargetHsize_ext TargetHsize 13 12 0 Thus total target image horizontal size 13 0 0 O O Reserved 25 Reserved 0 X X TargetVsize_ext 24 Bit value 13 of the target image vertical number register TargetVsize_ext TargetVsiz...

Page 1173: ...NPUT DMA address access style 0 Linear 1 Reserved 2 Reserved 3 64x32 tile 0 O X Reserved 28 15 Reserved 0 X X MODE_W 14 13 OUTPUT DMA address access style 0 Linear 1 Reserved 2 Reserved 3 64x32 tile 0 X X Reserved 12 4 Reserved 0 X X Reserved 3 0 Reserved 0 X X NOTE see 4 1 Tiled memory format in chapter 9 1 for the tile mode description ...

Page 1174: ...e 0x1E YUV422 8 bit 0x2A RAW8 0x2B RAW10 0x2C RAW12 0x1E X X NOTE FRAME END ADDRESS calculation method useful only TILE 64x32 access mode Example Image pixel size 720p 1280 x 720 Format YCbCr4 2 0 2plane NV12 hor_img_size width 1280byte ver_img_size height 720 if hor_img_size 16 0 hor_img_offset 0 else hor_img_offset 16 hor_img_size 16 if ver_img_size 16 0 ver_img_offset 0 elsever_img_offset 16 ve...

Page 1175: ..._y_minus 14 6 roundup_x pixel_x_minus 14 8 1 11 10 4 1 115 else pic_range roundup_x roundup_y 2 Chroma case pixel_x_minus pixel_x 1 1279 pixel_y_minus pixel_y 1 359 101100111 binary roundup_x INT INT pixel_x 1 16 8 1 10 roundup_y INT INT pixel_y 1 16 4 1 6 if pixel_y_minus 5 0 pixel_y_minus 5 0 b 100111 pixel_y_minus 5 1 pic_range pixel_y_minus 14 6 roundup_x pixel_x_minus 14 8 1 else pic_range ro...

Page 1176: ...ure 9 4 1 It has control registers inside It is possible to set the operation modes and conditions such as the Huffman table number and restart interval value into these registers 2 FEATURES Compression decompression up to 7168x7168 Supports following format of compression Refer to Table 9 4 1 Input raw image YCbCr4 2 2 or RGB565 Output JPEG file Baseline JPEG of YCbCr4 2 2 or YCbCr4 2 0 Supports ...

Page 1177: ...t YCbCr4 2 2 1 plane MSB LSB Cr0 Y1 Cb0 Y0 RGB565 1 plane R1 G1 B1 R0 G0 B0 Encoding Output Color Format YCbCr4 2 2 YCbCr4 2 0 Input Color Format YCbCr4 4 4 YCbCr4 2 2 YCbCr4 2 0 gray Decoding Output Color Format YCbCr4 2 2 1plane Cr Y1 Cb Y0 YCbCr4 2 0 2plane Y3 Y2 Y1 Y0 Cr1 Cb1 Cr0 Cb0 ...

Page 1178: ...ed over DCT coefficients by utilizing the quantization tables During decompression dequantization is done and then DCT coefficients is transformed into image data 3 3 HUFFMAN CODER AND MARKER PROCESS During compression Huffman encoding is done according to the Huffman table and marker process makes the JPEG bitstream During decompression marker process parses a JPEG file and Huffman decoding is do...

Page 1179: ... USER S MANUAL REV1 0 9 4 4 3 7JPEG HALF CLOCK JPEG has a half clock To select this write 1 or 0 on JPEG Color Mode Register 0 bit HALF_EN 0 Refer to JPEG Color Mode Register on Page 16 Figure 9 4 2 JPEG Half Clock ...

Page 1180: ... decompression mode input file is baseline JPEG in YCbCr4 4 4 YCbCr4 2 2 YCbCr4 2 0 gray with interleaved scan and output raw image has interleaved YCbCr4 2 2 or YCbCr4 2 0 formats Therefore for input file with YCbCr format decimation and interpolation process is done during decompression In this case decimation is same as downsampling and interpolation is sample and hold repetition of recent valu...

Page 1181: ...JPEG S5PC100 USER S MANUAL REV1 0 9 4 6 Figure 9 4 5 YCbCr4 2 2 Color Format ...

Page 1182: ... must be accessed first Then write transfers should follow To understand the write transfer refer to Figure 9 4 6 The access order for each table is shown below 3 4 1 2 7 8 5 6 11 12 9 10 15 16 13 14 19 20 17 18 23 24 21 22 27 28 25 26 31 32 29 30 35 36 33 34 39 40 37 38 43 44 41 42 47 48 45 46 51 52 49 50 55 56 53 54 59 60 57 58 63 64 61 62 Figure 9 4 6 Access Order in Quantizer Table 5 3 STARTIN...

Page 1183: ... HACTBLG1 AC Huffman Table1 Entry Register Essential Contents of registers in Table 5 changes in following cases 1 After the registers are written again by user 2 After reset operation is done 3 After decompression of arbitrary JPEG file In this case the registers have the value from header of input JPEG file after header parsing process Except these cases it is possible to process next picture by...

Page 1184: ...ing process The modified size is the minimum values which are the multiple of the block size and larger than or equal to the original value However register setting value of width and height for compression must be the original value 5 5 PROCESS FOR INPUT STREAM SIZE In case of decompression of an illegal JPEG stream JPEG IP does not recognize the end of the stream if some important markers are da...

Page 1185: ...es whether the interrupt is allowed or not after header parsing and for illegal input file for decompression To allow interrupt request after header analysis during decompression set HEAD_INT_EN to 1 before start the decompression process If this interrupt occurs JPEG pauses the decompression process During the pause JPGOPR has value 1 because the process is not complete To deal with an illegal in...

Page 1186: ...opy coded segment which is a sequence of entropy coded bytes SOI DQT DRI SOF0 DHT SOS ECS EOI Figure 9 4 7 Bitstream of Compressed File 5 11 JPEG COMPRESSION FLOW This is a pseudo instruction set that indicates the write or read on specific registers It is assumed that the Huffman and quantization tables were written already JPEG encoder initialization Write JPGCMOD 0x21 Mode selection and core cl...

Page 1187: ...EG decoder initialization Write JPGCMOD 0x21 Core clock setting Write JPGMOD 0x8 Decoding mode Write JPGINTSE 0x78 Enable interrupt after header analysis and for illegal stream Write OUTFORM 0x1 Output raw image is YCbCr4 2 0 Write IMGADR 0x1000_0000 Address for a decompressed raw image Write JPGADR 0x1001_0000 Address for a JPEG file to decompress Write DEC_STREAM_SIZE 0x0000_1000 Byte size of in...

Page 1188: ...00_0000 JPGINTSE 0xEE50_001C R W Interrupt Setting Register 0x0000_0000 JPGINTST 0xEE50_0020 R Interrupt Status Register 0x0000_0000 Reserved 0xEE50_0024 0xEE50_004C IMGADR 0xEE50_0050 R W Source or Destination Image Address 0x0000_0000 Reserved 0xEE50_0054 JPGADR 0xEE50_0058 R W Source or Destination JPEG File Address 0x0000_0000 COEF1 0xEE50_005C R W Coefficient Values for RGB YCbCr Converter 0x...

Page 1189: ...ting Register 0x00FF_FFE0 ENC_STREAM_INTST 0xEE50_009C R W Compressed Stream Size Interrupt Status Register 0x0000_0000 6 1 JPEG Mode Register JPGMOD R W Address 0XEE50_ 0000 JPGMOD Bit Description Reset Value Reserved 31 4 Reserved 0 PROC_MODE 3 Process mode 0 Compression process 1 Decompression process 0 SUBSAMPLING_MO DE 2 0 Sub sampling mode 0x0 chroma 4 4 4 format 0x1 chroma 4 2 2 format 0x2 ...

Page 1190: ... DC 0 6 4 JPEG Restart Interval Register JPGDRI R W Address 0XEE50_ 000C JPGDRI Bit Description Reset Value Reserved 31 16 Reserved 0 JPGDRI 15 0 It is a restart interval that identifies the distance between two adjacent Restart Maker RST in terms of Minimum Coded Unit MCU It is valid in compression mode If JPGDRI is set to 0 Define Restart Interval Marker DRI and RST is not inserted 0 6 5 JPEG Ve...

Page 1191: ...pt after header analysis 1 Enables interrupt after header analysis If enabled it is possible to read the image size and sampling factor value in the result of header analysis It is recommended to Set 1 0 INT_EN 2 0 Write 0x0 to enable interrupt 0 6 9 JPEG Interrupt Status Register JPGINTST R Address 0XEE50_ 0020 JPGINTST Bit Description Reset Value Reserved 31 7 Reserved 0 RESULT_STAT 6 Result sta...

Page 1192: ...e data Value for this register has to be multiple of 32 In compression mode JPEG file after compression is stored from this address In decompression mode JPEG file before compression is read from this address 0 6 12 Coefficient for RGB TO YCBCR Converter Register COEF1 R W Address 0XEE50_ 005C COEF1 Bit Description Reset Value Reserved 31 24 Reserved 0 COEF11 23 16 Coefficient value of COEF11 0 CO...

Page 1193: ...EFxx Bit 7 6 5 4 3 2 1 0 Value 0 5 0 25 0 125 0 0625 0 03125 0 015625 0 0078125 0 00390625 6 15 JPEG Color Mode Register JPGCMOD R W Address 0XEE50_ 0068 JPGCMOD Bit Description Reset Value Reserved 31 8 Reserved 0 MOD_SEL 7 5 Color space of input raw image 0x1 YCbCr4 2 2 0x2 RGB 565 Others are reserved 1 Reserved 4 2 It must be set 0x0 0 MODE_Y16 1 Y_16 selector for Y component 0 c1 0 1 c1 16 c1 ...

Page 1194: ...cleared with 0 internally Before starting operation you must set essential registers 0 6 18 JPEG Restart Register JRSTART W Address 0XEE50_ 0074 JRSTART Bit Description Reset Value Reserved 31 1 Reserved 0 JRSTART 0 Decompression of JPEG pauses after header analysis To restart decompression from pause set this value to 1 After one clock it is cleared with 0 internally Before restarting operation t...

Page 1195: ...ng 0 has no effect 0 TIMER_CNT 30 0 Timer counting value If start or restart it is initiated by TIMER_INIT value and starts to down count If JPEG operation finishes before end of counting it holds the counter value at that time This bit is read only 0x7FFF_FFFF 6 22 JPEG Command Status Register COMSTAT R Address 0XEE50_ 0084 COMSTAT Bit Description Reset Value Reserved 31 2 Reserved 0 CUR_PROC_MOD...

Page 1196: ...E50_ 0094 DEC_STREAM_SIZE Bit Description Reset Value Reserved 31 29 Reserved 0 DEC_STREAM_SIZE 28 0 Input JPEG stream size in the number of bytes for decompression It has to be set before start of each decompression operation Set 0 or 536 870 911 0x1FFF_FFFF is prohibited 0x1FFF_FFFE 6 26 JPEG Compressed Stream Size Interrupt Setting Register ENC_STREAM_INTSE R W Address 0XEE50_ 0098 TIMER_SE Bit...

Page 1197: ...0 _04FC W Quantization of table number 0 64 data with the distance of 4 on address 0x0000 0000 for 64 each data QTBL1 0xEE50_0500 0xEE50_0504 0xEE50 _05FC W Quantization of table number 1 64 data with the distance of 4 on address 0x0000 0000 for 64 each data QTBL2 0xEE50_0600 0xEE50_0604 0xEE50_06FC W Quantization of table number 2 64 data with the distance of 4 on address 0x0000 0000 for 64 each ...

Page 1198: ...0C00 0xEE50_0C04 0xEE50_0C3C W JPEG DC Huffman Table 1 Register The number of code per code length 16 data with the distance of 4 on address HDCTBLG1 0xEE50_0C40 0xEE50_0C44 0xEE50_0C6C W JPEG DC Huffman Table 1 Register Group number of the order for occurrence 12 data with the distance of 4 on address HACTBL1 0xEE50_0C80 0xEE50_0C84 0xEE50_0CBC W JPEG AC Huffman Table 1 Register The number of cod...

Page 1199: ...JPEG S5PC100 USER S MANUAL REV1 0 9 4 24 NOTES ...

Page 1200: ...sters 2 start the rendering process by setting the relevant command registers accordingly 2 FEATURES Primitives Line Point Drawing DDA Digital Differential Analyzer algorithm Do Not Draw Last Point support BitBLT stretched BitBLT support Nearest sampling Memory to Screen Host to Screen Color Expansion Memory to Screen Host to Screen Per pixel Operation Maximum 2040 2040 image size Window Clipping ...

Page 1201: ...or data is converted to 32 bit the data of each field is shifted 8 x bits to left where x is the bit width of the field The least significant x bits of the new field data are padded with the most significant x bits of the original field data For example if the R value in RGB_565 format is 5 b11010 it is converted to 8 b11010110 with three LSBs padded with three MSBs 3 b110 from the original R valu...

Page 1202: ...ndering process completes It is user s responsibility to make sure that the data written to the FIFO do not exceed its maximum capacity User can monitor the number of data entries used in FIFO by reading FIFO_USED bits in FIFO_STAT_REG or request graphics engine to give an interrupt signal if the number of entries in FIFO reaches a certain level by setting FIFO_INTC_REG and E bit in INTEN_REG 5 RE...

Page 1203: ...1110 01000000000 Related Registers COORD_0 Coordinate of the starting point COORD_2 Coordinate of the ending point Ignored if a point is rendered X INCR X increment value Ignored if x axis is the Major Axis or a point is rendered X INCR ex sx ey sy Y INCR Y increment value Ignored if y axis is the Major Axis or a point is rendered Y INCR ey sy ex sx FG_COLOR The color of the drawn line point CMD0_...

Page 1204: ...of the source image COORD_1 Coordinates of the rightmost bottommost coordinate of the source image COORD_2 Coordinates of the leftmost topmost coordinate of the destination image COORD_3 Coordinates of the rightmost bottommost coordinate of the destination image X INCR X increment value of the source image coordinates If it is greater than 1 the image is shrunk horizontally smaller than 1 stretche...

Page 1205: ...vides the source image data through these two command registers If the host writes the first 32 bit data into CMD2_REG the rendering process starts in the host to screen mode Then the host should provide the rest of data by writing into CMD3_REG continuously The data written to CMD2_REG CMD3_REG each time represents only one pixel regardless of the source color format If the source color format is...

Page 1206: ... Color ROP_REG Enable disable Transparent Mode CMD3_REG The base address of the font data Writing to this register starts the rendering process in the memory to screen mode CMD4_REG CMD5_REG The host provides the font data through these two command registers If the host writes the first 32 bit data into CMD4_REG the rendering process starts in the host to screen mode Then the host should provide t...

Page 1207: ...allowed Related Registers CW_LT_REG Coordinates of the leftmost topmost point of the clipping window CW_RB_REG Coordinates of the rightmost bottommost point of the clipping window 5 4 STENCIL TEST The Stencil Test conditionally discards a pixel based on the outcome of a comparison between the color value of this pixel of the source image and the DR min DR max values If each field R G B A of the co...

Page 1208: ...x16 bpp image the pattern data must be in RGB565 format The following equation is used to calculate the pattern index of pixel x y index patternOffsetY y 0x7 3 patternOffsetX x 0x7 where patternOffsetY and patternOffsetX are the offset value specified in register PATOFF_REG Here are some examples on how to use the ROP value to perform the operations 1 Final Data Source Only the Source data matter ...

Page 1209: ...onal alpha value is alpha ALPHA 1 256 The internal computation of alpha blending and fading is as follows User specified alpha value ALPHA given by ALPHA_REG from 0 to 255 Alpha Blending data source ALPHA 1 destination 255 ALPHA 8 Fading data source ALPHA 1 8 fading offset Per pixel alpha blending ALPHA given by the source image from 0 to 255 Alpha Blending data source ALPHA 1 destination 255 ALPH...

Page 1210: ...or Color Expansion Host to Screen Font Continue CMD6_REG 0xEE80_0118 W Reserved CMD7_REG 0xEE80_011C W Command Register for Color Expansion Memory to Screen Parameter Setting Registers Resolution SRC_ RES_REG 0xEE80_0200 R W Source Image Resolution 0x0000_0000 SRC_HORI_RES_REG 0xEE80_0204 R W Source Image Horizontal Resolution 0x0000_0000 SRC_VERT_RES_REG 0xEE80_0208 R W Source Image Vertical Reso...

Page 1211: ...ation Origin Coordinates 0x0000_0000 ROT_OC_Y_REG 0xEE80_0348 R W Y Coordinate of Rotation Origin Coordinates 0x0000_0000 ROTATE_REG 0xEE80_034C R W Rotation Mode Register 0x0000_0001 Data Format ENDIAN 0xEE80_0350 R W Big little ENDIAN Select 0x0000_0000 X Y Increment Setting X_INCR_REG 0xEE80_0400 R W X Increment Register 0x0000_0000 Y_INCR_REG 0xEE80_0404 R W Y Increment Register 0x0000_0000 RO...

Page 1212: ...W Stencil Decision Reference MIN Register 0x0000_0000 STENCIL_DR_MAX_REG 0xEE80_0728 R W Stencil Decision Reference MAX Register 0xFFFF_FFFF Image Base Address SRC_BASE_ADDR_REG 0xEE80_0730 R W Source Image Base Address Register 0x0000_0000 DEST_BASE_ADDR_REG 0xEE80_0734 R W Dest Image Base Address Register in most cases frame buffer address 0x0000_0000 9 5 13 ...

Page 1213: ...hed interrupt enable If this bit is set when the graphics engine finishes the execution of all commands in the command FIFO an interrupt occurs and the INTP_ALL_FIN flag in INTC_PEND_REG will be set 0x0 FIFO_FULL 8 Command FIFO Full interrupt enable If this bit is set when command FIFO is full 32 entries an interrupt occurs and the INTP_FULL flag in the interrupt pending register INTC_PEND_REG wil...

Page 1214: ... 0x0 6 1 5 FIFO status Register FIFO_STAT_REG R W Address 0xEE80_ 0010 FIFO_STAT_REG Bit Description Reset Value Reserved 31 11 Reserved 0x0 CMD_FIN 10 1 The graphics engine completes the execution of current command 0 In middle of rendering process 0x1 ALL_FIN 9 1 Graphics engine is in idle state The graphics engine completes the execution of all commands in the command FIFO Note that ALL_FIN CMD...

Page 1215: ...N 0 0 Nothing 1 Normal BitBLT 6 2 3 Host to Screen Start BitBLT Register CMD2_REG W Address 0xEE80_ 0108 CMD2_REG Bit Description Reset Value Data 31 0 BitBLT data Start NOTE The data written to this register represents only one pixel regardless of the source color mode If the source color mode is 16 bpp e g RGB565 the upper 16 bits of the data are ignored 6 2 4 Host to Screen Continue BitBLT Regi...

Page 1216: ...ata Start 6 2 6 Host to Screen Continue Color Expansion Register CMD5_REG W Address 0xEE80_ 0114 CMD5_REG Bit Description Reset Value Data 31 0 Color Expansion Data Continue 6 2 7 Memory to Screen Color Expansion Register CMD7_REG W Address 0xEE80_ 011C CMD7_REG Bit Description Reset Value Memory Address 31 0 Bitmap data base address Used in memory to screen mode must be word aligned 9 5 17 ...

Page 1217: ...04 SRC_HORI_RES_REG Bit Description Reset Value Reserved 31 11 Reserved 0x0 HoriRes 10 0 Horizontal resolution of source image Range 1 2040 NOTE In YUV mode HoriRes must be an even number 0x0 6 3 3 Source Image Vertical Resolution SRC_VERT_RES_REG R W Address 0xEE80_ 0208 SRC_VERT_RES_REG Bit Description Reset Value Reserved 31 11 Reserved 0x0 VertRes 10 0 Vertical resolution of source image Range...

Page 1218: ...rved 0x0 TopCW_Y 26 16 Top Y Clipping Window Requirement TopCW_Y BottomCW_Y 0x0 Reserved 15 11 Reserved 0x0 LeftCW_X 10 0 Left X Coordinate of Clipping Window Requirement LeftCW_X RightCW_X 0x0 6 3 8 Left X Clipping Window CW_LT_X_REG R W Address 0xEE80_ 0224 CW_LT_X_REG Bit Description Reset Value Reserved 31 11 Reserved 0x0 LeftCW_X 10 0 Left X Clipping Window Requirement LeftCW_X RightCW_X 0x0 ...

Page 1219: ...ELERATOR S5PC100 USER S MANUAL REV1 0 Requirement BottomCW_Y VeriRes SC_VERI_RES_REG Reserved 15 11 Reserved 0x0 RightCW_X 10 0 Right X Clipping Window Requirement RightCW_X HoriRes SC_HORI_RES_REG 0x0 9 5 20 ...

Page 1220: ...EG R W Address 0xEE80_ 0300 COORD0_REG Bit Description Reset Value Reserved 31 27 Reserved 0x0 Y 26 16 Coordinate_0 Y Range 0 2039 0x0 Reserved 15 11 Reserved 0x0 X 10 0 Coordinate_0 X Range 0 2039 0x0 6 3 14 Coordinate_0 X Register COORD0_X_REG R W Address 0xEE80_ 0304 COORD0_X_REG Bit Description Reset Value Reserved 31 11 Reserved 0x0 COORD0_X 10 0 Coordinate_0 X Range 0 2039 0x0 6 3 15 Coordin...

Page 1221: ...Y 10 0 Coordinate_1 Y Range 0 2039 0x0 6 3 19 Coordinate_2 Register COORD2_ REG R W Address 0xEE80_ 0320 COORD2_ REG Bit Description Reset Value Reserved 31 27 Reserved 0x0 Y 26 16 Coordinate_2 Y Range 0 2039 0x0 Reserved 15 11 Reserved 0x0 X 10 0 Coordinate_2 X Range 0 2039 0x0 6 3 20 Coordinate_2 X Register COORD2_X_REG R W Address 0xEE80_ 0324 COORD2_X_REG Bit Description Reset Value Reserved 3...

Page 1222: ...3 Y Register COORD3_Y_REG R W Address 0xEE80_ 0338 COORD3_Y_REG Bit Description Reset Value Reserved 31 11 Reserved 0x0 COORD3_Y 10 0 Coordinate_3 Y Range 0 2039 0x0 6 3 25 Rotation Origin Coordinate ROT_OC_REG R W Address 0xEE80_ 0340 ROT_OC_REG Bit Description Reset Value Reserved 31 27 Reserved 0x0 Y 26 16 X coordinate of the reference point of rotation Range 0 2039 0x0 Reserved 15 11 Reserved ...

Page 1223: ...are set to 1 at the same time drawing engine operates unpredictably 6 3 29 Endian ENDIAN_REG R W Address 0xEE80_ 0350 ENDIAN_REG Bit Description Reset Value Reserved 31 2 Reserved 0x0 DEST_ENDIAN 1 Big Endian setting for dest data 1 Big Endian 0 Little Endian 0x0 SRC_ENDIAN 0 Big Endian setting for source data 1 Big Endian 0 Little Endian 0x0 6 3 30 X Increment Register X_INCR_REG R W Address 0xEE...

Page 1224: ...e set at the same time 0x0 ROP Value 7 0 Raster Operation Value 0x0 6 3 33 Alpha Register ALPHA_REG R W Address 0xEE80_ 0420 ALPHA_REG Bit Description Reset Value Reserved 31 16 Reserved 0x0 Fading 15 8 Fading Offset Value 0x0 Alpha 7 0 Alpha Value 0x0 6 3 34 Foreground Color Register FG_COLOR_REG R W Address 0xEE80_0500 FG_COLOR_REG Bit Description Reset Value ForegroundColor 31 0 Foreground Colo...

Page 1225: ...it Description Reset Value Reserved 31 5 Reserved 0x0 Narrow 4 1 YUV narrow range Y 16 235 UV 16 240 0 YUV wide range YUV 0 255 0x0 YUV 3 1 YUV mode 0 RGB mode This bit should be set to 0 in point line drawing mode and color expansion mode 0x0 Color Setting 2 0 3 b000 RGB_565 3 b001 RGBA_5551 3 b010 ARGB_1555 3 b011 RGBA_8888 3 b100 ARGB_8888 3 b101 XRGB_8888 3 b110 RGBX_8888 The Color Setting is ...

Page 1226: ...tern OffsetX Value 0x0 6 3 40 Pattern Offset X Register PATOFF_X_REG R W Address 0xEE80_ 0704 PATOFF_X_REG Bit Description Reset Value Reserved 31 3 Reserved 0x0 POffsetX 2 0 Pattern OffsetX Value 0x0 6 3 41 Pattern Offset Y Register PATOFF_Y_REG R W Address 0xEE80_ 0708 PATOFF_Y_REG Bit Description Reset Value Reserved 31 3 Reserved 0x0 POffsetY 2 0 Pattern OffsetY Value 0x0 6 3 42 Colorkey Contr...

Page 1227: ...min 7 0 BLUE DR MIN value 0x0 6 3 44 Colorkey Decision Reference Maximum Register COLORKEY _DR_MAX_REG R W Address 0xEE80_ 0728 COLORKEY _DR_MAX_REG Bit Description Reset Value A_DR max 31 24 Alpha DR MAX value 0xFF R_DR max 23 16 RED DR MAX value 0xFF G_DR max 15 8 GREEN DR MAX value 0xFF B_DR max 7 0 BLUE DR MAX value 0xFF 6 3 45 Source Image Base Address Register SRC_BASE_ADDR_REG R W Address 0...

Page 1228: ...16 32 bpp y 32 bit depth buffer 8 bit stencil 24 bit Z y Texture format 1 2 4 8 16 32 bpp RGB YUV 422 S3TC Compressed y Support max 8 user defined textures y API Support OpenGL ES 1 1 2 0 D3D Mobile y Vertex Buffer Vertex Cache y H W Clipping Near Far y Primitive assembly hard wired triangle setup engine y Two pixels cycle hard wired rasterizer y Two texturing engine Nearest bilinear trilinear fil...

Page 1229: ...e L2 Cache Texture L1 Cache Texture L1 Cache Z S Cache Pixel Cache Pixel Cache DMA Texture Cache Arbiter 64 bit AXI 3 channel 32 bit AHB Host Interface HI Post Vertex Cache PVC Vertex Shader VS Primitive Engine PE Triangle Setup Engine TSE Rasterizer RA Per Fragment PF Pixel Shader PS Per Fragment PF Vertex Texture Unit Texture Unit Pixel Shader PS Texture Unit Figure 9 6 1 Overall Block Diagram ...

Page 1230: ...ontrol register 0x00010000 HI_IDXOFFSET 0x0000_800C R W Index offset register signed value 0x00000001 HI_VBADDR 0x0000_8010 R W Vertex Buffer Address 0x00000000 HI_ATTRIB0 0x0000_8040 R W Input attribute 0 control register 0x800000E4 HI_ATTRIB1 0x0000_8044 R W Input attribute 1 control register 0x800000E4 HI_ATTRIB2 0x0000_8048 R W Input attribute 2 control register 0x800000E4 HI_ATTRIB3 0x0000_80...

Page 1231: ...dress of input attribute 7 0x00000000 HI_ATTRIB8_VBBASE 0x0000_80E0 R W Vertex buffer base address of input attribute 8 0x00000000 HI_ATTRIB9_VBBASE 0x0000_80E4 R W Vertex buffer base address of input attribute 9 0x00000000 HI_DWENTRY 0x0000_C000 0x0000_DFFF W The input port of the FIFO in HI Burst writes are possible DWORDs written in 0x0000C000 0x0000DFFF are stored into FIFO of Host Interface H...

Page 1232: ...8 1 6 SPECIAL FUNCTION REGISTER SUMMARY PE Register Address R W Description Reset Value PE_VERTEX_CONTEXT 0x0003_0000 R W Vertex context format definition 0x00000000 PE_VIEWPORT_OX 0x0003_0004 R W The x coordinate of viewport center 0xX PE_VIEWPORT_OY 0x0003_0008 R W The y coordinate of viewport center 0xX PE_VIEWPORT_HALF_PX 0x0003_000C R W Half of viewport width 0xX PE_VIEWPORT_HALF_PY 0x0003_00...

Page 1233: ...lue control register 0x3F800000 RA_PSIZE_MAX 0x0003_8024 R W Point Width Max value control register 0x45000000 RA_COORDREPLACE 0x0003_8028 R W Coord Replace control register 0x00000000 RA_LWIDTH 0x0003_802C R W Line Width control register 0x3F800000 1 8 SPECIAL FUNCTION REGISTER SUMMARY PS Register Address R W Description Reset Value INSTMEM 0x0004_0000 0x0004_1FFF R W Instruction memory of pixel ...

Page 1234: ...0 TU_T_MIN_L0 0x0006_003C R W Texture 0 s Mipmap Min Level 0x00000000 TU_T_MAX_L0 0x0006_0040 R W Texture 0 s Mipmap Max Level 0x00000000 TU_TBADD0 0x0006_0044 R W Texture 0 s base address 0x00000000 TU_TSTA1 0x0006_0050 R W Texture 1 s status 0x08000000 TU_USIZE1 0x0006_0054 R W Texture 1 s U Size 0x00000000 TU_VSIZE1 0x0006_0058 R W Texture 1 s V Size 0x00000000 TU_PSIZE1 0x0006_005C R W Texture...

Page 1235: ..._00DC R W Texture 2 s Mipmap Min Level 0x00000000 TU_T_MAX_L2 0x0006_00E0 R W Texture 2 s Mipmap Max Level 0x00000000 TU_TBADD2 0x0006_00E4 R W Texture 2 s base address 0x00000000 TU_TSTA3 0x0006_00F0 R W Texture 3 s status 0x08000000 TU_USIZE3 0x0006_00F4 R W Texture 3 s U Size 0x00000000 TU_VSIZE3 0x0006_00F8 R W Texture 3 s V Size 0x00000000 TU_PSIZE3 0x0006_00FC R W Texture 3 s P Size 0x000000...

Page 1236: ...set 0x00000000 TU_T_MIN_L 4 0x0006_017C R W Texture 4 s Mipmap Min Level 0x00000000 TU_T_MAX_L4 0x0006_0180 R W Texture 4 s Mipmap Max Level 0x00000000 TU_TBADD4 0x0006_0184 R W Texture 4 s base address 0x00000000 TU_TSTA5 0x0006_0190 R W Texture 5 s status 0x08000000 TU_USIZE5 0x0006_0194 R W Texture 5 s U Size 0x00000000 TU_VSIZE5 0x0006_0198 R W Texture 5 s V Size 0x00000000 TU_PSIZE5 0x0006_01...

Page 1237: ...exture 6 s Level 11 Texture Offset 0x00000000 TU_T_MIN_L 6 0x0006_021C R W Texture 6 s Mipmap Min Level 0x00000000 TU_T_MAX_L6 0x0006_0220 R W Texture 6 s Mipmap Max Level 0x00000000 TU_TBADD6 0x0006_0224 R W Texture 6 s base address 0x00000000 TU_TSTA7 0x0006_0230 R W Texture 7 s status 0x08000000 TU_USIZE7 0x0006_0234 R W Texture 7 s U Size 0x00000000 TU_VSIZE7 0x0006_0238 R W Texture 7 s V Size...

Page 1238: ...lette address for indexed texture 0x00000000 TU_PALLETTE_IN 0x0006_0294 W Palette data in 0x00000000 VT_VTSTA0 0x0006_02C0 R W Vertex texture 0 s status 0x00000000 VT_VTSTA1 0x0006_02C8 R W Vertex texture 1 s status 0x00000000 VT_VTSTA2 0x0006_02D0 R W Vertex texture 2 s status 0x00000000 VT_VTSTA3 0x0006_02D8 R W Vertex texture 3 s status 0x00000000 VT_VTBADDR0 0x0006_02C4 R W Vertex texture 0 s ...

Page 1239: ...T 0x0007_0010 R W Back face stencil test control register 0x0000000 PF_DEPTHT 0x0007_0014 R W Depth test control register 0x00000002 PF_CCLR 0x0007_0018 R W Blend constant color 0x00000000 PF_BLEND 0x0007_001C R W Blending control register 0x00000000 PF_LOGOP 0x0007_0020 R W RGBA color logical operation enable function 0x00000000 PF_CBMSK 0x0007_0024 R W Color write mask in RGBA mode 0x00000000 PF...

Page 1240: ...increased This is the reason why GB_PIPESTATE exists 2 3 DATA TRANSFER USING 3D ACCELERATOR S INTERRTUP The data transfer includes the modification of SFR values and the geometry data transfer interrupts can be used to change SFR values and send geometry data Interrupts from 3D ACCELERATOR s pipeline state can be used to know when to change SFR values for a 3D ACCELERATOR block SFR values for a bl...

Page 1241: ...RATOR is empty the pipeline state generates an interrupt right after 3D ACCELERATOR interrupt is enabled However the 3D ACCELERATOR interrupt handler is executed when CPU executes the other user mode application program IRQ interrupt in enabled in the above figure Figure 9 6 4 illustrates how to change SFR values SFR can be changed when all the pipe state becomes empty ...

Page 1242: ...C100 USER S MANUAL REV1 0 3D ACCELERATOR 9 6 15 Figure 9 6 5 A Simple Example of Changing SFR Values Other Methods Can be Used as Well Note that the above scheme can be used also to transfer geometry data ...

Page 1243: ...it 0 is not empty busy 0b Reserved 11 Reserved 0 RA 10 0b raster engine is empty 1b raster engine is not empty busy 0b TSE 9 0b triangle setup engine is empty 1b triangle setup engine is not empty busy 0b PE 8 0b primitive engine is empty 1b primitive engine is not empty busy 0b Reserved 7 5 Reserved 0 VS 4 0b vertex shader is empty 1b vertex shader is not empty busy 0b VC 3 0b vertex cache is emp...

Page 1244: ...exture cache clear Automatically set to 0b after a cycle 00 default states both texture cache0 and cache1 unchanged 01 texture cache0 starts invalidation texture cache1 unchanged 10 texture cache1 starts invalidation texture cache0 unchanged 11 both texture cache0 and cache1 start invalidation 00b Reserved 7 6 Reserved 0 CCFLUSH 5 4 Color cache flush Automatically set to 00b after flushing 00 colo...

Page 1245: ...3D ACCELERATOR S5PC100 USER S MANUAL REV1 0 9 6 18 ...

Page 1246: ...is not important the write operation into GB_INTPENDING clears its value Currently GB_PIPESTATE Pipeline State in HI can only generate an interrupt Once 3D ACCELERATOR generates an interrupt CPU knows that GB_PIPESTATE is the interrupt source without reading GB_INTPENDING GB_INTPENDING Bit Description Reset Value Reserved 31 1 Reserved 0 Pipeline State 0 Read Pipeline State interrupt is generated ...

Page 1247: ...s 0b PF0 16 0b don t care 1b used to generate interrupts 0b Reserved 15 14 Reserved 0 PS1 13 0b don t care 1b used to generate interrupts 0b PS0 12 0b don t care 1b used to generate interrupts 0b Reserved 11 Reserved 0 RA 10 0b don t care 1b used to generate interrupts 0b TSE 9 0b don t care 1b used to generate interrupts 0b PE 8 0b don t care 1b used to generate interrupts 0b Reserved 7 5 Reserve...

Page 1248: ...pty 0b PS0 12 0b interrupts when the PS0 is not working Empty 1b interrupts when the PS0 is working not empty 0b Reserved 11 Reserved 0 RA 10 0b interrupts when the RA is not working Empty 1b interrupts when the RA is working not empty 0b TSE 9 0b interrupts when the TSE is not working Empty 1b interrupts when the TSE is working not empty 0b PE 8 0b interrupts when the PE is not working Empty 1b i...

Page 1249: ...the PS0 was not empty when an interrupt occurred 0b Reserved 11 Reserved 0 RA 10 0b the RA was empty when an interrupt occurred 1b the RA was not empty when an interrupt occurred 0b TSE 9 0b the TSE was empty when an interrupt occurred 1b the TSE was not empty when an interrupt occurred 0b PE 8 0b the PE was empty when an interrupt occurred 1b the PE was not empty when an interrupt occurred 0b Res...

Page 1250: ... the contents of the frame buffer are to be used for textures CPU must copy the frame buffer data to the texture The next section describes how to feed the geometry data to the Host Interface In this document DWORD represents 32 bit data A vertex is composed of several attributes Vertex attributes are used in the vertex shader program The vertex shader program determines what the given attributes ...

Page 1251: ...rface Host Interface uses the transferred index for the index to the Vertex Buffer And then the next index is automatically calculated HI_IDXOFFSET VALUE is added to the previous index usually set to 1 This process is repeated count times Each pair of DWORDs count and index value represents a set of indices Therefore this scheme maximizes the performance in transferring geometry data Figure 9 6 6 ...

Page 1252: ... the geometry data Just like index mode the number of vertices and an index must be transferred first In this case a dummy value 0xFFFFFFFF must be used as an index Figure 9 6 9 Non Index Mode The transferred data are decoded using HI_ATTRIB0 HI_ATTRIB9 Note that when float or half float format data is transferred to the Host Interface NaN or Infinite values must not be transferred ...

Page 1253: ...the index for Index mode In Non Index mode this step is skipped 4 for each n from 0x0 to 0xF 5 if HI_CONTROL EnVB 1 HI_ATTRIB n _VBCTRL Range 0 index HI_ATTRIB n _VBCTRL Range 6 Use DWORDs fetched from VertexBuffer HI_ATTRIB n _VBBASE Addr index HI_ATTRIB n _VBCTRL Stride Index mode 7 else 8 Fetch DWORDs from CPU and use them as the geometry data Non Index mode 9 Transform DWORDs into floating poi...

Page 1254: ...ue CPU can do the other job or process or continue to send the other part of the geometry data repeating the same procedure The CPU can use the interrupt scheme of 3D ACCELERATOR It depends wholy on the device driver Interrupts and Vertex Buffer are very useful schemes when a geometry is transferred See Section HOW TO USE THE VERTEX BUFFER AS A TEMPORAL BUFFER USING INTERRRUPTS for more informatio...

Page 1255: ...ter saving DWORDs into Vertex Buffer CPU sets 3D ACCELERATOR s interrupt scheme making the interrupt unit send an interrupt to CPU when the values of GB_PIPESTATE for Host FIFO and Host Interface become zero At this time CPU can do other valuable job such as Operating System or Sound related processes waiting for an interrupt from 3D ACCELERATOR If an interrupt from 3D ACCELERATOR is occurred and ...

Page 1256: ... wrtten by CPU the Post Vertex Cache is cleared or initialized automatically When you send a series of indices for a geometry data you send another different geometry In this case the index for the previous geometry data which is remained in Vertex Cache can be hit when the index of the new geometry data is sent Hence when you send multiple geometry data using index mode you must clear the content...

Page 1257: ... and the geometry data is transferred into this register 3 9 3 Host Interface Control Register HI_CONTROL R W Address 0X0000_8008 HI_CONTROL Bit Description Reset Value EnVB 31 Enable Vertex Buffer 0b Reserved 30 26 Reserved 0 IdxType 25 24 Transferred index type 00b unsigned int 01b unsigned short 10b reserved 11b unsigned byte 00b Reserved 23 17 Reserved 0 AutoInc 16 Auto increment mode 1b Reser...

Page 1258: ... CPU Then the used indices in the HI are index0 VAL index1 VAL index2 VAL etc If the recalculated indices are within HI_ATTRIBn_VBCTRL Range the geometry data in Vertex Buffer is used 0x00000001 3 9 5 Vertex Buffer Address Register HI_VBADDR R W Address 0X0000_8010 HI_VBADDR Bit Description Reset Value VAL 31 0 Start address of attribute to copy the geometry data 0x0 3 9 6 Vertex Buffer Entry Port...

Page 1259: ...signed short two attributes can be reside in a DWORD Therefore two DWORDs are required for 16 bit x 16 bit y 16 bit z and 16 bit w Figure 9 6 11 Memory Layouts for Short type Vertex Attribute in DWORDs from CPU or in the Vertex Buffer Note that when DWORDs are stored in the Vertex Buffer the above rule is also applied y Input attribute 0 Control Register R W Address 0x0000_8040 y Input attribute 1...

Page 1260: ...unsigned byte 0 255 0101 unsigned sort 0 65535 0110 unsigned int 0 4294967295 0111 float IEEE 754 single precision 1000 normalized byte 1 0f 1 0f 1001 normalized short 1 0f 1 0f 1010 normalized int 1 0f 1 0f 1011 normalized fixed 0 0f 1 0f 1100 normalized unsigned byte 0 0f 1 0f 1101 normalized unsigned short 0 0f 1 0f 1110 normalized unsigned int 0 0f 1 0f 1111 Half float h s 5 10 format When flo...

Page 1261: ...t Z component 00b select a component as Z 01b select b component as Z 10b select c component as Z 11b select d component as Z NOTE a d is defined in NumComp field 10b SrcY 3 2 Select Y component 00b select a component as Y 01b select b component as Y 10b select c component as Y 11b select d component as Y NOTE a d are defined in NumComp field 01b SrcX 1 0 Select X component 00b select a component ...

Page 1262: ...088 y Vertex Buffer Control of Input Attribute 3 R W Address 0x0000_808C y Vertex Buffer Control of Input Attribute 4 R W Address 0x0000_8090 y Vertex Buffer Control of Input Attribute 5 R W Address 0x0000_8094 y Vertex Buffer Control of Input Attribute 6 R W Address 0x0000_8098 y Vertex Buffer Control of Input Attribute 7 R W Address 0x0000_809C y Vertex Buffer Control of Input Attribute 8 R W Ad...

Page 1263: ...W Address 0x0000_80CC y Vertex Buffer Base Address Of Input Attribute 4 R W Address 0x0000_80D0 y Vertex Buffer Base Address Of Input Attribute 5 R W Address 0x0000_80D4 y Vertex Buffer Base Address Of Input Attribute 6 R W Address 0x0000_80D4 y Vertex Buffer Base Address Of Input Attribute 7 R W Address 0x0000_80D8 y Vertex Buffer Base Address Of Input Attribute 8 R W Address 0x0000_80E0 y Vertex...

Page 1264: ...program is composed of instruction sequences constant floating point values for the arithmetic operations constant integer and boolean values for the flow control These should be stored in the register or memory region before executing the program Vertex shader starts automatically when the host writes all attributes for a vertex 4 3 VERTEX SHADER SPECIAL REGISTERS The shader instruction and the c...

Page 1265: ...ter before use it 4 3 3 Constant Float W Component Value WORD 3 R W Address 0X0001_4XXC 00 XX FF WORD3 Bit Description Reset Value W 127 96 Constant float W component value 0xXXXXXXXX 4 3 4 Constant Float Z Component Value WORD 2 R W Address 0X0001_4XX8 00 XX FF WORD2 Bit Description Reset Value Z 95 64 Constant float Z component value 0xXXXXXXXX 4 3 5 Constant Float Y Component Value WORD 1 R W A...

Page 1266: ...ister VS_CINT R W Address 0X0001_8000 0X0001_803F The constant integer values can be stored in the constant integer register The constant integer value is only used for the flow control that is the iteration count for loop or the index of relative addressing The constant integer register has 16 entries and each entry is composed of 4 channel 8 bit unsigned integer value User has to initialize this...

Page 1267: ...initialize this register before use it CBOOL Bit Description Reset Value Reserved 31 16 Reserved 0xXXXX REG15 15 Constant Bool register 15 X REG14 14 Constant Bool register 14 X REG13 13 Constant Bool register 13 X REG12 12 Constant Bool register 12 X REG11 11 Constant Bool register 11 X REG10 10 Constant Bool register 10 X REG9 9 Constant Bool register 9 X REG8 8 Constant Bool register 8 X REG7 7...

Page 1268: ...ithout copy command the value of VS_PCRange is not used and the previous values are used for program start and end address 0b 4 3 11 Configuration Register for Vertex Shader FGVS VS_ STATUS R ADDRESS 0X0001_C804 Global register contains various configurations and environment setting for global operation VS_Status Bit Description Reset Value Reserved 31 1 Reserved 0 ClrStatus 1 When this bit is set...

Page 1269: ...ually call and ret instruction works a pair But the intentional unmatched ret makes vertex shader termination condition By this exception vertex shader program can be terminated 0x1FF Reserved 15 9 Reserved 0 PCStart 8 0 When the vertex shader start operation the first instruction which is stored at PCStart is fetched from instruction memory This register value should be copied to vertex shader pr...

Page 1270: ...Attrib3 27 24 Index of input attribute 3 0x3 Reserved 23 20 Reserved 0 Attrib 2 19 16 Index of input attribute 2 0x2 Reserved 15 12 Reserved 0 Attrib 1 11 8 Index of input attribute 1 0x1 Reserved 7 4 Reserved 0 Attrib 0 3 0 Index of input attribute 0 0x0 VS_InAttrIndex1 Bit Description Reset Value Reserved 31 28 Reserved 0 Attrib7 27 24 Index of input attribute 7 0x7 Reserved 23 20 Reserved 0 Att...

Page 1271: ...y VS_OutAttrIndex1 W Address 0x0002_0018 y VS_OutAttrIndex2 W Address 0x0002_001C VS_OutAttrIndex0 Bit Description Reset Value Reserved 31 28 Reserved 0 Attrib3 27 24 Index of output attribute 3 0x3 Reserved 23 20 Reserved 0 Attrib2 19 16 Index of output attribute 2 0x2 Reserved 15 12 Reserved 0 Attrib1 11 8 Index of output attribute 1 0x1 Reserved 7 4 Reserved 0 Attrib0 3 0 Index of output attrib...

Page 1272: ...S5PC100 USER S MANUAL REV1 0 3D ACCELERATOR 9 6 45 VS_OutAttrIndex2 Bit Description Reset Value Reserved 7 4 Reserved 0 Attrib8 3 0 Index of output attribute 8 0x8 ...

Page 1273: ...he primitive engine Vertex From Shader Clip coordinate system Primitive Assembly Shade Model Frustum Clipping Perspective Division Viewport Mapping To Triangle Setup Window coordinate system Figure 9 6 12 PE Pipeline 5 2 PRIMITIVE ENGINE SPECIAL REGISTERS There are two kinds of special registers in primitive engine One is for vertex information such as primitive types the number of associated data...

Page 1274: ...bit field from 0 to 8 is associated with the vertex shader output slot When the master flag is 0 the bit fields associated with vertex shader output slot are ignored For example to use vertex shader output slot0 as flat color channel bit field 9 and bit field 0 must be set as 1 The bit field 31 and 30 are used internally so don t touch these bit fields Note In 3D ACCELERATOR the vertex shader supp...

Page 1275: ...is use flat shade model 0b vertex shader output7 using smooth shade model 0b FLAT_MODEL6 6 1b vertex shader output6 is use flat shade model 0b vertex shader output6 using smooth shade model 0b FLAT_MODEL5 5 1b vertex shader output5 is use flat shade model 0b vertex shader output5 using smooth shade model 0b FLAT_MODEL4 4 1b vertex shader output4 is use flat shade model 0b vertex shader output4 usi...

Page 1276: ...epth range f The center of viewport ox oy can be expressed as x0 px 2 y0 py 2 assuming that the origin of viewport is x0 y0 In 3D ACCELERATOR y axes flipped window coordinates system is used To generate y axes flipped window coordinates system we simply replace y axes related equations yw py 2 yd oy and oy y0 py 2 with yw py 2 yd oy and oy window height y0 py 2 respectively y PE_VIEWPORT_OX R W Ad...

Page 1277: ...n widow coordinate system y n near value of the depth range y f far value of the depth range y H the height of the window in terms of pixel Bit Description Reset Value PE_VIEWPORT_OX 31 0 The x coordinate of viewport center 2 0 x p x 0xX Bit Description Reset Value PE_VIEWPORT_OY 31 0 The y coordinate of viewport center 2 0 y p y If you want to generate y flipped window coordinates set this SFR as...

Page 1278: ...t to generate y flipped window coordinates set this SFR as follows 2 y p 0xX Bit Description Reset Value PE_DEPTHRANGE_HAL F_F_SUB_N 31 0 The half value of subtract depth range far from near 2 n f 1 0 f n 0x3F000000 Bit Description Reset Value PE_DEPTHRANGE_HAL F_F_ADD_N 31 0 The half value of add depth range far to near 2 n f 1 0 f n 0x3F000000 ...

Page 1279: ...ERVIEW Raster engine include triangle setup engine and rasterizer 6 1 1 Triangle Setup Engine Overview y Primitive y value bounding y Back face culling y Edge interpolation y Triangle gradients calculation y Depth offset calculation Figure 9 6 15 Triangle Setup Stage Overview ...

Page 1280: ...r an object that uses depth offset This register value can be changed only in context switching time Back face culling control register To process back face cull cull face register front face register and enable register all should be set This register value can be changed only in context switching time LOD control register It is necessary to set this register if pixel shader uses DDX DDY LOD This...

Page 1281: ...ERS 6 3 1 Sampling Position Register RA_PIXSAMP R W Address 0X0003_8000 RA_PixSamp Bit Description Reset Value Reserved 31 1 Reserved PixCornerSamp 0 Select sample position used when fetching pixels for texture and shading 0b 0 5 0 5 center position 1b 0 0 left top corner position 0b ...

Page 1282: ...Address 0x0003_800C y RA_DOffRIn R W Address 0x0003_8010 RA_DOffEn Bit Description Reset Value Reserved 31 1 Reserved 0 DOffEn 0 Depth offset usage control register 0b Disable 1b Enable 0b RA_DOffFactor Bit Description Reset Value DOffFactor 31 0 Factor scales the max depth slope of the polygon Used to calculate the depth offset value 0x0 RA_DOffUnits Bit Description Reset Value DOffUnits 31 0 Uni...

Page 1283: ...A_YCLIP R W Address 0X0003_8018 In programmer s view screen has 0 0 pixel in the left bottom corner But in the view of H W 0 0 pixel is in the left top corner So it is necessary to flip the y coordinate value when Y clipping value is set After receiving the value of dd_min_val and dd_max_val from device driver the following equation is used to get MIN MAX values MAX screen_height_val 1 dd_min_val ...

Page 1284: ...1 K8 K12 1 1 0 K1 K3 K5 K2 K4 K6 K7 K9 K11 K8 K10 K12 1 1 1 K1 K3 K5 K2 K4 K6 K7 K9 K11 K8 K10 K12 RA_LODCTL Bit Description Reset Value Reserved 31 24 Reserved 0 LodCon7 23 21 DDY DDX LOD for attribute 7 000b all LOD coefficient disable 001b LOD coefficients calculation enable 010b DDX coefficients calculation enable 011b DDX LOD coefficients enable 100b DDY coefficients calculation enable 101b D...

Page 1285: ...gisters FGRA y RA_PWIDTH R W Address 0x0003_801C y RA_PSIZE_MIN R W Address 0x0003_8020 y RA_PSIZE_MAX R W Address 0x0003_8024 Point width value is clamped by Point Width Min and Point Width Max values RA_PWIDTH Bit Description Reset Value PointWidth 31 0 Specify point width value floating point 0x3F800000 RA_PSIZE_MIN Bit Description Reset Value PointSize_Min 31 0 Specify point width minimum valu...

Page 1286: ...d 0x0 CoordReplace7 7 Coord Replace control bit for Attribute 7 0 CoordReplace6 6 Coord Replace control bit for Attribute 6 0 CoordReplace5 5 Coord Replace control bit for Attribute 5 0 CoordReplace4 4 Coord Replace control bit for Attribute 4 0 CoordReplace3 3 Coord Replace control bit for Attribute 3 0 CoordReplace2 2 Coord Replace control bit for Attribute 2 0 CoordReplace1 1 Coord Replace cont...

Page 1287: ... 17 Pixel Shader Block Diagram Programmable shader has two register groups according to its usage One is special function register SFR for HW configuration and the other is program register for shader program SFR can be accessed by only HOST CPU Some of program registers such as instruction memory constant float register constant integer register and constant Boolean register can be access by both...

Page 1288: ...recision floating point format De normalized number is not supported Initial value of this register is un known because it is stored internal sram User has to initialize this register before use it y Constant Float W Component Value Word 3 R W Address 0x0004_4XXC 0 XX FF y Constant Float Z Component Value Word 2 R W Address 0x0004_4XXC 0 XX FF y Constant Float Y Component Value Word 1 R W Address ...

Page 1289: ...and F 0 and S 1 y 0 if E 0 and F 0 and S 0 7 1 3 Constant Integer Register PS_CINT R W Address 0X0004_8000 0X0004_803F The constant integer values can be stored in the constant integer register The constant integer value is only used for the flow control that is the iteration count for loop or the index of relative addressing The constant integer register has 16 entries and each entry is composed ...

Page 1290: ... initialize this register before use it PS_CBOOL Bit Description Reset Value Reserved 31 16 Reserved 0 REG15 15 Constant Bool register 15 0 REG14 14 Constant Bool register 14 0 REG13 13 Constant Bool register 13 0 REG12 12 Constant Bool register 12 0 REG11 11 Constant Bool register 11 0 REG10 10 Constant Bool register 10 0 REG9 9 Constant Bool register 9 0 REG8 8 Constant Bool register 8 0 REG7 7 ...

Page 1291: ...l shader operation is unpredictable The mode change constraints PSHostMode Æ PSExeMode Set All configuration register value Load Instruction Constant F B I register Confirm PS_IBStatus is 0 Assert PS_ExeMode to 1 PSExeMode Æ PSHostMode Confirm IsNotEmpty_PS is 0 for all pixel shader Assert PS_ExeMode to 0 0b 7 1 7 Special Function Register For Hw Configuration FGPS PS_ PCSTART R W ADDRESS 0X0004_C...

Page 1292: ... count to execute The other way to terminate pixel shader program Pixel shader program can be terminated by the extra ret instruction which makes program counter stack empty condition Usually call and ret instruction works a pair But the intentional unmatched ret makes pixel shader termination condition By this exception pixel shader program can be terminated 0x1FF 7 1 9 Special Function Register ...

Page 1293: ...ter PS_ AttributeNum should be set to 1 Otherwise this register is set to the number of semantics transferred to pixel shader input register If pixel shader program use more semantics than that transferred to pixel shader input register the pixel shader output is unpredictable 0x8 7 1 11 Special Function Register For Hw Configuration FGPS PS_ IBSTATUS R ADDRESS 0X0004_C814 PS_IBStatus Bit Descript...

Page 1294: ...x1 y Max Mipmap Levels 12 Levels y Texture Size fo Mipmap Level i Max 1 floor Width of level 0 texture 2i x Max 1 floor Height of level 0 texture 2i y Texture unit supports 2D texture Cubemap and 3D texture For 3D textures Level 0 texture only y Bilinear Trilinear Filtering is supported Also S3TC compression format and paletted texture format are supported For S3TC compression format Min Width Hei...

Page 1295: ...e type 00b reserved 01b 2D enable 10b Cube Enable 11b 3D enable 01b Reserved 26 23 Reserved 0000b CK_SEL 22 21 Color Key Enable Selection 00b Disable 01b Enable Use Color Key Register 1 or Color Key YUV Register 10b Disable 11b Enable Use Color Key Register 2 or Color Key YUV Register 00b TEX_EXP 20 Texture Value Expansion Method 0b Duplicate LSB 1b Zero Padding 0b AFORMAT_SEL 19 Alpha Location Se...

Page 1296: ...on parametric coordinate system VADDR_MODE are set to clamp to edge 00b PADDR_MODE 7 6 Mode used in P address 00b Repeat 01b Flip 10b Clamp to edge 11b reserved Note In non parametric coordinate system PADDR_MODE are set to clamp to edge 00b Reserved 5 Eeserved 0b TEX_COOR 4 Texture Addressing Coordinate System 0b Parametric 1b Non parametric 0b MAG_FILTER 3 Bilinear Filter Control Magnification 0...

Page 1297: ... Address 0x0006_0234 TU_USIZEn Bit Description Reset Value Reserved 31 11 Reserved 0 U_SIZE 10 0 U Size of Level 0 Texture 0x0 8 2 3 Texture V Size Register 0 7 TU_VSIZE y TU_VSIZE0 R W Address 0x0006_0008 y TU_VSIZE1 R W Address 0x0006_0058 y TU_VSIZE2 R W Address 0x0006_00A8 y TU_VSIZE3 R W Address 0x0006_00F8 y TU_VSIZE4 R W Address 0x0006_0148 y TU_VSIZE5 R W Address 0x0006_0198 y TU_VSIZE6 R ...

Page 1298: ...it Description Reset Value Reserved 31 11 Reserved 0 P_SIZE 10 0 P Size of Level 0 Texture the Depth of 3D Textures 0x0 8 2 5 Texture L1 Offset Register 0 7 TU_TOFFS_L1 y TU_TOFFS_L1_0 R W Address 0x0006_0010 y TU_TOFFS_L1_1 R W Address 0x0006_0060 y TU_TOFFS_L1_2 R W Address 0x0006_00B0 y TU_TOFFS_L1_3 R W Address 0x0006_0100 y TU_TOFFS_L1_4 R W Address 0x0006_0150 y TU_TOFFS_L1_5 R W Address 0x0...

Page 1299: ... Address 0x0006_0244 TU_TOFFS_L2n Bit Description Reset Value Reserved 31 23 Reserved 0 OFFSET 22 0 Level 2 Texture Offset 0x0 8 2 7 Texture L3 Offset Register 0 7 TU_TOFFS_L3 y TU_TOFFS_L3_0 R W Address 0x0006_0018 y TU_TOFFS_L3_1 R W Address 0x0006_0068 y TU_TOFFS_L3_2 R W Address 0x0006_00B8 y TU_TOFFS_L3_3 R W Address 0x0006_0108 y TU_TOFFS_L3_4 R W Address 0x0006_0158 y TU_TOFFS_L3_5 R W Addr...

Page 1300: ... Address 0x0006_024C TU_TOFFS_L4n Bit Description Reset Value Reserved 31 23 Reserved 0 OFFSET 22 0 Level 4 Texture Offset 0x0 8 2 9 Texture L5 Offset Register 0 7 TU_TOFFS_L5 y TU_TOFFS_L5_0 R W Address 0x0006_0020 y TU_TOFFS_L5_1 R W Address 0x0006_0070 y TU_TOFFS_L5_2 R W Address 0x0006_00C0 y TU_TOFFS_L5_3 R W Address 0x0006_0110 y TU_TOFFS_L5_4 R W Address 0x0006_0160 y TU_TOFFS_L5_5 R W Addr...

Page 1301: ... Address 0x0006_0254 TU_TOFFS_L6n Bit Description Reset Value Reserved 31 23 Reserved 0 OFFSET 22 0 Level 6 Texture Offset 0x0 8 2 11 Texture L7 Offset Register 0 7 TU_TOFFS_L7 y TU_TOFFS_L7_0 R W Address 0x0006_0028 y TU_TOFFS_L7_1 R W Address 0x0006_0078 y TU_TOFFS_L7_2 R W Address 0x0006_00C8 y TU_TOFFS_L7_3 R W Address 0x0006_0118 y TU_TOFFS_L7_4 R W Address 0x0006_0168 y TU_TOFFS_L7_5 R W Add...

Page 1302: ... Address 0x0006_025C TU_TOFFS_L8n Bit Description Reset Value Reserved 31 23 Reserved 0 OFFSET 22 0 Level 8 Texture Offset 0x0 8 2 13 Texture L9 Offset Register 0 7 TU_TOFFS_L9 y TU_TOFFS_L9_0 R W Address 0x0006_0030 y TU_TOFFS_L9_1 R W Address 0x0006_0080 y TU_TOFFS_L9_2 R W Address 0x0006_00D0 y TU_TOFFS_L9_3 R W Address 0x0006_0120 y TU_TOFFS_L9_4 R W Address 0x0006_0170 y TU_TOFFS_L9_5 R W Add...

Page 1303: ...ddress 0x0006_0264 TU_TOFFS_L10n Bit Description Reset Value Reserved 31 23 Reserved 0 OFFSET 22 0 Level 10 Texture Offset 0x0 8 2 15 Texture L11 Offset Register 0 7 TU_TOFFS_L11 y TU_TOFFS_L11_0 R W Address 0x0006_0038 y TU_TOFFS_L11_1 R W Address 0x0006_0088 y TU_TOFFS_L11_2 R W Address 0x0006_00D8 y TU_TOFFS_L11_3 R W Address 0x0006_0128 y TU_TOFFS_L11_4 R W Address 0x0006_0178 y TU_TOFFS_L11_5...

Page 1304: ...ddress 0x0006_026C TU_T_MIN_Ln Bit Description Reset Value Reserved 31 4 Reserved 0 MIN_LEVEL 3 0 Texture Mipmap Min level 0x0 8 2 17 Texture Max Level Register 0 7 TU_T_MAX_L y TU_T_MAX_L0 R W Address 0x0006_0040 y TU_T_MAX_L1 R W Address 0x0006_0090 y TU_T_MAX_L2 R W Address 0x0006_00E0 y TU_T_MAX_L3 R W Address 0x0006_0130 y TU_T_MAX_L4 R W Address 0x0006_0180 y TU_T_MAX_L5 R W Address 0x0006_0...

Page 1305: ...ss for Level 0 0xXXXXXXXX 8 2 19 Texture Color Key Register TU_CKEY y TU_CKEY1 R W Address 0x0006_0280 y TU_CKEY2 R W Address 0x0006_0284 y TU_ CKYUV R W Address 0x0006_0288 y TU_ CKMASK R W Address 0x0006_028C TU_CKEY1 Bit Description Reset Value reserved 31 24 reserved R 23 16 Color key red value not YUV and CK_SEL 01 0x0 G 15 8 Color key green value not YUV and CK_SEL 01 0x0 B 7 0 Color key blu...

Page 1306: ... 010b mask 2 lsb of each CK color component 011b mask 3 lsb of each CK color component 100b mask 4 lsb of each CK color component 101b mask 5 lsb of each CK color component 110b mask 6 lsb of each CK color component 111b mask 7 lsb of each CK color component 000b 8 2 20 Texture Palette Register TU_PALETTE y TU_ PALETTE_ADDR W Address 0x0006_0290 y TU_ PALETTE_IN W Address 0x0006_0294 TU_PALETTE_AD...

Page 1307: ...erved 00b VMOD 9 8 Mode used in v address 00b repeat 01b flip 11b clamp to edge 11b reserved 00b USIZE 7 4 Texture u size 0000b 1 pixel 0001b 2 pixels 0010b 4 pixels 0011b 8 pixels 0100b 16 pixels 0101b 32 pixels 0110b 64 pixels 0111b 128 pixels 1000b 256 pixels 1001b 512 pixels 1010b 1024 pixels 1011b 2048 pixels 1100b 1111b reserved 0x0 VSIZE 3 0 Texture v size 0000b 1 pixel 0001b 2 pixels 0010b...

Page 1308: ... Base Address Register VT_VTBADDR y VT_VTBADDR0 R W Address 0x0006_02C4 y VT_VTBADDR1 R W Address 0x0006_02CC y VT_VTBADDR2 R W Address 0x0006_02D4 y VT_VTBADDR3 R W Address 0x0006_02DC VT_VTBADDRn Bit Description Reset Value ADDR 31 0 Vertex texture bass address 0xXXXXXXXX ...

Page 1309: ...ha Test y Per Fragment Unit support Stencil Test Stencil Buffer is 8 bit and Stencil Operation Also support both front stencil buffer and back stencil buffer y Per Fragment Unit support Depth Test Depth Buffer is 24 bit y Per Fragment Unit Support Alpha Blending y Per Fragment Unit Support Logical Operation y Per Fragment Unit Support 16 32bit color mode y For Enhanced Color Per Fragment Unit supp...

Page 1310: ...S5PC100 USER S MANUAL REV1 0 3D ACCELERATOR 9 6 83 Figure 9 6 18 Per Fragment Function Block Diagram ...

Page 1311: ...to the frame buffer 0x0 reserved 15 12 Reserved 0 XMin 11 0 Pixel s X coordinate MIN is not written to the frame buffer 0x0 PF_SCISSOR_Y Bit Description Reset Value Reserved 31 28 Reserved 0 YMax 27 16 Pixel s Y coordinate MAX is not written to the frame buffer 0x0 Reserved 15 12 Reserved 0 YMin 11 0 Pixel s Y coordinate MIN is not written to the frame buffer 0x0 9 2 2 Alpha Test Control Register ...

Page 1312: ...11b DECR_WRAP 000b FrontStencil_dpfail 28 26 Stencil depth buffer fail action Same as above 000b FrontStencil_sfail 25 23 Stencil fail action Same as above 000b reserved 22 20 reserved FrontStencilMaskValue 19 12 8 bit stencil mask value 0x0 FrontStencilTestValue 11 4 8 bit stencil reference value 0x0 FrontStencilTestMode 3 1 Mode used in stencil test 000b NEVER 001b ALWAYS 010b LESS 011b LEQUAL l...

Page 1313: ...skValue 19 12 8 bit Stencil mask value 0x0 BackStencilTestValue 11 4 8 bit Stencil reference value 0x0 BackStencilTestMode 3 1 Mode used in Stencil test 000b NEVER 001b ALWAYS 010b LESS 011b LEQUAL 100b EQUAL 101b GREATER 110b GEQUAL 111b NOTEQUAL 000b Reserved 0 Reserved 0 9 2 4 Depth Test Control Register PF_DEPTHT R W Address 0X0007_0014 PF_DEPTHT Bit Description Reset Value Reserved 31 4 Reser...

Page 1314: ...Max 000b AlphaDstBlendFu nc 16 13 Mode used in Blending destination function 0000b ZERO 0001b ONE 0010b SRC_COLOR 0011b ONE_MINUS_SRC_COLOR 0100b DST_COLOR 0101b ONE_MINUS_DST_COLOR 0110b SRC_ALPHA 0111b ONE_MINUS_SRC_ALPHA 1000b DST_ALPHA 1001b ONE_MINUS_DST_ALPHA 1010b CONSTANT_COLOR 1011b ONE_MINUS_CONSTANT_COLOR 1100b CONSTANT_ALPHA 1101b ONE_MINUS_CONSTANT_ALPHA 1110b SRC_ALPHA_SATURATE 0x0 C...

Page 1315: ... 8 5 Mode used in Logical Operation Argument value Operation 0000 CLEAR 0 0001 AND s d 0010 AND_REVERSE s d 0011 COPY s 0100 AND_INVERTED s d 0101 NOOP d 0110 XOR s xor d 0111 OR s d 1000 NOR s d 1001 EQUIV s xor d 1010 INVERT d 1011 OR_REVERSE s d 1100 COPY_INVERTED s 1101 OR_INVERTED s d 1110 NAND s d 1111 SET all 1 s 0x0 ColorLogOpEnable 4 1 Mode used in color logical operation Same as above 0x...

Page 1316: ...led In the Reset Value the stencil buffer is enabled for writing when stencil test turns on Stencil buffer is consist of 8 bit per pixel so each bit of this register can mask each value of stencil buffer For example 00000000b in this case All 8bits are updated to stencil buffer 00000001b in this case All 8bits are updated to stencil buffer except lsb 1 bit 00000011b in this case All 8bits are upda...

Page 1317: ...ernal ARGB8888 format to 16 bit output pixel 0b dithering disable 1b dithering enable 0b ColorMode 2 0 Mode used in Frame Buffer Color 000b 555 RGB 16 bit top bit written as register alpha 7 001b 565 RGB 16 bit 010b 4444 RGB 16 bit 011b 1555 ARGB 16 bit 100b 0888 RGB 32 bit top byte written as register alpha 101b 8888 ARGB 32 bit 110 111b reserved 000b 9 2 10 Depth Buffer Base Address Register PF_...

Page 1318: ...ER S MANUAL REV1 0 3D ACCELERATOR 9 6 91 9 2 12 Frame Buffer Width Register PF_FBW R W Address 0X0007_0038 PF_FBW Bit Description Reset Value Reserved 31 12 Reserved 0 FbWidth 11 0 Frame buffer width 0 2048 800h ...

Page 1319: ...ent Block Per Fragment Block Z Stencil cache Pixel cache Z Stencil cache Pixel cache Texture Unit L1 cache Texture Unit L1 cache Texture L2 Cache Vertex Texture Unit Vertex Texture Cache AXI BUS AXI ARBITER AXI DMA AXI ARBITER AXI DMA AXI ARBITER AXI DMA Figure 9 6 19 AXI DMA Function Block Diagram ...

Page 1320: ...RT WRITE BYTE MASK SUPPORT VARIOUS BURST TYPE INCR WRAP SUPPORT LOW POWER CHANNEL y IP CORE INTERFACE FIFO INTERFACE EASY TO CONNECT WITH IP CORE Interface with AXI Arbiter0 AXI Arbiter1 z stencil cache or color cache Interface between AXI Arbiter and DMA is FIFO Interface Separate Read Address Channel and Read Data Channel Separate Write Address Channel and Write Data Channel Burst length is fixe...

Page 1321: ...3D ACCELERATOR S5PC100 USER S MANUAL REV1 0 9 6 94 Interface with AXI Bus FIMG_3DSEV1 1 AXI DMA support AMBA AXI BUS protocol ...

Page 1322: ...ludes following features I O and Control z ITU R BT 601 YCbCr 4 4 4 input format z 10 Bit 4X over sampled CVBS S video YPbPr RGB output data to 3 channel 54 MHz DAC z AHB Slave I F for register control Video Standard Compliances for CVBS and S video z M NTSC NTSC J z B D G H I PAL M PAL N PAL Nc PAL z PAL 60 NTSC4 43 Ancillary Data Insertion z EIA 608 compliant Closed Caption CC and Extended Data ...

Page 1323: ...olor Compensation for Invalid RGB Data z Programmable 23 Tap Luma Chroma Filters for Luma Chroma anti aliasing for CVBS z Programmable 95 Tap oversampling filter capable of frequency response compensation NOTE SCART RGB Interlaced scan is not supported with 3 channel DAC ...

Page 1324: ... Figure 9 7 1 Data Flow of TVOUT Module The TVOUT module is composed of the following data sub modules TG Timing Generation CVBS Waveform Generation QAM Modulation and YCbCr Video Processing AAF Affine Transformation luma chroma Anti Aliasing Filter OSF 4x Oversampling Filter VBI Ancillary data insertion during vertical blanking interval CTRL Register Control NOTE 1 Image Mixer is directly connect...

Page 1325: ...TSC 4 43 and PAL 60 Horizontal frequency FH 15 734 kHz 858 samples per line 13 5 MHz sample rate Vertical frequency FV 59 94 Hz 525 lines per frame 3 2 2 625 50 Hz Video standard PAL BGHID PAL N and PAL Nc Horizontal frequency FH 15 625 kHz 864 samples per line 13 5 MHz sample rate Vertical frequency FV 50 00 Hz 625 lines per frame There are four kinds of discrete timing oscillation for sub carrie...

Page 1326: ... 268 269 270 271 272 285 286 Start of Vsync 523 524 525 1 2 3 4 5 6 7 8 9 10 22 261 262 263 264 265 266 267 268 269 270 271 272 285 286 Burst Begins with Positive Half Cycle Burst Phase 180o Relative to U Burst Begins with Negative Half Cycle Burst Phase 180o Relative to U HSYNC H 2 H 2 HSYNC 2 H 2 H 2 Analog Field 2 Analog Field 4 Burst Phase Burst Phase Analog Field 3 Equalizing Pulses Figure 9 ...

Page 1327: ...t Phase 314 315 316 317 318 319 320 336 337 313 312 311 310 309 308 Analog Field 2 1 2 3 4 5 6 7 23 24 625 624 623 622 621 620 Analog Field 3 314 315 316 317 318 319 320 336 337 313 312 311 310 309 308 Analog Field 4 FieldFour FieldThree Field Two FieldOne Burst Blanking Intervals Burst Phase Reference Phase 90o 225o Relative to U Pal Switch 1 V Component Figure 9 7 3 Field PAL BGHIDNc Sequence an...

Page 1328: ...ase 314 315 316 317 318 319 320 336 337 313 312 311 310 309 308 Analog Field 6 1 2 3 4 5 6 7 23 24 625 624 623 622 621 620 Analog Field 7 314 315 316 317 318 319 320 336 337 313 312 311 310 309 308 Analog Field 8 Field Eight Field Seven FieldSix Field Five Burst Blanking Intervals Burst Phase Reference Phase 90o 225o Relative to U PAL Switch 1 V Component Figure 9 7 4 Eight Field PAL BGHIDNc Seque...

Page 1329: ...g are defined as follows Sample Rate 13 5 MHZ 16 Samples Digital Blanking 138 Samples 0 137 Digital Active Line 720 Samples 138 857 Total Line 858 Samples 0 857 Figure 9 7 5 Horizontal Blanking and Active Video Timing 525 60 Hz Sample Rate 13 5 MHZ 12 Samples Digital Blanking Digital Active Line Total Line 144 Samples 0 143 720 Samples 144 863 864 Samples 0 863 Figure 9 7 6 Horizontal Blanking and...

Page 1330: ...d at S video encoding rather than CVBS encoding The AAF sub module in TVOUT provides 23 tap linear FIR filters for spectral shaping of luminance data Y and chrominance data Cb and Cr The filter responses are fully programmable since filter coefficients themselves are controllable Since linear FIR filters have symmetric coefficients 11 coefficients completely defines the filter responses The regist...

Page 1331: ... 1 1 1 1 SDO_CB6 6 7 7 7 SDO_CB7 13 14 15 15 SDO_CB8 28 28 2A 2B SDO_CB9 3F 3F 44 45 SDO_CB10 51 52 57 59 SDO_CB11 56 5A 5F 61 Table 9 7 3 Filter Coefficients of Anti aliasing Filters for Chrominance Cr Register 7 5 IRE Setup 7 3 Sync 7 5 IRE Setup 10 4 Sync 0 IRE Setup 7 3 Sync 0 IRE Setup 10 4 Sync SDO_CR0 0 0 0 0 SDO_CR1 0 0 0 0 SDO_CR2 0 0 0 0 SDO_CR3 0 0 0 0 SDO_CR4 0 0 0 0 SDO_CR5 2 1 2 2 SD...

Page 1332: ... responses of CB and CR anti aliasing filters with the above settings Note that these filters are applied only to CVBS an S video Figure 9 7 7 Magnitude Response of CB and CR Anti Aliasing Filter 13 5 MHz Sampling Rate Figure 9 7 8 Phase Response of CB and CR Anti Aliasing Filter 13 5 MHz Sampling Rate ...

Page 1333: ...vering signals The physical waveform of EIA 608 closed caption and extended data service signals is as follows 10 5 0 25μs 12 91μs 7 Cycles of 0 5035 MHZ Clock Run In 40 IRE Blank Level Sync Level 3 58 MHZ Color Burst 9 Cycles Two 7 Bit Parity ASCIICharacters Data D0 D6 D0 D6 S T A R T P A R I T Y P A R I T Y 240 288 NS Rise Fall Times 2T Bar Shaping 50 2 IRE 10 5 0 25 μs 27 382 μs 33 764 μs Figur...

Page 1334: ...ed for carrying the 20 bit data into the waveform Bits b1 b0 define display aspect ratio control bit b7 b6 b5 b4 b3 b2 define copy control information and bits b13 b12 b11 b10 b9 b8 is used to specify the operation of the reserved functions Bits b19 b18 b17 b16 b15 b14 are used for CRC error check The physical waveform of ITU R BT 1119 compliant Wide Screen Signaling WSS signals is as follows 43 I...

Page 1335: ...roperly scaled and offset luminance video data Y For the chrominance data paths base band chrominance data Cb and Cr are modulated with a sub carrier FSC along with the video standard i e C n U n sin 2π FSC n V n cos 2π FSC n where U n and V n denote properly scaled and offset versions of Cb n and Cr n respectively Then a pilot sinusoidal waveform called a burst is formed and added prior to the st...

Page 1336: ... to sync ratio are controlled by CSETUP CSYNC VSETUP and VSYNC bits in SDO_SCALE registers Note that the configuration of setup level and video to sync ratio in our implementation are set regardless of video standards and output format White Level Sync Level Blank Level 100 IRE 40 IRE Black Level 20 IRE 20 IRE 7 5 IRE White Yellow Cyan Green Magenta Red Blue Black Blank Level Color Saturation 3 58...

Page 1337: ...vel Sync Level Black Blank Level 100 IRE 43 IRE 21 43 IRE White Yellow Cyan Green Magenta Red Blue Black Color Burst 10 1 Cycles 21 43 IRE Blank Level Color Saturation Luminance Level Phase Hue Figure 9 7 14 PAL BGHIDNc Composite Video Signal with 75 Color Bars ...

Page 1338: ... Black Figure 9 7 15 Color Cube Comparison If YCbCr data outside of the RGB cube occurs the CVBS sub module compensates the value so that the result falls within the RGB cube A constant luma and constant hue approach is used for this compensation The luminance Y is not altered while the chrominance Cb and Cr are limited to the maximum valid values having the same hue as the invalid color prior to ...

Page 1339: ...tenuation is done by making the filter response have a boost at high frequency OSF operates in different ways according to the oversampling ratio the number of taps and the meanings of the coefficient registers are different for each case 1 4x oversampling case 13 5Msps interlaced mode It operates as 4 polyphase 95 tap FIR filter All the coefficient registers SDO_OSFC00_0 SDO_OSFC23_0 DAC 0 SDO_OS...

Page 1340: ...4 2 h 82 h 80 2 0 9 SDO_OSFC06 osf_coef13 h 13 h 81 0 9 osf_coef14 h 12 h 14 2 h 82 h 80 2 0 9 SDO_OSFC07 osf_coef15 h 15 h 79 0 9 osf_coef16 h 16 h 18 2 h 78 h 76 2 0 9 SDO_OSFC08 osf_coef17 h 17 h 77 0 9 osf_coef18 h 16 h 18 2 h 78 h 76 2 0 9 SDO_OSFC09 osf_coef19 h 19 h 75 0 9 osf_coef20 h 20 h 22 2 h 74 h 72 2 0 9 SDO_OSFC10 osf_coef21 h 21 h 73 0 9 osf_coef22 h 20 h 22 2 h 74 h 72 2 0 9 SDO_O...

Page 1341: ...27 11 osf_coef44 h 44 h 46 2 h 50 h 48 2 h 20 h 26 12 SDO_OSFC22 osf_coef45 h 45 h 49 h 21 h 25 12 osf_coef46 h 44 h 46 2 h 50 h 48 2 h 22 h 24 12 SDO_OSFC23 osf_coef47 h 47 h 23 12 3 8 BLACK BURST GENERATION FOR DAC CROSSTALK TEST In the three channel video DACs the signal of one channel may leak to others so that some part of it may be detected at the other channel outputs Such interference is c...

Page 1342: ... Active video The level during active video period of black burst is set by ref_bb_level in SDO_BB_CTRL register Black burst signal Black level active video Figure 9 7 16 Black Burst Signal Set sel_bb_chan bits in SDO_BB_CTRL register to select test channel as shown in the following figure ...

Page 1343: ...Test sel_bb_chan 2 b00 Black burst DAC 0 DAC 1 DAC 2 CVBS Black burst 2 Ch1 Test sel_bb_chan 2 b01 measure crosstalk from ch1 to ch0 measure crosstalk from ch1 to ch2 Black burst DAC 0 DAC 1 DAC 2 Black burst CVBS 3 Ch2 Test sel_bb_chan 2 b10 measure crosstalk from ch2 to ch1 measure crosstalk from ch2 to ch0 Figure 9 7 17 Crosstalk Measurement Using Black Burst Generation ...

Page 1344: ... of other channels with gains The following figure shows crosstalk cancellation network Each coefficient in the figure is programmable OSF Ch 0 xtalk_coef01 xtalk_coef02 xtalk_coef10 xtalk_coef12 xtalk_coef21 xtalk_coef20 to DAC Ch 0 to DAC Ch 1 to DAC Ch 2 OSF Ch 1 OSF Ch 2 1 21 _ 0 20 _ 2 2 2 12 _ 0 10 _ 1 1 2 02 _ 1 01 _ 0 0 OSFch coef xalk OSFch coef xtalk OSFch DACch OSFch coef xtalk OSFch co...

Page 1345: ...e gain errors of each sample are recorded at ATE test and the information on the error are e fused into CHIPID bits at mass production In S5L8720 15 CHIPID bits are assigned for the calibration 5 CHIPID bits per channel Please refer to DAC0_CAL DAC1_CAL and DAC2_CAL bits in the CHIPIDL register For digital gain programming SDO_Y_G SDO_PB_B SDO_PR_R SDO_Y SDO_C SDO_CVBS registers are used according...

Page 1346: ... 2048 01001 X 2223 2048 01000 X 2202 2048 00111 X 2182 2048 00110 X 2161 2048 00101 X 2142 2048 00100 X 2122 2048 00011 X 2103 2048 00010 X 2084 2048 00001 X 2066 2048 00000 X 2048 2048 11111 X 2030 2048 11110 X 2013 2048 11101 X 1996 2048 11100 X 1979 2048 11011 X 1962 2048 11010 X 1946 2048 11001 X 1930 2048 11000 X 1914 2048 10111 X 1898 2048 10110 X 1883 2048 10101 X 1868 2048 10100 X 1853 204...

Page 1347: ...us clock 3 12 OUTPUT INTERFACE TVOUT output data are directly feed to DAC The output data are synchronized to video clock vclk Note that output data transit with positive edge of video clock vclk It implies that the two video clocks fed to TVOUT and DAC respectively are recommended to have opposite phase to each other vclk TVOUT dac y 9 0 dac c 9 0 vclk DAC Figure 9 7 19 Output Interface of TVOUT ...

Page 1348: ...xF000_0000 R W Clock Control Register 0x0000_0000 SDO_CONFIG 0xF000_0008 R W Video Standard Configuration Register 0x0024_2430 SDO_SCALE 0xF000_000C R W Video Scale Configuration Register 0x0000_0006 SDO_SYNC 0xF000_0010 R W Video Sync Configuration Register 0x0000_0001 SDO_VBI 0xF000_0014 R W VBI Configuration Register 0x0007_77FF SDO_SCALE_CH0 0xF000_001C R W Scale Control Register for DAC Chann...

Page 1349: ..._0014 SDO_CB8 0xF000_00A0 R W CB AAF 9 th and 15 th Coefficient 0x0000_0028 SDO_CB9 0xF000_00A4 R W CB AAF 10 th and 14 th Coefficient 0x0000_003F SDO_CB10 0xF000_00A8 R W CB AAF 11 th and 13 th Coefficient 0x0000_0052 SDO_CB11 0xF000_00AC R W CB AAF 12 th Coefficient 0x0000_005A SDO_CR0 0xF000_00C0 R W CR AAF 1 st and 23 th Coefficient 0x0000_0000 SDO_CR1 0xF000_00C4 R W CR AAF 2 nd and 22 th Coe...

Page 1350: ...0 0x00F7_00FA SDO_OSFC05_0 0xF000_0214 R W OSF Coefficient 11 10 of Channel 0 0x0000_0001 SDO_OSFC06_0 0xF000_0218 R W OSF Coefficient 13 12 of Channel 0 0x000E_000A SDO_OSFC07_0 0xF000_021C R W OSF Coefficient 15 14 of Channel 0 0x0000_01FF SDO_OSFC08_0 0xF000_0220 R W OSF Coefficient 17 16 of Channel 0 0x01EC_01F2 SDO_OSFC09_0 0xF000_0224 R W OSF Coefficient 19 18 of Channel 0 0x0000_0001 SDO_OS...

Page 1351: ...f Channel 1 0x0000_0001 SDO_OSFC10_1 0xF000_02E8 R W OSF Coefficient 21 20 of Channel 1 0x001D_0014 SDO_OSFC11_1 0xF000_02EC R W OSF Coefficient 23 22 of Channel 1 0x0000_01FE SDO_OSFC12_1 0xF000_02E0 R W OSF Coefficient 25 24 of Channel 1 0x03D8_03E4 SDO_OSFC13_1 0xF000_02F4 R W OSF Coefficient 27 26 of Channel 1 0x0000_0002 SDO_OSFC14_1 0xF000_02F8 R W OSF Coefficient 29 28 of Channel 1 0x0038_0...

Page 1352: ...xF000_035C R W OSF Coefficient 31 30 of Channel 2 0x0000_03FD SDO_OSFC16_2 0xF000_0360 R W OSF Coefficient 33 32 of Channel 2 0x03B0_03C7 SDO_OSFC17_2 0xF000_0364 R W OSF Coefficient 35 34 of Channel 2 0x0000_0005 SDO_OSFC18_2 0xF000_0368 R W OSF Coefficient 37 36 of Channel 2 0x0079_0056 SDO_OSFC19_2 0xF000_036C R W OSF Coefficient 39 38 of Channel 2 0x0000_03F6 SDO_OSFC20_2 0xF000_0370 R W OSF C...

Page 1353: ...TVOUT VIDEO DAC S5PC100 USER S MANUAL REV1 0 9 7 32 ...

Page 1354: ...mally this bit is 0 After SDO_CLKCON 0 bit is 0 if the internal line counter and pixel counter are 0 just before starting line 1 this bit will be 1 0 SDO clock on 0 This bit determines run stop mode of TVOUT 0 TVOUT clock off TVOUT requests for clock down to host controller If SDO is ready for clock down SDO_CLKCON 1 bit will be 1 The host controller should stop the clock for the TVOUT after that ...

Page 1355: ...for DAC 1 19 18 If bit 5 is set to YpbPr 0 Y signal 1 Pb signal 2 Pr signal Otherwise 0 G signal 1 B signal 2 R signal 1 Selection of Video Mux for DAC 0 17 16 If bit 5 is set to YpbPr 0 Y signa 1 Pb signal 2 Pr signal Otherwise 0 G signal 1 B signal 2 R signal 0 Reserved 15 14 Reserved read as zero do not modify 0 Selection of Video Mux for DAC 2 13 12 0 CVBS signal 1 Y signal 2 C signal 2 Select...

Page 1356: ...Outputs 5 0 RGB 1 YPbPr This setting is valid if bit 6 is set to be component 1 Selection of Video Scan for Component Output 4 0 Interlaced 1 Progressive The scan rate of video output is not changed if bit 6 is set to be component But the setting of this bit has an impact on pixel requests If they are working in interlaced scan mode this bit should be also set Interlaced 1 Selection of Video Stand...

Page 1357: ...FIG register is set to component 0 Video to Sync Ratio Selection for YpbPr RGB Component 2 0 10 4 1 7 3 This setting is valid if bit 6 of SDO_CONFIG register is set to component 1 Setup Level Selection for Composite S Video 1 0 0 IRE 1 7 5 IRE This setting is valid if bit 6 of SDO_CONFIG register is set to composite 1 Video to Sync Ratio Selection for Composite S Video 0 0 10 4 1 7 3 This setting ...

Page 1358: ...86 525 Line Betacam 1 R Y B Y 0 467 7 5 setup on Y 100 saturation three wire Y sync R Y B Y Y 0 700 sync 0 300 625 Line Betacam 1 R Y B Y 0 350 0 setup on Y 100 saturation three wire Y sync R Y B Y Y 0 700 sync 0 300 525 Line MII 2 R Y B Y 0 324 7 5 setup on Y 100 saturation three wire Y sync R Y B Y Y 0 700 sync 0 300 625 Line MII 2 R Y B Y 0 350 0 setup on Y 100 saturation three wire Y sync R Y ...

Page 1359: ...010 SDO_SYNC Bit Description Reset Value Reserved 31 2 Reserved read as zero do not modify 0 Configuration Sync Insertion for YpbPr RGB Component Video 1 0 0 Sync pulse is absent 1 Sync pulse is delivered only on Y channel or G channel 2 Reserved 3 Sync pulses are delivered on all the Y Pb Pr channels or G B R channels This setting is valid if bit 6 of SDO_CONFIG register is set to component For Y...

Page 1360: ...f the Selection of Video Standard in SDO_CONFIG Register is set to NTSC M PAL M PAL 60 or NTSC 4 43 0 No Ancillary Data Insertion 1 US Closed Caption Insertion at 21H 2 US Closed Caption Insertion at 21H and 284H 3 Reserved for Other Use Otherwise No Ancillary Data Insertion NOTE This setting is valid if the bit 6 of SDO_CONFIG register is set to composite NOTE European closed caption is not suppo...

Page 1361: ... NTSC 4 43 0 No Ancillary Data Insertion 1 CGMS A Insertion at 41H Otherwise 0 No Ancillary Data Insertion 1 CGMS A Insertion at 43H For RGB component video the VBI data are delivered on the same channel as the sync pulses are delivered This setting is valid if the SDO_CONFIG register is set to progressive scan component RGB video 1 Wide Screen Signaling Configuration for Interlaced RGB Video 6 If...

Page 1362: ...n SDO_CONFIG Register is set to NTSC M PAL M PAL 60 or NTSC 4 43 0 No Ancillary Data Insertion 1 CGMS A Insertion at 41H Otherwise 0 No Ancillary Data Insertion 1 CGMS A Insertion at 43H For YpbPr component video the VBI data are delivered on the same channel as the sync pulses are delivered on This setting is valid if the SDO_CONFIG register is set to progressive scan component YpbPr video 1 Wide...

Page 1363: ...NTSC M PAL M PAL 60 or NTSC 4 43 0 No Ancillary Data Insertion 1 US Closed Caption Insertion at 21H 2 US Closed Caption Insertion at 21H and 284H 3 Reserved for Other Use Otherwise No Ancillary Data Insertion For YpbPr component video the VBI data are delivered on the same channel as the sync pulses are delivered on This setting is valid if the SDO_CONFIG register is set to interlaced scan compone...

Page 1364: ...LE CONTROL REGISTER SDO_SCALE_CH0 R W ADDRESS 0XF000_ 001C OSF_ 0 OSF_ 1 OSF_ 2 Gain_CH0 Y_data C_data CVBS_data Y_G_data Pb_B_data Pr_R_data SEL_DAC_OUT SEL_COMPONENT DAC 0 DAC 1 DAC 2 Gain_CH1 Gain_CH2 Figure 9 7 20 Individual Gain Offset Control for DAC Channel Balancing ...

Page 1365: ...set Gain 0x1FF 511 0x001 1 0x000 0 0x3FF 1 0x200 512 This setting is valid if the bit 6 of SDO_CONFIG register is set to component 000 Reserved 15 12 Reserved read as zero do not modify 0 Gain of Channel 0 Signal Scale Conversion 11 0 Function F x X Offset Gain 0x000 x0 0 0x400 x0 5 0x800 x1 0 0xC00 x1 5 0xFFF x1 999512 2048 2 1 2048 This setting is valid if the bit 6 of SDO_CONFIG register is set...

Page 1366: ...cale Conversion 25 16 Function F x X Offset Gain 0x1FF 511 0x001 1 0x000 0 0x3FF 1 0x200 512 This setting is valid if the bit 6 of SDO_CONFIG register is set to component 000 Reserved 15 12 Reserved read as zero do not modify 0 Gain of channel 1 Signal Scale Conversion 11 0 Function F x X Offset Gain 0x000 x0 0 0x400 x0 5 0x800 x1 0 0xC00 x1 5 0xFFF x1 999512 2048 2 1 2048 This setting is valid if...

Page 1367: ...cale Conversion 25 16 Function F x X Offset Gain 0x1FF 511 0x001 1 0x000 0 0x3FF 1 0x200 512 This setting is valid if the bit 6 of SDO_CONFIG register is set to component 000 Reserved 15 12 Reserved read as zero do not modify 0 Gain of channel 2 Signal Scale Conversion 11 0 Function F x X Offset Gain 0x000 x0 0 0x400 x0 5 0x800 x1 0 0xC00 x1 5 0xFFF x1 999512 2048 2 1 2048 This setting is valid if...

Page 1368: ...tion 15 8 0x3F 4 667 usec 0x01 0 074 usec 0x00 0 000 usec 0xFF 0 074 usec 0x40 4 741 usec FA Offset of Video Active End Position 7 0 0x3F 4 667 usec 0x01 0 074 usec 0x00 0 000 usec 0xFF 0 074 usec 0x40 4 741 usec 00 5 10 SDO SCH PHASE CONTROL REGISTER SDO_SCHLOCK R W ADDRESS 0XF000_ 0038 SDO_SCHLOCK Bit Description Reset Value Reserved 31 1 Reserved read as zero do not modify 0 Color Sub Carrier P...

Page 1369: ...ically power down to save a static current 35mA The mode all DAC power down and only BGR generation circuit alive does not exist 5 12 SDO STATUS REGISTER SDO_FINFO R ADDRESS 0XF000_ 0040 SDO_FINFO Bit Description Reset Value Reserved 31 26 Reserved read as zero do not modify 0 Field Counter Modulo 1001 25 16 This counter is used for 59 94 60 0 Hz field rate conversion 0 Reserved 15 2 Reserved read...

Page 1370: ...R W Address 0xF000_ 0080 5 13 14 SDO Anti Aliasing Filter Coefficients SDO_CB1 R W Address 0xF000_ 0084 5 13 15 SDO Anti Aliasing Filter Coefficients SDO_CB2 R W Address 0xF000_ 0088 5 13 16 SDO Anti Aliasing Filter Coefficients SDO_CB3 R W Address 0xF000_ 008C 5 13 17 SDO Anti Aliasing Filter Coefficients SDO_CB4 R W Address 0xF000_ 0090 5 13 18 SDO Anti Aliasing Filter Coefficients SDO_CB5 R W A...

Page 1371: ...uch a way that total sum of filter coefficients should be equal to a predefined constant Otherwise DC component of filter output would be re scaled from the original one The value of the constant depends on the setting of SDO_SCALE register for Y channel 0x251 at 7 5 IRE setup and 7 3 ratio 0x25D at 7 5 IRE setup and 10 4 ratio 0x281 at 0 IRE setup and 7 3 ratio 0x28F at 0 IRE setup and 7 3 ratio ...

Page 1372: ...s The RGB color compensation imposes a transform operation on the YcbCr data which become to have ill defined values at transformation into RGB format i e values over the range 16 235 for R G and B The brightness and hue would be maintained but saturation reduced appropriately after the transformation 0 On Off Control of YC Color Compensation 1 0 On 1 Bypass The YC color compensation imposes a sat...

Page 1373: ...0 0x80 1 0 0xFF 1 992188 128 2 1 128 This setting is valid for all the CVBS Y C YpbPr RGB outputs 80 Reserved 15 9 Reserved read as zero do not modify 0 Offset of Brightness Control with 8 0 F Y Gain Y Offset 0x0FF 255 0x001 1 0x000 0 0x1FF 1 0x100 256 This setting is valid for all the CVBS Y C YpbPr RGB outputs 00 ...

Page 1374: ...ion Control of CB with F CB CR CB Gain0 CR Gain1 Offset 0x0FF 1 992188 128 2 1 128 0x080 1 0 0x000 0 0 0x180 1 0 0x100 2 0 This setting is valid for all the CVBS Y C YpbPr RGB outputs 80 Reserved 15 9 Reserved read as zero do not modify 0 Gain1_CB 8 0 Gain1 of Hue Saturation Control of CB with F CB CR CB Gain0 CR Gain1 Offset 0x0FF 1 992188 128 2 1 128 0x080 1 0 0x000 0 0 0x180 1 0 0x100 2 0 This ...

Page 1375: ...ion Control of CR with F CB CR CB Gain0 CR Gain1 Offset 0x0FF 1 992188 128 2 1 128 0x080 1 0 0x000 0 0 0x180 1 0 0x100 2 0 This setting is valid for all the CVBS Y C YpbPr RGB outputs 00 Reserved 15 9 Reserved read as zero do not modify 0 Gain1_CR 8 0 Gain1 of Hue Saturation Control of CR with F CB CR CB Gain0 CR Gain1 Offset 0x0FF 1 992188 128 2 1 128 0x080 1 0 0x000 0 0 0x180 1 0 0x100 2 0 This ...

Page 1376: ...CVBS Y C YpbPr RGB outputs 00 Reserved 15 10 Reserved read as zero do not modify 0 Offset_CB 9 0 Offset of Hue Saturation Control of CB with 0x1FF 511 0x001 1 0x000 0 0x3FF 1 0x200 512 This setting is valid for all the CVBS Y C YpbPr RGB outputs 00 5 19 COLOR COMPENSATION CONTROL REGISTER FOR RGB OUTPUT SDO_RGB_CC R W ADDRESS 0XF000_0194 SDO_RGB_CC Bit Description Reset Value Reserved 31 1 Reserve...

Page 1377: ...5PC100 USER S MANUAL REV1 0 9 7 56 It should be set such that Max_RGB_ Cube 15 8 Max_RGB_Cube 7 0 It is highly recommended for users not to alter their reset values This setting is valid only if SDO_CCCON 2 is set to On ...

Page 1378: ...CC_Y2 Bit Description Reset Value Reserved 31 26 Reserved read as zero do not modify 0 Y_Top_CVBS_Corn 25 16 Top Y Boundary of Legal CVBS Corn 0x3FF 1023 0x000 0 3FF 15 10 Reserved read as zero do not modify 0 Y_Upper_Mid_CVBS_Corn 9 0 Upper mid Y Boundary of Legal CVBS Corn 0x3FF 1023 0x000 0 200 5 22 COLOR COMPENSATION CONTROL REGISTER FOR CVBS OUTPUT SDO_CVBS_CC_C R W ADDRESS 0XF000_ 01A0 SDO_C...

Page 1379: ... as zero do not modify 0 Y_Bottom_YC_Cylinde r 9 0 Bottom Y Boundary of Legal YC Cylinder 0x3FF 1023 0x000 0 0 5 24 COLOR COMPENSATION CONTROL REGISTER FOR S VIDEO OUTPUT SDO_YC_CC_C R W ADDRESS 0XF000_ 01A8 SDO_YC_CC_C Bit Description Reset Value Reserved 31 9 Reserved read as zero do not modify 0 Radius_YC_Cylinder 8 0 Radius of Legal YC Cylinder 0x1FF 511 0x000 0 1FF It should be set such that ...

Page 1380: ...ssive 1 27MHz resolution in interlaced 1 13 5MHz Compare line count value with porch position 5 26 SDO 625 LINE COMPONENT FRONT BACK PORCH POSITION CONTROL RESIGTER SDO_CSC_625_PORCH R W ADDRESS 0XF000_ 01B4 SDO_CSC_625_PORCH Bit Description Reset Value Reserved 31 26 Reserved read as zero do not modify 0 625 line back porch position 25 16 Back porch start position 96 Reserved 15 10 Reserved read ...

Page 1381: ...eserved 7 5 Reserved read as zero do not modify 0 Polarity Control for VSYNC Output 4 0 Low active 1 High active 0 Reserved 3 1 Reserved read as zero do not modify 0 Polarity Control for HSYNC Output 0 0 Low active 1 High active 0 5 28 SDO OVERSAMPLING 0 FILTER COEFFICIENT SDO_OSFC00_0 R W ADDRESS 0XF000_ 0200 SDO_OSFCN_0 N is 00 23 Bit Description Reset Value osf_coef 2xN 1 23 16 27 16 2xN 1 th o...

Page 1382: ...ilter Coefficient SDO_OSFC13_0 R W Address 0xF000_ 0234 5 28 14 SDO Oversampling 0 Filter Coefficient SDO_OSFC14_0 R W Address 0xF000_ 0238 5 28 15 SDO Oversampling 0 Filter Coefficient SDO_OSFC15_0 R W Address 0xF000_ 023C 5 28 16 SDO Oversampling 0 Filter Coefficient SDO_OSFC16_0 R W Address 0xF000_ 0240 5 28 17 SDO Oversampling 0 Filter Coefficient SDO_OSFC17_0 R W Address 0xF000_ 0244 5 28 18 ...

Page 1383: ...9 11 SDO Oversampling 1 Filter Coefficient SDO_OSFC11_1 R W Address 0xF000_ 02EC 5 29 12 SDO Oversampling 1 Filter Coefficient SDO_OSFC12_1 R W Address 0xF000_ 02F0 5 29 13 SDO Oversampling 1 Filter Coefficient SDO_OSFC13_1 R W Address 0xF000_ 02F4 5 29 14 SDO Oversampling 1 Filter Coefficient SDO_OSFC14_1 R W Address 0xF000_ 02F8 5 29 15 SDO Oversampling 1 Filter Coefficient SDO_OSFC15_1 R W Addr...

Page 1384: ...ing 2 Filter Coefficient SDO_OSFC09_2 R W Address 0xF000_ 0344 5 30 10 SDO Oversampling 2 Filter Coefficient SDO_OSFC10_2 R W Address 0xF000_ 0348 5 30 11 SDO Oversampling 2 Filter Coefficient SDO_OSFC11_2 R W Address 0xF000_ 034C 5 30 12 SDO Oversampling 2 Filter Coefficient SDO_OSFC12_2 R W Address 0xF000_ 0350 5 30 13 SDO Oversampling 2 Filter Coefficient SDO_OSFC13_2 R W Address 0xF000_ 0354 5...

Page 1385: ...osf_coef20 20 osf_coef36 86 osf_coef05 5 osf_coef21 29 osf_coef37 121 osf_coef06 1 osf_coef22 2 osf_coef38 10 osf_coef07 0 osf_coef23 0 osf_coef39 0 osf_coef08 6 osf_coef24 28 osf_coef40 154 osf_coef09 9 osf_coef25 40 osf_coef41 212 osf_coef10 1 osf_coef26 2 osf_coef42 27 osf_coef11 0 osf_coef27 0 osf_coef43 0 osf_coef12 10 osf_coef28 40 osf_coef44 613 osf_coef13 14 osf_coef29 56 osf_coef45 651 os...

Page 1386: ...ef09 0 osf_coef25 0 osf_coef41 0 osf_coef10 0 osf_coef26 5 osf_coef42 120 osf_coef11 0 osf_coef27 0 osf_coef43 0 osf_coef12 0 osf_coef28 8 osf_coef44 211 osf_coef13 0 osf_coef29 0 osf_coef45 0 osf_coef14 0 osf_coef30 13 osf_coef46 650 osf_coef15 0 osf_coef31 0 osf_coef47 1024 5 32 SDO CHANNEL CROSSTALK CANCELLATION COEFFICIENT FOR CH 0 SDO_XTALK0 R W ADDRESS 0XF000_ 0260 SDO_XTALK0 Bit Description...

Page 1387: ...5 35 SDO BLACK BURST CONTROL REGISTER SDO_BB_CTRL R W ADDRESS 0XF000_ 026C SDO_XTALK2 Bit Description Reset Value Reserved 31 18 Reserved read as zero do not modify 0 ref_bb_level 17 8 Black level setting value It specifies the level during horizontal active video for black burst signal The recommended values are NTSC 0x11A include 7 5 IRE setup PAL 0xFB without setup 0x11A Reserved 7 6 Reserved r...

Page 1388: ...erted even if the request is disabled Only the request to MCU will be disabled 0 5 38 SDO CLOSED CAPTION DATA REGISTERS SDO_ARMCC R W ADDRESS 0XF000_ 03C0 SDO_ARMCC Bit Description Reset Value Reserved 31 16 Reserved read as zero do not modify 0 Display Control Character of Closed Caption Data 15 8 Bit alignment of the Display Control Character register is in their incoming order The first incomin...

Page 1389: ...ister is according to their incoming order The first incoming bit becomes LSB i e Word 2 13 6 b13 b12 b11 b10 b9 b8 b7 b6 where bn represents data bit with their incoming order n The Word 2 data are used for copy control b7 b6 00 copying permitted 01 one copy permitted 10 reserved 11 no copying permitted b9 b8 reserved b10 not analog pre recorded medium analog pre recorded medium b13 b12 b11 reser...

Page 1390: ...ct ratio letterbox 11 reserved 0 5 40 SDO WSS 625 DATA REGISTERS SDO_ARMWSS625 R W ADDRESS 0XF000_ 03C8 SDO_ARMWSS625 Bit Description Reset Value Reserved 31 14 Reserved read as zero do not modify 0 Group D of WSS 625 Data 13 11 Bit alignment of the Group D register is according to their incoming order The first incoming bit becomes LSB i e Group D 13 11 b13 b12 b11 where bn represents data bit wi...

Page 1391: ...titles b8 teletext subtitles 0 no 1 yes b10 b9 open subtitles 00 no 01 inside active picture 10 outside active picture 11 reserved 0 Group B of WSS 625 Data 7 4 Bit alignment of the Group B register is according to their incoming order The first incoming bit becomes LSB i e Group B 7 4 b7 b6 b5 b4 where bn represents data bit with their incoming order n The Group B data are used for enhanced video...

Page 1392: ...SB i e Group A 3 0 b3 b2 b1 b0 where bn represents data bit with their incoming order n The Group A data are used for display aspect ratio control b3 b2 b1 b0 1000 4 3 full format 576 lines 0001 14 9 letterbox center 504 lines 0010 14 9 letterbox top 504 lines 1011 16 9 letterbox center 430 lines 0100 16 9 letterbox top 430 lines 1101 16 9 letterbox center 1110 14 9 full format center 576 lines 01...

Page 1393: ... register is according to their incoming order The first incoming bit becomes LSB i e Word 2 13 6 b13 b12 b11 b10 b9 b8 b7 b6 where bn represents data bit with their incoming order n The Word 2 data are used for copy control b7 b6 00 copying permitted 01 one copy permitted 10 reserved 11 no copying permitted b9 b8 reserved b10 No analog pre recorded medium analog pre recorded medium b13 b12 b11 re...

Page 1394: ... ratio letterbox 11 reserved 0 5 42 SDO CGMS A 625 DATA REGISTERS SDO_ARMCGMS625 R W ADDRESS 0XF000_ 03D4 SDO_ARMCGMS625 Bit Description Reset Value Reserved 31 14 Reserved read as zero do not modify 0 Group D of CGMS A 625 Data 13 11 Bit alignment of the Group D register is according to their incoming order The first incoming bit becomes LSB i e Group D 13 11 b13 b12 b11 where bn represents data ...

Page 1395: ...titles b8 teletext subtitles 0 no 1 yes b10 b9 open subtitles 00 no 01 inside active picture 10 outside active picture 11 reserved 0 Group B of CGMS A 625 Data 7 4 Bit alignment of the Group B register is according to their incoming order The first incoming bit becomes LSB i e Group B 7 4 b7 b6 b5 b4 where bn represents data bit with their incoming order n The Group B data are used for enhanced vi...

Page 1396: ...r n The Group A data are used for display aspect ratio control b3 b2 b1 b0 1000 4 3 full format 576 lines 0001 14 9 letterbox center 504 lines 0010 14 9 letterbox top 504 lines 1011 16 9 letterbox center 430 lines 0100 16 9 letterbox top 430 lines 1101 16 9 letterbox center 1110 14 9 full format center 576 lines 0111 16 9 anamorphic 576 lines 0 5 43 SDO VERSION REGISTER SDO_VERSION R ADDRESS 0XF00...

Page 1397: ...ng shadow registers which are named with SDO_XXX at the next vertical sync interrupt Then the values become effective during VBI interval at the next field Please avoid setting direct value to these shadow resigers 6 1 SDO CLOSED CAPTION DATA SHADOW REGISTER SDO_CC R W ADDRESS 0XF000_ 0380 SDO_CC Bit Description Reset Value Reserved 31 16 Reserved read as zero do not modify 0 Display Control Chara...

Page 1398: ...eset Value Reserved 31 20 Reserved read as zero do not modify 0 CRC of CGMS A 525 Data 19 14 0 Word 2 of CGMS A 525 Data 13 6 0 Word 1 of CGMS A 525 Data 5 2 0 Word 0 of CGMS A 525 Data 1 0 If MCU set values of SDO_ARMCGMS525 the values are copied into this shadow register at the next vertical sync interrupt Do not set values to this shadow register 0 6 5 SDO CGMS A 625 DATA REGISTERS SDO_CGMS625 ...

Page 1399: ... output currents of 6 5mA at one channel with 200 ohm load for 1 3V The dac6620t_50p has a power down mode to reduce power consumption during inactive periods 7 2 FEATURES y 65nm Low Power Process y Maximum 54MHz Update Rate y 10 bit Current Output DAC y 1 3Vpp Triple Output Compliance Range y Internal Voltage Reference y Fine Full Scale control 91 1 114 8 y Power Down Mode Low Active 7 3 TYPICAL ...

Page 1400: ... 9 0 CLK CK2 CK1 PD3 1st Latch Decoder Buffer 2nd Latch Current Cell Matrix CK2 CK1 PD2 1st Latch Decoder Buffer 2nd Latch Current Cell Matrix Reference CLK Driver CK2 CK1 PD1 VREF ICH1 CTRL PWDN 3 1 CMREF FS 2 0 PD3 PD2 PD1 IREF AMP VREF BGR PD COMP SIN1 AVSS12D SIN2 SIN1 SIN2 COMP SIN1 SIN2 COMP AVDD30A1 AVDD30A2 AVSS30A2 AVSS30A1 COMP SIN1 SIN2 ICH1 Figure 9 7 21 Block Diagram of Video DAC ...

Page 1401: ...30A1 IOUT1 IOUT2 IOUT3 AO DAC current output Full scale output is achieved if all input bits are set to binary 1 COMP AO Compensation Pin This is a compensation pin for the internal reference amplifier A 0 1uF ceramic capacitor must be connected between COMP and AVDD30A1 AVDD30A1 AVDD30A2 AP Analog Supply Voltage Accepts a supply voltage range of 2 7V to 3 3V AVSS30AR AVSS30A2 AG Analog Ground for...

Page 1402: ...sed through its end points The difference between the ideal and actual characteristics is called the INL profile 7 6 2 Differential Non Linearity or DLE DNL is the maximum deviation in the output step size from the ideal value of one least significant bit 7 6 3 Monotonicity A D A converter is monotonic if the output either increases or remains constants as the digital input increases 7 6 4 Offset ...

Page 1403: ...001 31 32 96 8 010 31 33 93 9 011 31 34 91 1 100 31 27 114 8 101 31 28 110 7 110 31 29 106 8 111 31 30 103 3 7 7 RECOMMENDED OPERATING CONDITIONS Table 9 7 10 Operating Conditions Characteristics Symbol Min Typ Max Unit AVDD30A1 AVDD30A2 AVDD30D 2 7 3 0 3 3 V Operating Supply Voltage AVDD12D 0 99 1 2 1 32 V Operating Temperature Range Top 40 85 C ...

Page 1404: ... Typ Max Unit Resolution Bit 10 Bits Differential linearity error DNL 1 LSB Integral linearity error INL 3 LSB Monotonicity Guaranteed Reference Voltage VVREF 1 26 V Maximum Output Compliance VOC 1 43 V Full Scale Output Current Per Channel IFS 5 85 6 5 7 15 mA Full Scale Output Voltage VFS 1 17 1 3 1 43 V Operating Current IOP 19 23 27 mA Power Down Current IPD 0 100 uA Y Channel Pb Channel CBYPB...

Page 1405: ...og Output Fall Time TF 5 ns Setup Time TS 4 nsec Hold time TH 4 nsec PSRR PSRR 44 40 dB Y Channel Pb Channel XYPB 50 40 dB Y Channel Pr Channel XYPR 50 40 dB Crosstalk Pb Channel Pr Channel XPBPR 50 40 dB SNR SNR 45 51 dB SFDR Spurious Free Dynamic Range Fout 1MHz Fclk 54MHz SFDR 60 50 dBc NOTE 1 Analog output delay analog output rise fall time and Setup Hold time are simulation values not a test ...

Page 1406: ...g Conversion NOTES 1 Output delay is measured from the 50 point of the rising edge of CLK to the full scale transition 2 Settling time is measured from the 50 point of full scale transition to the output remaining within 0 1 3 Output rise fall time is measured between the 10 and 90 points of full scale transition Digital Input D 9 0 CLK Analog Output VO 0000000000 0000000000 1111111111 90 10 Tr Tf...

Page 1407: ...2 9 0 D3 9 0 VREF 1 26 V Cc Ct PWR AVDD30A1 AVSS30A1 GND 3 0V RLOAD RLOAD IOUT1 IOUT3 GND PWR IREF GND R SET COMP 3 0V Cc AVDD12D AVSS12D GND 1 2V PWR IOUT2 RLOAD GND AVDD30D AVSS30D GND 3 0V PWR GND CLK PWDN 3 1 AVDD30A2 AVSS30A2 GND 3 0V PWR 6 34kohm FS 2 0 Figure 9 7 24 Recommended Board Configuration ...

Page 1408: ...on Ct 10uF tantalum capacitor Tolerance 10 Cc 0 1uF ceramic capacitor Tolerance 10 RSET 6 34 KΩ or 8 3 KΩ Tolerance 1 RLOAD 200Ω Tolerance 1 7 11 1 Full Scale Voltage Modification Table 9 7 14 Recommended RSET and RO According to Full Scale Voltage Full Scale Voltage RSET RO 1 3V 6 34KΩ 200Ω 1 0V 8 3KΩ 200Ω ...

Page 1409: ... by non ideal interpolation filter is basically implies distortions in chrominance components However in the case of CVBS signal the chrominance component and the luminance component are together to be mixed and transmitted via one channel Then parts of the interpolation error appears in luminance parts if the CVBS signal is separated into luminance component and chrominance components by the comb...

Page 1410: ...pecification BOB 2D TILE YUV420 NV12 type Note refer to MFC user s manual for 2D TILE Input source size up to 1280x720 min 32x4 Produce YCbCr 4 4 4 outputs to help MIXER to blend video and graphics Supports 1 4X to 16X vertical scaling with 4 tap 16 phase poly phase filter Supports 1 4X to 16X horizontal scaling with 8 tap 16 phase poly phase filter Supports Pan Scan Letterbox and NTSC PAL convers...

Page 1411: ...4 8bits 32 1280 4 bytes YUV 4 2 0 8bits Figure 9 8 2 Block Diagram of Video Processor DMA DMA reads the image from memory Input Line Memory It stores data for processing the image Registers The configuration of Video Processor 2D IPC and Vertical Scaler It does IPC and vertical scaling Horizontal Scaler Horizontal scaling and post processing ...

Page 1412: ... and intra field processing Particular Intra field processing in video mode is the simplest method for generating additional scan lines using only information in the original field The computer industry has coined this technique as BOB But BOB in VP consists of Intra field or inter field Inter field comes from a frame as Figure 9 8 3 a Also Intra field is made up fields that come from two frames a...

Page 1413: ... S5PC100 USER S MANUAL REV1 0 9 8 4 Figure 9 8 4 The Concept of BOB IPC engine executes Edge Detection Function which is based on the edge diagnosis method So IPC can estimate edge line and display more natural image ...

Page 1414: ...IDTH 0xF010_004C R W Width of the Source Image 0x0000_0000 VP_SRC_HEIGHT 0xF010_0050 R W Height of the Source Image 0x0000_0000 VP_DST_H_POSITION 0xF010_0054 R W Horizontal Offset in the Display 0x0000_0000 VP_DST_V_POSITION 0xF010_0058 R W Vertical Offset in the Display 0x0000_0000 VP_DST_WIDTH 0xF010_005C R W Width of the Display 0x0000_0000 VP_DST_HEIGHT 0xF010_0060 R W Height of the Display 0x...

Page 1415: ..._Y0_LH 0xF010_00F0 R W 4 Tap Poly phase Filter Coefficients for Luminance Vertical Scaling 0x0000_0000 VP_POLY4_Y0_HL 0xF010_00F4 R W 4 Tap Poly phase Filter Coefficients for Luminance Vertical Scaling 0x0000_0000 VP_POLY4_Y0_HH 0xF010_00F8 R W 4 Tap Poly phase Filter Coefficients for Luminance Vertical Scaling 0x0000_0000 VP_POLY4_Y1_LL 0xF010_00FC R W 4 Tap Poly phase Filter Coefficients for Lum...

Page 1416: ...oefficient Setting 0x0000_0000 PP_CSC_CB2Y_COEF 0xF010_01D8 R W CB to Y CSC Coefficient Setting 0x0000_0000 PP_CSC_CR2Y_COEF 0xF010_01DC R W CR to Y CSC Coefficient Setting 0x0000_0000 PP_CSC_Y2CB_COEF 0xF010_01E0 R W Y to Y CSC Coefficient Setting 0x0000_0000 PP_CSC_CB2CB_COEF 0xF010_01E4 R W CB to Y CSC Coefficient Setting 0x0000_0000 PP_CSC_CR2CB_COEF 0xF010_01E8 R W CR to Y CSC Coefficient Set...

Page 1417: ...egister Address R W Description Reset Value PP_BRIGHT_OFFSET 0xF010_0238 R W Brightness Offset Control for Y 0x0000_0000 PP_CSC_EN 0xF010_023C R W Color Space Conversion Control 0x0000_0002 VP_VERSION_INFO 0xF010_03FC R VP Version Information 0x0000_0010 ...

Page 1418: ...VP_SRC_HEIGHT_S 0xF010_01B8 R Height of the Source Image 0x0000_0000 VP_DST_H_POSITION_S 0xF010_01BC R Horizontal Offset in the Display 0x0000_0000 VP_DST_V_POSITION_S 0xF010_01C0 R Vertical Offset in the Display 0x0000_0000 VP_DST_WIDTH_S 0xF010_01C4 R Width of the Display 0x0000_0000 VP_DST_HEIGHT_S 0xF010_01C8 R Height of the Display 0x0000_0000 VP_H_RATIO_S 0xF010_01CC R Horizontal Zoom Ratio ...

Page 1419: ...Coefficient Setting 0x0000_0000 PP_CSC_Y2CB_COEF_S 0xF010_029C R Y to Y CSC Coefficient Setting 0x0000_0000 PP_CSC_CB2CB_COEF_S 0xF010_02A0 R CB to Y CSC Coefficient Setting 0x0000_0000 PP_CSC_CR2CB_COEF_S 0xF010_02A4 R CR to Y CSC Coefficient Setting 0x0000_0000 PP_CSC_Y2CR_COEF_S 0xF010_02A8 R Y to Y CSC Coefficient Setting 0x0000_0000 PP_CSC_CB2CR_COEF_S 0xF010_02AC R CB to Y CSC Coefficient Se...

Page 1420: ...led 1 Enabled NOTE The SFRs of Video Processor and Image Mixer is updated by Vertical Sync of TVENC s Timing Generator So those are configured before this bit is enabled The sequence of enabling TVSS is following as VP MIXER TVENC HDMI Also because of the same reason the disabling sequence is following as VP MIXER TVNEC HDMI R W 0 4 3 2 Video Processor Software Reset VP_SRESET R W Address 0xF010_0...

Page 1421: ... Value Reserved 31 1 Reserved read as zero do not modify 0 VP_FILED_ID 0 When VP_MODE 2 is set to high this bit shows current FIELD information Otherwise when VP_MODE 2 is set to low this control the pointer of top and bottom field 0 Top field 1 Bottom field 0 4 3 5 Video Processor Operation Mode Control Register VP_MODE R W Address 0xF010_ 0010 VP_MODE Bit Description Reset Value Reserved 31 6 Re...

Page 1422: ... Reserved 0 Reserved It must be 0 0 The guide of Configuration 1 Interlace to Interlace 2 Interlaced to Progressive 3 Progressive to Interlace Progressive 4 Progressive to Progressive Progressive VSYNC Field ID VSYNC Field ID VSYNC Field ID VSYNC Field ID LINE_SKIP 2D_IPC FIELD_ID_AUT O_TOGGLE FIELD_ID 1 On 0 Disable 1 Auto don t care 0 Off 0 Disable 1 Auto don t care 1 On 1 Enable 0 By user 0 Top...

Page 1423: ...re not allowed 0 Reserved 15 14 Reserved read as zero do not modify 0 VP_IMG_VSIZE_Y 13 0 Vertical size of image 1 8192 0 4 3 6 Video Processor Chrominance Image Size Control Register VP_IMG_SIZE_C R W Address 0xF010_ 0018 VP_ IMG _SIZE_C Bit Description Reset Value Reserved 31 30 Reserved read as zero do not modify 0 VP_IMG_HSIZE_C 29 16 Horizontal size of image 8 8192 Without minus 1 LSB 2 0 mus...

Page 1424: ...ideo Processor Top Chrominance Picture Pointer Control Register VP_TOP_C_PTR R W Address 0xF010_0030 VP_CR_PTR Bit Description Reset Value VP_TOP_C_PTR 31 0 Base address for chrominance of top field It should be integer multiples of 8 LSB 2 0 must be 3 b000 0 4 3 10 Video Processor Bottom Chrominance Picture Pointer Control Register VP_BOT_C_PTR R W Address 0xF010_ 0034 VP_BOT_Y_PTR Bit Descriptio...

Page 1425: ...o not modify 0 VP_SRC_H_POSITION 14 0 Horizontal offset in the source image 11 4 format For source image cropping VP_SRC_H_POSITION VP_SRC_WIDTH should be less than or equal to VP_IMG_HSIZE_Y Note 11 4 format means that 11 is a integer 4 is a fraction Example In case of H Position 4 4 0x4 h 0100 b is integer Because of 4bit fraction 0100 b is had to do 4 time left shift operation As a result regis...

Page 1426: ...HEIGHT 9 0 Height of the source image If LINE_SKIP is 1 VP_SRC_HEIGHT should be a half of that if LINE_SKIP is 0 MIN 4 0 4 3 17 Video Processor Horizontal Offset of Destination Image Control Register VP_DST_H_POSITION R W Address 0xF010_ 0054 VP_DST_H_POSITION Bit Description Reset Value Reserved 31 11 Reserved read as zero do not modify 0 VP_DST_H_POSITION 10 0 Horizontal offset in the display 0 ...

Page 1427: ...8 18 4 3 20 Video Processor Height of Destination Image Control Register VP_DST_HEIGHT R W Address 0xF010_ 0060 VP_DST_HEIGHT Bit Description Reset Value Reserved 31 10 Reserved read as zero do not modify 0 VP_DST_HEIGHT 9 0 Height of the display 0 ...

Page 1428: ... 8 19 NOTE VP_DST_H_POSITION VP_DST_V_POSITION picture height picture width VP_SRC_HEIGHT VP_SRC_WIDTH VP_DST_HEIGHT VP_DST_WIDTH Arbitrary Scaling Positioning VP_SRC_H_POSITION VP_SRC_V_POSITION Figure 9 8 7 Video Scaling Positioning on TV Display ...

Page 1429: ...value is 1 2 2 16 0x8000 0 4 3 22 Video Processor Vertical Zoom Ratio VP_V_RATIO R W Address 0xF010_ 0068 VP_V_RATIO Bit Description Reset Value Reserved 31 19 Reserved read as zero do not modify 0 VP_V_RATIO 18 0 Vertical zoom ratio of SRC DST 3 16 format This register should be as follows 1 BOB mode IPC disable VP_V_RATIO SRC DST 2 BOB mode IPC enable VP_V_RATIO 2 SRC DST This is because destina...

Page 1430: ... 27 Reserved read as zero do not modify 0 vp_poly8_y0_ph4 26 24 Poly phase Filter Coefficients 0 Reserved 23 19 Reserved read as zero do not modify 0 vp_poly8_y0_ph5 18 16 Poly phase Filter Coefficients 0 Reserved 15 11 Reserved read as zero do not modify 0 vp_poly8_y0_ph6 10 8 Poly phase Filter Coefficients 0 Reserved 7 3 Reserved read as zero do not modify 0 vp_poly8_y0_ph7 2 0 Poly phase Filter...

Page 1431: ... 31 29 Reserved read as zero do not modify 0 vp_poly8_y1_ph0 28 24 Poly phase Filter Coefficients 0 Reserved 23 21 Reserved read as zero do not modify 0 vp_poly8_y1_ph1 20 16 Poly phase Filter Coefficients 0 Reserved 15 13 Reserved read as zero do not modify 0 vp_poly8_y1_ph2 12 8 Poly phase Filter Coefficients 0 Reserved 7 5 Reserved read as zero do not modify 0 vp_poly8_y1_ph3 4 0 Poly phase Fil...

Page 1432: ...ved 31 29 Reserved read as zero do not modify 0 vp_poly8_y1_ph12 28 24 Poly phase Filter Coefficients 0 Reserved 23 21 Reserved read as zero do not modify 0 vp_poly8_y1_ph13 20 16 Poly phase Filter Coefficients 0 Reserved 15 13 Reserved read as zero do not modify 0 vp_poly8_y1_ph14 12 8 Poly phase Filter Coefficients 0 Reserved 7 5 Reserved read as zero do not modify 0 vp_poly8_y1_ph15 4 0 Poly ph...

Page 1433: ...d 31 Reserved read as zero do not modify 0 vp_poly8_y2_ph8 30 24 Poly phase Filter Coefficients 0 Reserved 23 Reserved read as zero do not modify 0 vp_poly8_y2_ph9 22 16 Poly phase Filter Coefficients 0 Reserved 15 Reserved read as zero do not modify 0 vp_poly8_y2_ph10 14 8 Poly phase Filter Coefficients 0 Reserved 7 Reserved read as zero do not modify 0 vp_poly8_y2_ph11 6 0 Poly phase Filter Coef...

Page 1434: ...ved 31 Reserved read as zero do not modify 0 vp_poly8_y3_ph4 30 24 Poly phase Filter Coefficients 0 Reserved 23 Reserved read as zero do not modify 0 vp_poly8_y3_ph5 22 16 Poly phase Filter Coefficients 0 Reserved 15 Reserved read as zero do not modify 0 vp_poly8_y3_ph6 14 8 Poly phase Filter Coefficients 0 Reserved 7 Reserved read as zero do not modify 0 vp_poly8_y3_ph7 6 0 Poly phase Filter Coef...

Page 1435: ...0 Reserved read as zero do not modify 0 vp_poly4_y0_ph0 29 24 Poly phase Filter Coefficients 0 Reserved 23 22 Reserved read as zero do not modify 0 vp_poly4_y0_ph1 21 16 Poly phase Filter Coefficients 0 Reserved 15 14 Reserved read as zero do not modify 0 vp_poly4_y0_ph2 13 8 Poly phase Filter Coefficients 0 Reserved 7 6 Reserved read as zero do not modify 0 vp_poly4_y0_ph3 5 0 Poly phase Filter C...

Page 1436: ...ved 31 30 Reserved read as zero do not modify 0 vp_poly4_y0_ph12 29 24 Poly phase Filter Coefficients 0 Reserved 23 22 Reserved read as zero do not modify 0 vp_poly4_y0_ph13 21 16 Poly phase Filter Coefficients 0 Reserved 15 14 Reserved read as zero do not modify 0 vp_poly4_y0_ph14 13 8 Poly phase Filter Coefficients 0 Reserved 7 6 Reserved read as zero do not modify 0 vp_poly4_y0_ph15 5 0 Poly ph...

Page 1437: ...d 31 Reserved read as zero do not modify 0 vp_poly4_y1_ph8 30 24 Poly phase Filter Coefficients 0 Reserved 23 Reserved read as zero do not modify 0 vp_poly4_y1_ph9 22 16 Poly phase Filter Coefficients 0 Reserved 15 Reserved read as zero do not modify 0 vp_poly4_y1_ph10 14 8 Poly phase Filter Coefficients 0 Reserved 7 Reserved read as zero do not modify 0 vp_poly4_y1_ph11 6 0 Poly phase Filter Coef...

Page 1438: ...ved 31 Reserved read as zero do not modify 0 vp_poly4_y2_ph4 30 24 Poly phase Filter Coefficients 0 Reserved 23 Reserved read as zero do not modify 0 vp_poly4_y2_ph5 22 16 Poly phase Filter Coefficients 0 Reserved 15 Reserved read as zero do not modify 0 vp_poly4_y2_ph6 14 8 Poly phase Filter Coefficients 0 Reserved 7 Reserved read as zero do not modify 0 vp_poly4_y2_ph7 6 0 Poly phase Filter Coef...

Page 1439: ...0 Reserved read as zero do not modify 0 vp_poly4_y3_ph0 29 24 Poly phase Filter Coefficients 0 Reserved 23 22 Reserved read as zero do not modify 0 vp_poly4_y3_ph1 21 16 Poly phase Filter Coefficients 0 Reserved 15 14 Reserved read as zero do not modify 0 vp_poly4_y3_ph2 13 8 Poly phase Filter Coefficients 0 Reserved 7 6 Reserved read as zero do not modify 0 vp_poly4_y3_ph3 5 0 Poly phase Filter C...

Page 1440: ...t modify 0 vp_poly4_y3_ph13 21 16 Poly phase Filter Coefficients 0 Reserved 15 14 Reserved read as zero do not modify 0 vp_poly4_y3_ph14 13 8 Poly phase Filter Coefficients 0 Reserved 7 6 Reserved read as zero do not modify 0 vp_poly4_y3_ph15 5 0 Poly phase Filter Coefficients 0 4 3 55 Video Processor Chrominance 4 tap Poly phase Filter Coefficients VP_POLY4_C0_LL R W Address 0xF010_ 012C Unlike V...

Page 1441: ...rved 31 30 Reserved read as zero do not modify 0 vp_poly4_c0_ph8 29 24 Signed 6 bit integer 32 31 0 Reserved 23 22 Reserved read as zero do not modify 0 vp_poly4_c0_ph9 21 16 Signed 6 bit integer 32 31 0 Reserved 15 14 Reserved read as zero do not modify 0 vp_poly4_c0_ph10 13 8 Signed 6 bit integer 32 31 0 Reserved 7 6 Reserved read as zero do not modify 0 vp_poly4_c0_ph11 5 0 Signed 6 bit integer...

Page 1442: ...signed 8 bit integer 0 255 0 4 3 61 Video Processor Chrominance 4 tap Poly phase Filter Coefficients VP_POLY4_C1_HL R W Address 0xF010_ 0144 VP_POLY4_C1_HL Bit Description Reset Value vp_poly4_c1_ph8 31 24 Unsigned 8 bit integer 0 255 0 vp_poly4_c1_ph9 23 16 Signed 8 bit integer 128 127 0 vp_poly4_c1_ph10 15 8 Signed 8 bit integer 128 127 0 vp_poly4_c1_ph11 7 0 Signed 8 bit integer 128 127 0 4 3 6...

Page 1443: ...9 0 983398 Cr709 y Above all equations are written without interface offsets of 16 for Luminance and 128 for Chrominance y CSC module calculates above all equations without 128 offset for Chrominance and generates final CSC results with 128 offset y In case of two Luminance equations 16 offset is selectable by control register PP_CSC_EN 1 If Y offset 16 exists in matrix input data the coefficient ...

Page 1444: ...rved read as zero do not modify 0 PP_CSC_Y2CB_COEF 11 0 BT 601 to BT 709 or BT 709 to BT 601 CSC coefficient for Y to CB 0 4 3 67 Video Processor Post processing Color Space Conversion Coefficient Register PP_CSC_CB2CB_COEF R W Address 0xF010_ 01E4 PP_CSC_CB2CB_COEF Bit Description Reset Value Reserved 31 12 Reserved read as zero do not modify 0 PP_CSC_CB2CB_COEF 11 0 BT 601 to BT 709 or BT 709 to...

Page 1445: ...ot modify 0 PP_CSC_CR2CR_COEF 11 0 BT 601 to BT 709 or BT 709 to BT 601 CSC coefficient for CR to CR 0 4 3 72 Video Processor Post processing Image Bypass Mode Control Register PP_BYPASS R W Address 0xF010_0200 PP_BYPASS Bit Description Reset Value Reserved 31 1 Reserved read as zero do not modify 0 PP_BYPASS 0 Disables the post image processor Post image processor executes color saturation contro...

Page 1446: ...o Processor Brightness Contrast Control Register PP_LINE_EQ0 PP_LINE_EQ7 y PP_LINE_EQ0 R W Address 0xF010_0218 y PP_LINE_EQ1 R W Address 0xF010_021C y PP_LINE_EQ2 R W Address 0xF010_0220 y PP_LINE_EQ3 R W Address 0xF010_0224 y PP_LINE_EQ4 R W Address 0xF010_0228 y PP_LINE_EQ5 R W Address 0xF010_022C y PP_LINE_EQ6 R W Address 0xF010_0230 y PP_LINE_EQ7 R W Address 0xF010_0234 PP_LINE_EQx Bit Descrip...

Page 1447: ...wing as PP_LINE_EQ0 0 31 PP_LINE_EQ1 31 63 PP_LINE_EQ2 64 95 PP_LINE_EQ4 96 127 PP_LINE_EQ5 128 159 PP_LINE_EQ6 160 191 PP_LINE_EQ7 192 223 PP_LINE_EQ8 224 255 4 3 76 Video Processor Brightness Offset Control Register for Y PP_BRIGHT_OFFSET R W Address 0xF010_ 0238 PP_BRIGHT_OFFSET Bit Description Reset Value Reserved 31 9 Reserved read as zero do not modify 0 PP_BRIGHT_OFFSET 8 0 Offset for Y bri...

Page 1448: ...S MANUAL REV1 0 VIDEO PROCESSOR 9 8 39 INPUT Luminance 0 OUTPUT Luminance 255 127 31 63 95 159 191 223 31 63 95 159 191 223 255 127 contrast darken image brighten image Figure 9 8 8 Image Brightness Contrast Control ...

Page 1449: ...28 Cb2Y_coef Cr 128 Cr2Y_coef Cb Y 16 Y2Cb_coef Cb 28 Cb2Cb_coef Cr 128 Cr2Cb_coef Cr Y 16 Y2Cr_coef Cb 28 Cb2Cr_coef Cr 128 Cr2Cr_coef Else Y Y Y2Y_coef Cb 128 Cb2Y_coef Cr 128 Cr2Y_coef Cb Y Y2Cb_coef Cb 28 Cb2Cb_coef Cr 128 Cr2Cb_coef Cr Y Y2Cr_coef Cb 28 Cb2Cr_coef Cr 128 Cr2Cr_coef 1 CSC_EN 0 Color space conversion enable control 0 Disable 1 Enable 0 4 3 78 Video Processor Version Information...

Page 1450: ...s to be interpolated are calculated with VP_SRC_V_POSITION and VP_V_RATIO Once the vertical position is calculated the nearest pixel phase with 1 16 resolution and which pixels are used for interpolation are decided V_RATIO Y0 Y1 Y2 Y3 Y0 Y1 Y2 Y3 0 16 phase 8 16 phase 16 16 phase Nth Line N 1th Line N 2th Line N 3th Line N 4th Line 4 16 phase 12 16 phase Current Interpolated Pixel with Y0 Y1 Y2 Y...

Page 1451: ...4_y0_ph7 vp_poly4_y1_ph7 vp_poly4_y2_ph7 and vp_poly4_y3_ph7 8 tap luminance horizontal poly phase filter and 4 tap chrominance horizontal poly phase filter use the exact same scheme At the boundaries of pictures top bottom left and right some pixels in filter window are not available In this case value of the nearest pixel is repeated as shown in Figure 9 8 a b c d e 1st Line 2nd Line 3rd Line a ...

Page 1452: ...S5PC100 USER S MANUAL REV1 0 VIDEO PROCESSOR 9 8 43 NOTES ...

Page 1453: ... mixer is directly transferred to TVENC HDMI module for the real time transfer 1 1 FEATURE Supports AXI Master AHB Slave Interface a AXI Master interface for graphic layer data fetch b AHB Slave interface for control register setup c Supports Little Big Endian Input a Multiple Layers Background layer Graphic0 layer Graphic1 layer Video layer b Input Control features Blending between each layers Se...

Page 1454: ...ng Maximum 256 level pixel and layer blending Separately configurable layer blending factor between each layer Video Layer a Source Video processor module b Color Format 24bpp Direct YCbCr 888 c Maximum Resolution 480i p 720x480 pixel 576i p 720x576 pixel Background layer a Source Configuration register b Lowest layer c Gradient color 24bpp YCbCr 888 Layer ordering a Background Æ Video Graphic0 Gr...

Page 1455: ...0 CSC Grp1 CSC Blender TVOUT I F DMA Line Buffer Control Line Buffer0 W1x128 Line Buffer1 W1x128 AXI Master I F AHB Slave I F Configuration Registers Pipe line Layer ordering Control Out Buffer W2x24 Background color Video YCbCr 24bit from VP To TVOUT YCbCr 24bit AXI BUS 64bit AHB BUS 32bit Figure 9 9 1 Mixer Block Diagram ...

Page 1456: ... out and HDMI out It is selected exclusively at the Clock Controller refer to 9 6 7 MIXER_OUT_SEL register When TV out is selected Mixer I F clock VCLKHS and VCLKS TVENC clock is fixed by 54MHz Thus you must configure MIXER_SEL register 9 2 3 CLK_SRC2 Clock Controller by VCLK_54 0x01 Otherwise in HDMI out selection MIXER_OUT_SEL register is configured properly Then you make the same clock configur...

Page 1457: ...HIC0_WH 0xF020_0030 R W Width Height for Graphic Layer0 0x0000_0000 MIXER_GRAPHIC0_DXY 0xF020_0034 R W Destination X Y Positions for Graphic Layer0 0x0000_0000 MIXER_GRAPHIC0_BLANK 0xF020_0038 R W Blank Pixel Value for Graphic Layer0 0x0000_0000 Graphic1 Layer Configuration MIXER_GRAPHIC1_CFG 0xF020_0040 R W Graphic Layer1 Configuration 0x0000_0000 MIXER_GRAPHIC1_BASE 0xF020_0044 R W Base Address ...

Page 1458: ...0_0000 MIXER_GRAPHIC0_BASE_S 0xF020_2024 R Graphic0 Base Address Shadow 0x0000_0000 MIXER_GRAPHIC0_SPAN_S 0xF020_2028 R Graphic0 Span Shadow 0x0000_0000 MIXER_GRAPHIC0_SXY_S 0xF020_202C R Graphic0 Source X Y Coordinates Shadow 0x0000_0000 MIXER_GRAPHIC0_WH_S 0xF020_2030 R Graphic0 Width Height Shadow 0x0000_0000 MIXER_GRAPHIC0_DXY_S 0xF020_2034 R Graphic0 Destination X Y Coordinates Shadow 0x0000_...

Page 1459: ...MIXER_BG_COLOR0_S 0xF02_2064 R Background First Color Shadow 0x0000_0000 MIXER_BG_COLOR1_S 0xF020_2068 R Background Second Color Shadow 0x0000_0000 MIXER_BG_COLOR2_S 0xF020_206C R Background Last Color Shadow 0x0000_0000 Version Register MIXER_VER 0xF020_0100 R Mixer Version 0x07D6_0A11 ...

Page 1460: ...ot modify 0 16_BURST_MODE 7 16 burst mode 64Bit Bus enabled in DMA 1 16Beat Burst Mode 0 8Beat Burst Mode 0 Reserved 6 4 Reserved 0 BIG_ENDIAN 3 0 Little Endian Source Format 1 Big Endian Source Format 0 SYNC_ENABLE 2 0 Values set by user will not be applied to the mixer operation although v_sync is detected 1 Values set by user can be applied to the mixer operation after v_sync detected 1 Reserve...

Page 1461: ... 4 Graphic0 layer display control bit 0 Disable 1 Enable 0 REG_VIDEO_EN 3 Video layer display control bit 0 Disable 1 Enable 0 REG_SCAN_MODE 2 Display scanning mode of TV 0 Interlaced mode 1 Progressive mode 0 REG_NTSC_PAL 1 Display standard of TV If you set this bit 0 and set REG_SCAN_MODE 1 output has to be call 480p standard 0 NTSC 720x480 1 PAL 720x576 0 REG_HD_SD 0 HD or SD selection 0 SD 1 H...

Page 1462: ... change of the MIXER_INT_STATUS 10 bit status 0 INT_EN_GRP1 9 The graphic layer1 line buffer underflow interrupt enable 0 Disables interrupt 1 Enables interrupt Setting this bit to 0 disables only the interrupt request to host controller It does not mask the change of the MIXER_INT_STATUS 9 bit status 0 INT_EN_GRP0 8 The graphic layer0 line buffer underflow interrupt enable 0 Disables interrupt 1 ...

Page 1463: ...ed underflow in line buffer 0 INT_STATUS_GRP1 9 The graphic layer1 line buffer underflow interrupt status 0 Interrupt is not fired 1 Interrupt is fired Writing 1 to this bit clears the interrupt This interrupt is automatically asserted by line buffer controller when generated underflow in line buffer 0 INT_STATUS_GRP0 8 The graphic layer0 line buffer underflow interrupt status 0 Interrupt is not f...

Page 1464: ...iority value 0 Hides the graphic layer 1 0 Graphic layer 0 priority 7 4 15 1 the priority value 0 Hides the graphic layer 0 0 Video layer priority 3 0 15 1 the priority value 0 Hides the video layer 0 0 NOTE All the changes of this register are valid on a vertical sync signal of next frame when SYNC_ENABLE flag is set to one And the Hide means that layer data is ready but is not displayed 2 7 MIXE...

Page 1465: ...In this mode graphic pixel data must be pre multiplied with graphic pixel alpha In pre multiplied mode REG_PIXEL0_BLEND_EN must be enabled Graphic and lower layer blending factor This factor is used all over the pixels in the graphic and lower layer to blend with A blending factor α is as follows depending on the a layer blending factor and a pixel blending factor values See Table 9 9 1 0 Reserved...

Page 1466: ...r to blend with A blending factor α is as follows depending on the a layer blending factor and a pixel blending factor values α graphic_layer_pixel_value 1 α lower_layer_pixel_value See Table 9 9 1 If REG_ALPHA_WIN0 is 0 blending_factor_layer is 0 If REG_ALPHA_WIN0 is not 0 blending_factor_layer REG_ALPHA_WIN 1 256 If A blending factor of each pixel is 0 blending_factor_each_pixel is 0 If A blendi...

Page 1467: ...n this mode graphic pixel data must be pre multiplied with graphic pixel alpha In pre multiplied mode REG_PIXEL1_BLEND_EN must be enabled Graphic and lower layer blending factor This factor is used all over the pixels in the graphic and lower layer to blend with A blending factor α is as follows depending on the a layer blending factor and a pixel blending factor values See Table 9 9 1 0 Reserved ...

Page 1468: ...r to blend with A blending factor α is as follows depending on the a layer blending factor and a pixel blending factor values α graphic_layer_pixel_value 1 α lower_layer_pixel_value See Table 9 9 1 If REG_ALPHA_WIN1 is 0 blending_factor_layer is 0 If REG_ALPHA_WIN1 is not 0 blending_factor_layer REG_ALPHA_WIN 1 256 If A blending factor of each pixel is 0 blending_factor_each_pixel is 0 If A blendi...

Page 1469: ... layer In pre multiplied mode the input graphic data is multiplied by the pixel blending factor alpha_gp and truncated to the size of source format bits For example although the result of the multiplication of 8 bit data by 8 bit pixel blending factor is 16 bits which is the first term of the blending equation in the Table 9 9 2 Normal mode the supplied data is truncated to 8 bits that results the...

Page 1470: ... example 640x480 s span is 640 It doesn t care BPP bit per pixel 0 2 14 MIXER_GRAPHIC0_WH R W ADDRESS 0XF020_ 0030 2 15 MIXER_GRAPHIC1_WH R W ADDRESS 0XF020_ 0050 MIXER_GRAPHICn_ WH Bit Description Reset Value Reserved 31 27 Reserved read as zero do not modify 0 REG_GRAPHICn_W 26 16 Width of graphic layer pixel unit 0 Reserved 15 10 Reserved read as zero do not modify 0 REG_GRAPHICn_H 10 0 Height ...

Page 1471: ...de 720p 0 2 18 MIXER_GRAPHIC0_DXY R W ADDRESS 0XF020_ 0034 2 19 MIXER_GRAPHIC1_DXY R W ADDRESS 0XF020_ 0054 MIXER_GRAPHICn_DXY Bit Description Reset Value Reserved 31 27 Reserved read as zero do not modify 0 REG_GRAPHICn_DX 26 16 X coordinate of upper left corner of graphic layer in destination frame pixel unit Allowed range 0 719 at SD mode 0 1279 at HD mode 720p 0 Reserved 15 10 Reserved read as...

Page 1472: ... 0068 2 24 MIXER_BG_COLOR2 R W ADDRESS 0XF020_ 006C MIXER_BG_COLOR0 1 2 Bit Description Reset Value 31 24 Reserved read as zero do not modify 0 Y 23 16 Y component of background color 0 Cb 15 8 Cb component of background color 0 Cr 7 0 Cr component of background color 0 NOTE You can choose proper YCbCr value for BT 601 or BT 709 ...

Page 1473: ...nt C10 19 Sign bit 18 10 Fractional bit Default and Recommended value 0 504 in decimal 0x102 REG_COEFF_20 9 0 Scaled color space conversion coefficient C20 9 Sign bit 8 0 Fractional bit Default and Recommended value 0 098 in decimal 0x32 NOTE RGB to YCbCr Conversion Equations 1 RGB data with 16 235 range Y601 0 299R 0 587G 0 114B Y709 0 213R 0 715G 0 072B Cb 0 172R 0 339G 0 511B 128 Cb 0 117R 0 39...

Page 1474: ... 0 signed bit 0 0 0 1 1 0 0 1 0 0x032 Ex2 0 148 First of all let s think about 0 148 0 148 0 5 0 0 25 0 0 125 1 0 0625 0 0 03125 0 0 015625 1 0 0078125 0 0 00390625 1 0 001953125 1 0 signed bit 0 0 1 0 0 1 0 1 1 10 b0001001011 Now to change the number from 0 148 to 0 148 we have to derive 2 s compliment of 0 148 10 b 0 0 0 1 0 0 1 0 1 1 10 b 1 1 1 0 1 1 0 1 0 0 bitwise invert 1 10 b 1 1 1 0 1 1 0 ...

Page 1475: ...efficient C01 29 Sign bit 28 20 Fractional bit Default value 0 0742785 in decimal Recommended value 0 148 in decimal 0x3b5 in hexa decimal 0x3b4 REG_COEFF_11 19 10 Scaled color space conversion coefficient C11 19 Sign bit 18 10 Fractional bit Default value 0 1455078125 in decimal Recommended value 0 291 in decimal 0x36c in hexa decimal 0x36b REG_COEFF_21 9 0 Scaled color space conversion coefficie...

Page 1476: ...EFF_02 29 20 Scaled color space conversion coefficient C02 29 Sign bit 28 20 Fractional bit Default and Recommended value 0 439 in decimal 0xe1 REG_COEFF_12 19 10 Scaled color space conversion coefficient C12 19 Sign bit 18 10 Fractional bit Default and Recommended value 0 368 in decimal 0x344 REG_COEFF_22 9 0 Scaled color space conversion coefficient C22 9 Sign bit 8 0 Fractional bitobs Default a...

Page 1477: ...g factor as it is the lowest layer y Video layer Video layer has one blending factor that is applied to all the pixels in the video layer MIXER_VIDEO_CFG 7 0 REG_ALPHA_VID is the blending factor The video blending is enabled or disabled y Graphic0 layer Graphic0 layer supports pixel blending and window blending Pixel blending factors are applied pixel by pixel although window blending factor is ap...

Page 1478: ...As the Video Processor scales the source image in letterbox mode the display region of the video data is smaller than the screen size In this case background layer is seen in the blank region 3 2 GRAPHIC LAYER ARM or Graphic Accelerator generates the graphic source data in the external memory and they are transferred to Mixer by AXI access Mixer supports the following graphic formats y 16bpp RGB 5...

Page 1479: ...erent color format When specifying the X Y coordinates and the width height of a graphic layer the graphic layers should be located in the display region 720x480 in NTSC display mode 720x576 in PAL display mode 1280x720p in HD display mode The Mixer does not support the clipping operation for the pixels that are displayed out of screen 3 3 BLANK PIXEL Blank pixel data in graphic layer is a pixel d...

Page 1480: ...B0 A1 R1 G1 B1 A R2 G2 B2 A R1 G1 B1 A R0 G0 B0 15 63 0 31 47 15 63 0 31 47 15 63 0 31 47 15 Figure 9 9 6 Graphic Data Format in Memory Pixels with lower X coordinates are located from the left These pixel data are represented by different digital data depending on the graphic format setting For example one graphic pixel is represented by 16 bit digital data in 16 BPP mode If these pixels are proc...

Page 1481: ...ANUAL REV1 0 MIXER 9 9 29 3 5 BACKGROUND LAYER If there is no video or graphic other layers in the display region background color is seen in that region Use YCbCr 888 format to set the background color in the register ...

Page 1482: ...MIXER S5PC100 USER S MANUAL REV1 0 9 9 30 NOTES ...

Page 1483: ...p 27Mhz 720p 74 25Mhz 4 4 4 YCbCr format for HDMI DVI input 4 4 4 YCbCr format 8 8 8 RGB Limited range format for HDMI output 8 8 8 RGB Limited Full range format for DVI output Packet transmission capabilities Audio Clock Regeneration ACR Packet is transmitted at 128xFs N rate GCP packet for AV mute control ACP ISRC1 and ISRC2 AVI Audio and MPEG Source Infoframes Vender Specific Infoframe or Sourc...

Page 1484: ... the HDMI timing information such as pixel and line numbers according to the horizontal active signal horizontal sync signal vertical sync signal and etc Second role is to control the packet transmission It checks the timing information and if available it generates control signals to audio FIFO and packet generator a Packet transmission control consideration Most of packets are transmitted once p...

Page 1485: ...data of SPDIF format type to extract 2 ch PCM or 5 1 ch stream format audio data and 4 bits extra information It sends decoded audio data to HDMI audio buffer It handles up to 192 KHz Fs data if 2 ch PCM is used 1 2 5 Buffer Buffer receives the audio PCM samples from the external and keeps them on the buffer FIFO The buffer size must be selected carefully because buffering just one sample for 8 ch...

Page 1486: ...a as specified in HDCP specification v1 1 It also processes the data for first second and the third authentication It requires external key memory 1 3 AUDIO INTERFACE 1 3 1 Audio Mode Setting There are 4 audio modes In multi channel mode the SP_PRE bits are used for Audio Sample Packet ASP header In 2 channel mode those bits are automatically generated ASP_CON Register Setting Audio Mode SACD_EN 5...

Page 1487: ... 24 bits i_pcm0R i_pcm0L 0 24 don t care don t care i_cuvR i_cuvL 2 0 Channel1 DSD stream 24 bits Channel0 DSD stream 24 bits i_pcm0R i_pcm0L 0 24 don t care don t care i_cuvR i_cuvL 2 0 Figure 9 10 2 24 Bits 2 Ch L PCM or 5 1 Ch DSD Mode For shorter bit width case for example 16 bits per channel each 16 bit PCM data should be located as left justified with LSB zero padding The 0 in the following ...

Page 1488: ...rypted HDCP KEY 288bytes ARM Core 80bits Key in EFROM HDCP Cipher Generated HAES Key 256bits Figure 9 10 4 HDMI Key Protection To decrypt HAES encrypted HDCP key S5PC100 gets information of HAES key used in encryption by utility program and HAES encrypted HDCP key message before starting HDMI HAES Key Generator generated HAES key based on 80bits Key in EFROM and generated HAES Key will be fed to H...

Page 1489: ...rypted data After checking that HAES_CON 0 flag is 0 then decrypted data can be used for HDCP key After generation of HDCP key is done HDCP module in HDMI will reference HDCP key automatically when HDCP sequence HDCP_CTRL 1 1 b1 is started 1 5 COLOR SPACE CONVERTER Color Space Converter CSC in Video Recevier block outputS RGB or YCbCr format according to display mode CSC coverts YCbCr601 to YCbCr7...

Page 1490: ... 256 256 1 601 219 219 219 219 R B C C Y B G R 128 128 16 0 506 443 256 738 178 132 86 256 901 350 0 256 256 1 601 219 219 219 219 R B C C Y B G R c YCbCr 601 RGB 0 255 128 128 16 0 7324453 1 1643828 1 81296875 0 390625 0 1643828 1 596027 1 0 1643828 1 601 219 255 255 255 R B C C Y B G R d YCbCr 709 RGB 16 235 128 128 16 0 430 464 256 165 117 885 46 256 150 394 0 256 256 1 601 219 219 219 219 R B ...

Page 1491: ...rates reference timing according to video format of output Figure 9 10 2 and Figure 9 10 2 shows parameter sets Figure 9 10 2 shows the reference timing for progressive mode and Figure 9 10 6 for interlaced mode Figure 9 10 6 Progressive Mode Reference Timing Generation ...

Page 1492: ...HDMI S5PC100 USER S MANUAL REV1 0 9 10 10 Figure 9 10 7 Interlace Mode Reference Timing Generation Expansion from Progressive Mode ...

Page 1493: ...0 864 1980 TG_HACT_ST_H L 138 370 144 700 TG_HACT_SZ_H L 720 1280 720 1280 TG_V_FSZ_H L 525 750 625 750 TG_VSYNC_H L 1 1 TG_VSYNC2_H L NA NA NA NA TG_VACT_ST_H L 45 30 49 30 TG_VACT_SZ_H L 480 720 480 720 TG_FIELD_CHG_ H L NA NA NA NA TG_VACT_ST2_H L NA NA NA NA TG_VSYNC_TOP_HDMI_H L 1 1 TG_VSYNC_BOT_HDMI_H L 563 563 TG_FIELD_TOP_HDMI_H L 1 1 TG_FIELD_BOT_HDMI_H L 563 563 ...

Page 1494: ...itive XhdmiTX2P Dedicated HDMI_TX2N Output Differential Data 2 Negative XhdmiTX2N Dedicated HDMI_TXCP Output Differential Clock Positive XhdmiTXCP Dedicated HDMI_TXCN Output Differential Clock Negative XhdmiTXCN Dedicated HDMI_REXT External Register XhdmiREXT Dedicated NOTES 1 The coloum Type in the above table indicates whether pads are dedicated to the signal or pads are connected to the multipl...

Page 1495: ... 0x10 HDMI_CMAX 0xF030_0068 R W Maximum Cb Cr Pixel Value 0xF0 HDMI_CMIN 0xF030_006C R W Minimum Cb Cr Pixel Value 0x10 VBI_ST_MG 0xF030_0080 R W Packet Transmission Start Margin during VBI 0x3C VBI_END_MG 0xF030_0084 R W Packet Transmission End Margin during VBI 0x30 VACT_ST_MG 0xF030_0088 R W Packet Transmission Start Margin during Active Video 0x2C VACT_END_MG 0xF030_008C R W Packet Transmissio...

Page 1496: ...me 0x01 V_SYNC_GEN_1_1 0xF030_0134 R W Vertical Sync Generation for Top Field or Frame 0x10 V_SYNC_GEN_1_2 0xF030_0138 R W Vertical Sync Generation for Top Field or Frame 0x00 Reserved 0xF030_0140 R W 0x01 Reserved 0xF030_0144 R W 0x10 Reserved 0xF030_0148 R W 0x00 Reserved 0xF030_0150 R W 0x01 Reserved 0xF030_0154 R W 0x10 Reserved 0xF030_0158 R W 0x00 ASP_CON 0xF030_0160 R W ASP Packet Control R...

Page 1497: ... 0xF030_01E4 W ACP Packet Header 0x00 ACP_DATA00 16 0xF030_ 0200 0240 W ACP Packet Body 0x00 ISRC_CON 0xF030_0250 R W ISRC Packet Control Register 0x00 ISRC1_HEADER1 0xF030_0264 W ISCR1 Packet Header 0x00 ISRC1_DATA00 15 0xF030_ 0270 02AC W ISRC1 Packet Body 0x00 ISRC2_DATA00 15 0xF030_ 02B0 02EC W ISRC2 Packet Body 0x00 AVI_CON 0xF030_0300 R W AVI Packet Control Register 0x00 AVI_CHECK_SUM 0xF030...

Page 1498: ...ers 0x00 HDMI_CSC_COEF20L 0xF030_04D0 R W CSC Coefficient Registers 0x00 HDMI_CSC_COEF20H 0xF030_04D4 R W CSC Coefficient Registers 0x00 HDMI_CSC_COEF21L 0xF030_04D8 R W CSC Coefficient Registers 0x00 HDMI_CSC_COEF21H 0xF030_04DC R W CSC Coefficient Registers 0x00 HDMI_CSC_COEF22L 0xF030_04E0 R W CSC Coefficient Registers 0x00 HDMI_CSC_COEF22H 0xF030_04E4 R W CSC Coefficient Registers 0x01 HDCP_RX...

Page 1499: ...RESULT 0xF030_0670 R W 2nd authentication status 0x00 HDCP_CTRL 0xF030_0680 R W HDCP Control 0x00 HDCP_CHECK_RESULT 0xF030_0690 R W HDCP Ri Pj V result 0x00 HDCP_BKSV_0_0 0xF030_06A0 R W Receiver s BKSV 0x00 HDCP_BKSV_0_1 0xF030_06A4 R W Receiver s BKSV 0x00 HDCP_BKSV_0_2 0xF030_06A8 R W Receiver s BKSV 0x00 HDCP_BKSV_0_3 0xF030_06AC R W Receiver s BKSV 0x00 HDCP_BKSV_1 0xF030_06B0 R W Receiver s ...

Page 1500: ...R W Horizontal Active Start 0x01 TG_ HACT_SZ_L 0xF030_1028 R W Horizontal Active Size 0x00 TG_ HACT_SZ_H 0xF030_102C R W Horizontal Active Size 0x05 TG_V_FSZ_L 0xF030_1030 R W Vertical Full Line Size 0xEE TG_V_FSZ_H 0xF030_1034 R W Vertical Full Line Size 0x02 TG_VSYNC_L 0xF030_1038 W Vertical Sync Position 0x01 TG_VSYNC_H 0xF030_103C W Vertical Sync Position 0x00 TG_VSYNC2_L 0xF030_1040 W Vertica...

Page 1501: ...PDIFIN_USER_VALUE 15 8 0x00 SPDIFIN_USER_VALUE_3 0xF030_5028 R W SPDIFIN_USER_VALUE 23 16 0x00 SPDIFIN_USER_VALUE_4 0xF030_502C R W SPDIFIN_USER_VALUE 31 24 0x00 SPDIFIN_CH_STATUS_0_1 0xF030_5030 R W SPDIFIN_CH_STATUS_0 7 0 0x00 SPDIFIN_CH_STATUS_0_2 0xF030_5034 R W SPDIFIN_CH_STATUS_0 15 8 0x00 SPDIFIN_CH_STATUS_0_3 0xF030_5038 R W SPDIFIN_CH_STATUS_0 23 16 0x00 SPDIFIN_CH_STATUS_0_4 0xF030_503C ...

Page 1502: ..._1_3 0xF030_5078 R W SPDIFIN_DATA_BUF_1 23 16 0x00 SPDIFIN_USER_BUF_1 0xF030_507C R W SPDIFIN_DATA_BUF_1 31 28 0x00 HAES_CON 0xF030_6000 R W HAES_CON 0x00 HAES_DATA_SIZE _L 0xF030_6020 R W HAES_DATA_SIZE_L 0x20 HAES_DATA_SIZE_H 0xF030_6024 R W HAES_DATA_SIZE_H 0x01 HAES_DATA 0xF030_6030 W HAES_DATA 0xXX ...

Page 1503: ... operation mode 0 HDMI_EN 0 Enable HDMI module in HDMI System HDMI system has HDMI module HDCP module HAES module SPDIFR module and TG module To enable and run HDMI system properly S W should enable each module 0 Disables HDMI module 1 Enables HDMI module NOTE Before enabling HDMI IP VP MIXER should be enabled 0 3 2 HDMI SYSTEM CONTROL REGISTER 1 HDMI_CON_1 R W ADDRESS 0XF030_0004 HDMI_CON_1 Bit D...

Page 1504: ... 0 AUD_FIFO_OVF 6 If audio FIFO is overflowed this bit will be set Once it is set it should be cleared by host 0 not full 1 full 0 Reserved 5 Reserved 0 UPDATE_RI_INT 4 HDCP generates this signal Refer to HDCP documentation If it is written by 1 it is cleared 0 not occurred 1 interrupt occurred 0 UPDATE_PJ_INT 3 HDCP generates this signal Refer to HDCP documentation If it is written by 1 it is cle...

Page 1505: ...nables 0 NOTE Update_Ri_int_en and Update_Ri_int_en should be enabled after s w gets ExchangeKSV_int 3 6 SOFTWARE HOT PLUG DETECTION HPD R W ADDRESS 0XF030_0030 HPD Hot Plug Detection Bit Description Reset Value Reserved 7 2 Reserved 0 SW_HPD 1 SW_HPD signal is used for Hot plug HDMI DVI cable plugging detection If S W detects Hot plug detection S W should set this field 0 Low unplugged 1 High plu...

Page 1506: ...Therefore in this case we have to send blue screen or some pictures irrelavent to real contents 3 9 BLUE_SCREEN_0 BLUE_SCREEN_0 R W ADDRESS 0XF030_0050 BLUE_SCREEN Bit Description Reset Value BLUESCREEN_0 7 0 Channel 0 color setting Cb value or B value 0 3 10 BLUE_SCREEN_1 BLUE_SCREEN_0 R W ADDRESS 0XF030_0054 BLUE_SCREEN Bit Description Reset Value BLUESCREEN_1 7 0 Channel 1 color setting Y value...

Page 1507: ...OTE Value 16 at each line is to compensate the difference of bit width between the input pixels and register value 0xEB 3 13 PIX PIXEL LIMIT VALUE REGISTERS HDMI_YMIN R W ADDRESS 0XF030_0064 HDMI_YMIN Bit Description Reset Value HDMI_YMIN 7 0 These registers are used according to PX_LMT_CTRL bits in HDMI_CON_1 register For Y values if input_color_value HDMI_YMAX x 16 output_color_value HDMI_YMAX x...

Page 1508: ...MI_CMIN R W ADDRESS 0XF030_006C HDMI_CMIN Bits Description Reset Value HDMI_CMIN 7 0 These registers are used according to PX_LMT_CTRL bits in HDMI_CON_1 register For Cb and Cr values if input_color_value HDMI_CMAX x 16 output_color_value HDMI_CMAX x 16 else if input_color_value HDMI_CMIN x 16 output_color_value HDMI_CMIN x 16 else output_color_value input_color_value NOTE Value 16 at each line is...

Page 1509: ... VBI_ST_MG AUTH_ST_MG AUTH_END_MG h blanking Active Video Data Line 525 Line 1 Line 524 Packet transmission capable duration Figure 9 10 8 Packet Transmission Timing Setting 480p 60Hz Case The above figure shows the 480p 59 94 60Hz timing diagram for packet transmission capable duration There are 6 parameters VBI_ST_MG VBI_END_MG VACT_ST_MG VACT_END_MG AUTH_ST_MG and AUTH_END_MG ...

Page 1510: ...eventing transmission of any packet data from the start of the video line during active video period Horizontal Blanking Period NOTE Strongly recommend that do NOT modify this field 0x2C 3 19 PACKET TRANSMISSION END MARGIN DURING ACTIVE VIDEO VACT_END_MG R W ADDRESS 0XF030_008C Name Bits Description Reset Value VACT_END_MG 7 0 The number of cycles for preventing transmission of any packet data fro...

Page 1511: ...TION V_BLANK_0 R W ADDRESS 0XF030_ 00B0 V_BLANK_0 Bit Description Reset Value V2_BLANK_L 7 0 Number of line size for end part of vertical blanking region V1_BLANK Active Lines Lower part 0 3 23 V_BLANK SIZE THAT DEPENDS ON RESOLUTION V_BLANK_1 R W ADDRESS 0XF030_ 00B4 V_BLANK_1 Bit Description Reset Value V1_BLANK_L 7 3 Number of line size for front part of vertical blanking region Lower part 0 V2...

Page 1512: ...280x720p V1_BLANK_H L 49 d 30 d 3 25 H_LINE V_LINE REAL RESOLUTION IT DEPENDS ON RESOLUTIONS H_V_LINE_0 R W ADDRESS 0XF030_00C0 H_V_LINE_0 Bit Description Reset Value V_LINE_L 7 0 Vertical Line Length Lower part 0 3 26 H_LINE V_LINE REAL RESOLUTION IT DEPENDS ON RESOLUTIONS H_V_LINE_1 R W ADDRESS 0XF030_00C4 H_V_LINE_1 Bit Description Reset Value H_LINE_L 7 4 Horizontal Line Length Lower part 0 V_...

Page 1513: ..._ 00E4 SYNC_MODE Bit Description Reset Value Reserved 7 1 Reserved 0 V_SYNC_POL_SEL 0 For Start Point Detection 720p s sync shapes are different from 480p and 576p s They are inverted shapes If v_sync is inverted then hard to detect start point therefore it is needed in this design 0 Active High 1 Active Low 0 50 60 Hz 720x480p 720x576p 1280x720p VSYNC_POL 1 1 0 3 29 INTERLACE OR PROGRESSIVE MODE ...

Page 1514: ...0x000 3 32 THE END POSITION OF NOT SEND PERIOD SEND_END_0 R W ADDRESS 0XF030_ 0100 SEND_END_0 Bit Description Reset Value SEND_END_PD_L 7 0 The end positon of not send period Lower part Don t send data period with SEND_START After this period hdmi control block should apply to HDCP block an encryption enable signal with one clock duty from setting SEND_END_ENC_H L 0x0FF 3 33 THE END POSITION OF NO...

Page 1515: ... odd field is different This register specifies the end position of bottom field s blank region Lower part 0x000 V_BOT_ST_H 2 0 The start position of bottom field s blank region Upper part 0x000 This register has nothing to do with progressive mode It affects just interlace mode 50 60 Hz 720x480p 720x576p 1280x720p V_BOT_ST_H L Don t care Don t care Don t care 3 37 THE START END POSITION OF BOTTOM...

Page 1516: ...per part 0x000 60Hz 720x480p 1280x720p HSYNC_START_H L 14 d 108 d 50Hz 720x576p 1280x720p HSYNC_START_H L 10 d 438 d 3 40 HDMI_H_SYNC_GEN H_SYNC_GEN_2 R W ADDRESS 0XF030_0128 H_SYNC_GEN_2 Bit Description Reset Value Reserved 7 5 Reserved 0x0 HSYNC_POL 4 Set this bit for inverting the generated signal to meet the modes Do not invert the signals in 720p modes Signals must be inverted for other modes...

Page 1517: ...erlaced mode or frame V sync start line number for progressive mode Upper part 0x1 VSYNC_T_END_H 3 0 Top field V sync end line number for interlaced mode or frame V sync end line number for progressive mode Upper part 0x0 50 60 Hz 720x480p 720x576p 1280x720p VSYNC_T_END_H L 15 d 10 d 10 d 3 43 HDMI_V_SYNC_GEN_1 V_SYNC_GEN_1_2 R W ADDRESS 0XF030_0138 V_SYNC_GEN_1_2 Bit Description Reset Value VSYNC...

Page 1518: ... channel mode selection This bit also is also used for layout bit in ASP header 0 2 channel mode 1 Multi channel mode 0 SP_PRE 3 0 Control sub packet usage for multi channel mode only If two channel mode this register value is not used 0000 3 46 SP_FLAT OR SAMPLE_INVALID VALUE FOR ASP HEADER ASP_SP_FLAT R W ADDRESS 0XF030_ 0164 ASP_SP_FLAT Bit Description Reset Value Reserved 7 4 Reserved 0 SP_FLA...

Page 1519: ...el 111 SPK3L_SEL 26 24 Audio channel Selection for subpacket 3 left channel data in multi channel mode The meaning is the same as SPK3R_SEL 110 Reserved 23 22 Reserved 0 SPK2R_SEL 21 19 Audio channel Selection for subpacket 2 right channel data in multi channel mode The meaning is the same as SPK3R_SEL 101 SPK2L_SEL 18 16 Audio channel Selection for subpacket 2 left channel data in multi channel m...

Page 1520: ... available at anytime after this value is set After transmitting these bits are reset to all zero 010 Tx ACR_TXCNT times during every VBI period 011 Tx by counting video_pixel_clock for a given CTS value in the ACR_CTS0 2 registers 100 Measured CTS mode Make ACR packet with CTS value by counting TMDS clock for Fs x 128 N duration In this case the 7 LSBs of N value ACR_N register should be all zero...

Page 1521: ...ddress 0xF030_01A8 ACR_N0 ACR_N1 ACR_N2 Bit Description Reset Value Reserved 23 20 Reserved 0 ACR_N 19 0 The N value in ACR packet Least significant byte first 0x003E8 3 52 SEE ALT_CTS_RATE IN ACR_CON REGISTER ACR_LSB2 R W ADDRESS 0XF030_01B0 ACR_LSB2 Bit Description Reset Value ACR_LSB2 7 0 Alternate CTS least significant byte See ALT_CTS_RATE in ACR_CON register 0x00 3 53 ACR PACKET TRANSMISSION...

Page 1522: ...1BC ACR_CTS_OFFSET Bit Description Reset Value ACR_CTS_OFFSET 7 0 If measured CTS mode is used the CTS value is measured by counting the TMDS clock for a given duration This value is added to measured CTS value It is 8 bit signed integer so subtraction is possible 0x00 3 56 GCP PACKET TRANSMISSION CONTROL REGISTER GCP_CON R W ADDRESS 0XF030_01C0 GCP_CON Bit Description Reset Value Reserved 7 2 Res...

Page 1523: ... packet once per every ACP_FR_RATE 1 frames or fields 0 Reserved 2 Reserved 0 ACP_TX_CON 1 0 00 Do not transmit 01 Transmit once 1x Transmit every vsync with ACP_FR_RATE 00 3 59 ACP PACKET HEADER HB1 REGISTER ACP_TYPE R W ADDRESS 0XF030_01E4 ACP_TYPE Bit Description Reset Value ACP_TYPE 7 0 ACP packet header HB1 of ACP packet header Refer to Table 5 18 in HDMI v1 2 specification 0x00 ...

Page 1524: ..._0218 y ACP_DATA07 W Address 0xF030_021C y ACP_DATA08 W Address 0xF030_0220 y ACP_DATA09 W Address 0xF030_0224 y ACP_DATA10 W Address 0xF030_0228 y ACP_DATA11 W Address 0xF030_022C y ACP_DATA12 W Address 0xF030_0230 y ACP_DATA13 W Address 0xF030_0234 y ACP_DATA14 W Address 0xF030_0238 y ACP_DATA15 W Address 0xF030_023C y ACP_DATA16 W Address 0Xf030_0240 ACP_DATAxx Bit Description Reset Value ACP_D...

Page 1525: ...SRC2_EN 2 Transmit ISRC2 packet with ISRC1 packet 0 ISRC_TX_CON 1 0 00 Do not transmit 01 Transmit once 1x Transmit every vsync with ISRC_FR_RATE 00 3 62 ISRC PACKET HEADER ISRC1_HEADER1 R W ADDRESS 0XF030_0264 ISRC1_HEADER1 Bit Description Reset Value ISRC_Cont 7 Refer to Table 5 20 in HDMI v1 2 specification 0 ISRC_Valid 6 Refer to Table 5 20 in HDMI v1 2 specification 0 Reserved 5 3 Reserved 00...

Page 1526: ... 0xF030_0288 y ISRC1_DATA07 W Address 0xF030_028C y ISRC1_DATA08 W Address 0xF030_0290 y ISRC1_DATA09 W Address 0xF030_0294 y ISRC1_DATA10 W Address 0xF030_0298 y ISRC1_DATA11 W Address 0xF030_029C y ISRC1_DATA12 W Address 0xF030_02A0 y ISRC1_DATA13 W Address 0xF030_02A4 y ISRC1_DATA14 W Address 0xF030_02A8 y ISRC1_DATA15 W Address 0xF030_02AC ISRC1_DATAxx Bit Description Reset Value ISRC1_DATA00 ...

Page 1527: ...xF030_ 02C8 y ISRC2_DATA07 W Address 0xF030_ 02CC y ISRC2_DATA08 W Address 0xF030_ 02D0 y ISRC2_DATA09 W Address 0xF030_ 02D4 y ISRC2_DATA10 W Address 0xF030_ 02D8 y ISRC2_DATA11 W Address 0xF030_ 02DC y ISRC2_DATA12 W Address 0xF030_ 02E0 y ISRC2_DATA13 W Address 0xF030_ 02E4 y ISRC2_DATA14 W Address 0xF030_ 02E8 y ISRC2_DATA15 W Address 0XF030_ 02EC ISRC2_DATAxx Bit Description Reset Value ISRC2...

Page 1528: ...Bit Description Reset Value 7 2 Reserved 0 AVI_TX_CON 1 0 00 Do not transmit 01 Transmit once 1x Transmit every vsync 00 3 66 AVI INFOFRAME CHECKSUM DATA AVI_CHECK_SUM W ADDRESS 0XF030_ 0310 AVI_CHECK_SUM Bit Description Reset Value AVI_CHECK_SUM 7 0 AVI InfoFrame checksum byte Refer to HDMI v1 2 specification for detailed information 0x00 ...

Page 1529: ...I_BYTE06 W Address 0xF030_ 0334 y AVI_BYTE07 W Address 0xF030_ 0338 y AVI_BYTE08 W Address 0xF030_ 033C y AVI_BYTE09 W Address 0xF030_ 0340 y AVI_BYTE10 W Address 0xF030_ 0344 y AVI_BYTE11 W Address 0xF030_ 0348 y AVI_BYTE12 W Address 0xF030_ 034C y AVI_BYTE13 W Address 0xF030_ 0350 AVI_BYTExx Bit Description Reset Value AVI_DATA01 AVI_DATA13 7 0 AVI Infoframe packet data registers Least significa...

Page 1530: ...0370 AUI_CHECK_SUM Bit Description Reset Value AUI_CHECK_SUM 7 0 AUI Infoframe checksum data PB0 byte of AUI packet body Refer to HDMI v1 2 specification 0x00 3 70 AUI INFOFRAME PACKET DATA AUI_BYTE1 AUI_BYTE4 y AUI_BYTE1 R W Address 0xF030_0380 y AUI_BYTE2 R W Address 0xF030_0384 y AUI_BYTE3 R W Address 0xF030_0388 y AUI_BYTE4 R W Address 0xF030_038C AUI_BYTEx Bit Description Reset Value AUI_BYTE...

Page 1531: ...set Value MPG_CHECK_SUM 7 0 MPG infoframe checksum register PB0 byte of MPG packet body Refer to HDMI v1 2 specification 0x00 3 73 MPG INFOFRAME PACKET BODY MPG_BYTE1 MPG_BYTE5 y MPG_BYTE1 W Address 0xF030_ 03C0 y MPG_BYTE2 W Address 0xF030_ 03C4 y MPG_BYTE3 W Address 0xF030_ 03C8 y MPG_BYTE4 W Address 0xF030_ 03CC y MPG_BYTE5 W Address 0xF030_ 03D0 MPG_BYTEx Bit Description Reset Value MPG_DTAT1 ...

Page 1532: ...smission They consist of full 3 bytes header register and 28 bytes packet body registers that is they are used for any format s packet transmission 3 75 SPD PACKET HEADER SPD_HEADER y SPD_HEADER0 W Address 0xF030_ 0410 y SPD_HEADER1 W Address 0xF030_ 0414 y SPD_HEADER2 W Address 0xF030_ 0418 SPD_HEADER0 SPD_HEADER1 SPD_HEADER2 Bit Description Reset Value SPD_HEADER0 SPD_HEADER1 SPD_HEADER2 7 0 7 0...

Page 1533: ...dress 0xF030_0450 y SPD_DATA13 W Address 0xF030_0454 y SPD_DATA14 W Address 0xF030_0458 y SPD_DATA15 W Address 0xF030_045C y SPD_DATA16 W Address 0xF030_0460 y SPD_DATA17 W Address 0xF030_0464 y SPD_DATA18 W Address 0xF030_0468 y SPD_DATA19 W Address 0xF030_046C y SPD_DATA20 W Address 0xF030_0470 y SPD_DATA21 W Address 0xF030_0474 y SPD_DATA22 W Address 0xF030_0478 y SPD_DATA23 W Address 0xF030_04...

Page 1534: ...pped to zero 0 IN_OFFSET_S 1 0 Output offset control It specifies ioffset0 and ioffset1 values shown in Figure 9 10 9 00 RGB FR ioffset0 0 ioffset1 0 01 reserved 10 RGB LR ioffset0 16 ioffset1 16 11 YCbCr ioffset0 16 ioffset1 128 11 NOTE The HDMI handles various pixel formats color space such as BT 601 YCbCr BT 709 YCbCr full range RGB limited range RGB and so on The color space conversion process...

Page 1535: ...ef10 0 256 298 256 298 0 HDMI_CSC_coef11 256 443 516 464 540 260 HDMI_CSC_coef12 0 0 0 0 0 29 HDMI_CSC_coef20 0 256 298 256 298 0 HDMI_CSC_coef21 0 0 0 0 0 19 HDMI_CSC_coef22 256 350 408 394 458 262 Coefficient RGB FR to RGB LR RGB FR to YCbCr601 RGB FR to YCbCr709 CSC_CON 0x20 0x30 0x30 HDMI_CSC_coef00 220 129 157 HDMI_CSC_coef01 0 25 16 HDMI_CSC_coef02 0 65 47 HDMI_CSC_coef10 0 74 87 HDMI_CSC_co...

Page 1536: ...T HDMI_CSC_COEF01 y HDMI_CSC_COEF01L R W Address 0xF030_04A8 y HDMI_CSC_COEF01H R W Address 0xF030_04AC HDMI_CSC_COEF01L HDMI_CSC_COEF01H Bit Description Reset Value Reserved 15 10 Reserved 0 HDMI_CSC_COEF01 9 0 coef01 of Figure 9 10 9 Signed 2 8 fixed point format Least significant byte first 0x0000 3 80 COEF02 OF FIGURE 9 10 9 SIGNED 2 8 FIXED POINT FORMAT HDMI_CSC_COEF02 y HDMI_CSC_COEF02L R W ...

Page 1537: ...HDMI_CSC_COEF11 y HDMI_CSC_COEF11L R W Address 0xF030_ 04C0 y HDMI_CSC_COEF11H R W Address 0xF030_ 04C4 HDMI_CSC_COEF02L HDMI_CSC_COEF02H Bit Description Reset Value Reserved 15 11 Reserved 0 HDMI_CSC_COEF02 10 0 coef11 of Figure 9 10 9 Signed 3 8 fixed point format Least significant byte first 0x0100 3 83 COEF12 OF FIGURE 9 10 9 SIGNED 2 8 FIXED POINT FORMAT HDMI_CSC_COEF12 y HDMI_CSC_COEF12L R W...

Page 1538: ...HDMI_CSC_COEF21 y HDMI_CSC_COEF21L R W Address 0xF030_ 04D8 y HDMI_CSC_COEF21H R W Address 0xF030_ 04DC HDMI_CSC_COEF21L HDMI_CSC_COEF21H Bit Description Reset Value Reserved 15 10 Reserved 0 HDMI_CSC_COEF21 9 0 coef21 of Figure 9 10 9 Signed 2 8 fixed point format Least significant byte first 0x0000 3 86 COEF21 OF FIGURE 9 10 9 SIGNED 2 8 FIXED POINT FORMAT HDMI_CSC_COEF22 y HDMI_CSC_COEFF22L R W...

Page 1539: ..._RX_SHA1_08 W Address 0xF030_ 0620 y HDCP_RX_SHA1_09 W Address 0xF030_ 0624 y HDCP_RX_SHA1_10 W Address 0xF030_ 0628 y HDCP_RX_SHA1_11 W Address 0xF030_ 062C y HDCP_RX_SHA1_12 W Address 0xF030_ 0630 y HDCP_RX_SHA1_13 W Address 0xF030_ 0634 y HDCP_RX_SHA1_14 W Address 0xF030_ 0638 y HDCP_RX_SHA1_15 W Address 0xF030_ 063C y HDCP_RX_SHA1_16 W Address 0xF030_ 0640 y HDCP_RX_SHA1_17 W Address 0xF030_ 0...

Page 1540: ...ISTER HDCP_KSV_LIST_CTRL ADDRESS 0XF030_ 0664 HDCP_KSV_LIST_ CTRL Bit Description RW Reset Value Reserved 7 3 Reserved 0 HDCP_KSV_LIST_ EMPTY 2 If the number of KSV list is zero set this value to enable SHA 1 module to calculate without KSV list 0 Not Empty 1 Empty W 0 HDCP_KSV_END 1 It is used to indicate that current KSV value in HDCP_KSV_LIST_X registers is the last one 0 Not End 1 End W 0 HDCP...

Page 1541: ...Reserved 0 EN_PJ 4 Enables Pj port update 1 Enables 0 Disables 0 Reserved 3 Reserved 0 TIMEOUT 2 Should be set if Rx is repeater NOTE KSV list is not ready until 5 sec waiting 0 CP_DESIRED 1 HDCP enable 1 Enables 0 Disables NOTE To enable HDCP feature proper s w sequence is needed 1 Set HDMI_STATUS_EN HDMI_HPD HDCP_OFFSET_TXx HDCP_CYCLE_AA registers 2 Set AES_DATA_SIZE_H L registers and run HAES_C...

Page 1542: ...SV_1 W Address 0xF030_ 06A4 y HDCP_BKSV_2 W Address 0xF030_ 06A8 y HDCP_BKSV_3 W Address 0xF030_ 06AC y HDCP_BKSV_4 W Address 0xF030_ 06B0 HDCP_BKSV_x Bit Description Reset Value HDCP_BKSV 39 0 Key selection vector KSV value from receiver Least significant byte first 0x0000000000 3 94 HDCP_AKSV 39 0 LITTLE ENDIAN ADDRESSING HDCP_AKSV_0 4 y HDCP_AKSV_0 R Address 0xF030_ 06C0 y HDCP_AKSV_1 R Address...

Page 1543: ...An 63 0 64 bit Random number generated by Tx An Least significant byte first All zeros 3 96 BCAPS INFORMATION FROM RX THIS VALUE IS THE DATA READ FROM RX HDCP_BCAPS R W ADDRESS 0XF030_0700 HDCP_BCAPS Bit Description Reset Value Reserved 7 Reserved 0 REPEATER 6 The receiver supports downstream connections 0 READY 5 KSV FIFO SHA 1 calculation ready 0 FAST 4 The receiver devices supports 400KHz trans...

Page 1544: ...error 0 DEPTH 10 8 Cascade depth 0 MAX_DEVS_EXCEEDED 7 Topology error indicator 1 Error 0 No Error 0 DEVICE_COUNT 6 0 Total number of attached downstream devices 0 3 98 HDCP RI VALUE OF THE TRANSMITTER HDCP_RI y HDCP_Ri_0 R Address 0xF030_ 0740 y HDCP_Ri_1 R Address 0xF030_ 0744 HDCP_Ri_0 HDCP_Ri_1 Bit Description Reset Value HDCP_Ri 15 0 HDCP Ri value of the transmitter Least significant byte fir...

Page 1545: ...pted key information Using HDCP_KEY_OFFSET start position of KEY in 288 bytes is declared Recommended value 0x05 0x00 HDCP_KSV_OFFSET 12 0 KSV address offset 12 0 Least significant byte first After HAES decrypts key information valid key information lies on 285 bytes of 288 bytes of decrypted key information Using HDCP_KSV_OFFSET start position of KSV in 288 bytes is declared Recommended value 0x0...

Page 1546: ...d mode enable This should be 0 0 tg_en 0 TG global enable bit 0 3 103 HORIZONTAL FULL SIZE TG_H_FSZ_L R W ADDRESS 0XF030_ 1018 TG_H_FSZ_L Bit Description Reset Value TG_H_FSZ_L 7 0 Horizontal full size 1 8191 Lower part 0x72 3 104 HORIZONTAL FULL SIZE TG_H_FSZ_H R W ADDRESS 0XF030_ 101C TG_H_FSZ_H Bit Description Reset Value Reserved 7 5 Reserved 0x0 TG_H_FSZ_H 4 0 Horizontal full size 1 8191 Uppe...

Page 1547: ...0 Horizontal active size 0 4095 Lower part 0x00 3 108 HORIZONTAL ACTIVE SIZE TG_HACT_SZ_H R W ADDRESS 0XF030_ 102C TG_HACT_SZ_H Bit Description Reset Value Reserved 7 4 Reserved 0x0 TG_HACT_SZ_H 3 0 Horizontal active size 0 4095 Upper part 0x5 3 109 VERTICAL FULL SIZE TG_V_FSZ_L R W ADDRESS 0XF030_ 1030 TG_V_FSZ_L Bit Description Reset Value TG_V_FSZ_L 7 0 Vertical full size 1 2047 Lower part 0xEE...

Page 1548: ...s is top field vsync position 1 2047 Upper part 0x0 3 113 BOTTOM FIELD VSYNC POSITION TG_VSYNC2_L W ADDRESS 0XF030_ 1040 TG_VSYNC2_L Bit Description Reset Value TG_VSYNC2_L 7 0 Vertical sync position for bottom field 1 2047 Lower part 0x33 3 114 BOTTOM FIELD VSYNC POSITION TG_VSYNC2_H W ADDRESS 0XF030_ 1044 TG_VSYNC2_H Bit Description Reset Value Reserved 7 0 Reserved 0x0 TG_VSYNC2_H 2 0 Vertical ...

Page 1549: ...size 0 2047 Lower part 0xD0 3 118 VERTICAL ACTIVE SIZE TG_TACT_SZ_H R W ADDRESS 0XF030_ 1054 TG_VACT_SZ_H Bit Description Reset Value Reserved 7 3 Reserved 0x0 TG_VACT_SZ_H 2 0 Vertical active size 0 2047 Upper part 0x2 3 119 FIELD CHANGE POSITION TG_FIELD_CHG_L R W ADDRESS 0XF030_ 1058 TG_FIELD_CHG_L Bit Description Reset Value TG_FIELD_CHG_L 7 0 Field change position 1 2047 Lower part 0x33 3 120...

Page 1550: ...tion for bottom field 1 2047 Upper part 0x2 3 123 VSYNC POSITION FOR HDMI TG_VSYNC_TOP_HDMI_L R W ADDRESS 0XF030_ 1078 TG_VSYNC_TOP_HDMI_L Bit Description Reset Value TG_VSYNC_TOP_HDMI_L 7 0 HDMI vsync position for top field Lower part 0x01 3 124 VSYNC POSITION FOR HDMI TG_VSYNC_TOP_HDMI_H R W ADDRESS 0XF030_ 107C TG_VSYNC_TOP_HDMI_H Bit Description Reset Value Reserved 7 3 Reserved 0x0 TG_VSYNC_T...

Page 1551: ... 0x01 3 128 TOP FIELD CHANGE POSITION FOR HDMI TG_FIELD_TOP_HDMI_H R W ADDRESS 0XF030_ 108C TG_FIELD_TOP_HDMI_H Bit Description Reset Value Reserved 7 3 Reserved 0x0 TG_FIELD_TOP_HDMI_H 2 0 HDMI top field start position Upper part 0x0 3 129 BOTTOM FIELD CHANGE POSITION FOR HDMI TG_FIELD_BOT_HDMI_L R W ADDRESS 0XF030_ 1090 TG_FIELD_BOT_HDMI_L Bit Description Reset Value TG_FIELD_BOT_HDMI_L 7 0 HDMI...

Page 1552: ...ecovery If recovery is done SPDIFIN begins detecting preambles of SPDIF signal format and stream data header abnormal time signal input abnormal signal input It also reports this status via interrupts in SPDIFIN_IRQ_STATUS 11b status checking HDMI operation mode run with HDMI 01b case operations checking internal buffer overflow write received data which is either audio sample word of PCM or paylo...

Page 1553: ...is disabled 1 Interrupt generation is enabled 0 stream_header_detected_ir_en 4 Mask bit for Interrupt 5 0 Interrupt generation is disabled 1 Interrupt generation is enabled 0 stream_header_not_detected_ir_ en 3 Mask bit for Interrupt 4 0 Interrupt generation is disabled 1 Interrupt generation is enabled 0 wrong_preamble_ir_en 2 Mask bit for Interrupt 3 0 Interrupt generation is disabled 1 Interrup...

Page 1554: ...on is checked every Pd time if stream mode This interrupt assertes if SPDIFIN_OP_CTRL op_ctrl 001b or 011b This interrupt assertes if SPDIFIN_CONFIG data_type is stream If user does not handle this interrupt SPDIFIN will stop transferring stream payload via HDMI then wait for the next stream header detection 0 No interrupt 1 Pd exceeds 1 block size of stream Writing 0 has no effect Writing 1 clear...

Page 1555: ...fter previous interrupt of stream_header_not_detected_ir 0 wrong_preamble_ir 2 0 No interrupt 1 Detects Preamble but there is a problem with detected time Writing 0 has no effect Writing 1 clears the interrupt request This interrupt assertes if SPDIFIN_OP_CTRL op_ctrl 001b or 011b Meaningless until ch_status_recovered_ir is asserted initially after SPDIFIN_OP_CTRL op_ctrl 01b Cases for interrupt C...

Page 1556: ...not recover clock from input because of tolerable range violation unlock or because of no signal from outside or because of non biphase in non preamble duration Meaningless until ch_status_recovered_ir is asserted initially after SPDIFIN_OP_CTRL op_ctrl 01b 0 1 Detection of stream header y Wait for matching of Pa Pb 0xF872 0x4E1F respectively y Wait for the repetition time From decoded Pc value or...

Page 1557: ...x 0 Linear PCM type data 1 Nonlinear PCM type data Stream type 0 PcPd_value_mode 4 If 0 for automatic setting Pc and Pd values are chosen by value of Pc Pd from decoded stream header reported as in SPDIFIN_Px_INFO If you set this register the receiver uses SPDIFIN_USER_VALUE 31 16 SPDIFIN_USER_VALUE 15 4 value as Pc and Pd respectively instead of decoded data from stream header as reported in SPDI...

Page 1558: ...x00ffffff for 24 bit data If stream mode you should set word_length_value_mode as 1 and set SPDIFIN_USER_VALUE word_length_manual as 3 b000 These two modes is applied to both modes of SPDIFIN_CONFIG data_type i e PCM or stream see also SPDIFIN_DATA_BUF_x 0 16 bit mode 1 32 bit mode 0 3 136 SPDIFIN_CONFIG_2 R W ADDRESS 0XF030_ 5014 SPDIFIN_CONFIG_2 Bit Description Reset Value clk_divisor 3 0 SPDIFI...

Page 1559: ...manual 3 0 Word length Used as size for transferring data to memory via HDMI valid if SPDIFIN_CONFIG word_length_value_mode is set for manual mode 0 is 1 0 is 0 3 1 101 24 bits 20 bits 001 23 bits 19 bits 010 22 bits 18 bits 011 21 bits 17 bits 100 20 bits 16 bits 0000 3 138 REPETITION TIME SPDIFIN_USER_VALUE_2 R W ADDRESS 0XF030_ 5024 SPDIFIN_USER_VALUE_2 Bit Description Reset Value repetition_ti...

Page 1560: ...IFIN_USER_VALUE_4 Bit Description Reset Value burst_payload_length_manual_ high 7 0 Burst_payload_length_manual register 16 bits value This register is high 8 bits Valid if SPDIFIN_CONFIG PcPd_value_mode is set for manual mode Unit bits 0x00 3 141 HDCP PJ INTERRUPT STATUS SPDIFIN_CH_STATUS_0_1 R W ADDRESS 0XF030_ 5030 SPDIFIN_CH_STATUS_0_1 Bit Description Reset Value channel_status_mode 7 6 00 Mod...

Page 1561: ...01L Mini disc 1001_001L L information about generation status of the material This register is updated every 192 frames 1 block of SPDIF format 0x00 3 143 SPDIFIN_CH_STATUS_0_3 R W ADDRESS 0XF030_5038 SPDIFIN_CH_STATUS_0_3 Bit Description Reset Value channel_number 7 4 Bit 20 is LSB This register is updated every 192 frames 1 block of SPDIF format 0000 source_number 3 0 Bit 16 is LSB This register...

Page 1562: ...k_accuracy 5 4 5 4 10 level I 50ppm 00 level II 1000ppm 01 level III variable pitch shifted This register is updated every 192 frames 1 block of SPDIF format 00 sampling_frequency 3 0 0 1 2 3 0010 22 05kHz 0000 44 1 kHz 0001 88 2kHz 0011 176 4kHz 0110 24kHz 0100 48 kHz 0101 96kHz 0111 192kHz 1100 32 kHz This register is updated every 192 frames 1 block of SPDIF format 0000 ...

Page 1563: ...20 bits 1 Maximum length 24 bits This register is updated every 192 frames 1 block of SPDIF format 0 3 146 COUNTING VALUE FOR A FRAME OF SPDIF FORMAT SPDIFIN_FRAME_PERIOD_1 R W ADDRESS 0XF030_ 5048 SPDIFIN_FRAME_PERIOD_1 Bit Description Reset Value Rrame_cnt_low 0 Counting value for a frame of SPDIF format Frame_cnt register is 16 bits value This is low 8 bits The period of a frame 2 sub frames th...

Page 1564: ...de with SPDIFIN_CONFIG clk_divisor Unit SPDIF_internal_clk Cycles Recommended value for locking incoming signals Over 0x220 8 5timesx64 bits 0x00 3 148 SPDIFIN_PC_INFO_1 R W ADDRESS 0XF030_ 5050 SPDIFIN_Pc_INFO_1 Bit Description Reset Value Error_flag 7 0 Valid burst payload 1 Vurst payload contains errors 0 Reserved 6 5 Reserved 00 compressed_data_type 4 0 0d Null data 1d Dolby AC 3 2d Reserved 3...

Page 1565: ..._ N th data_ N 1 th If SPDIFIN_CONFIG data_align is 1 for 32 bit received_data U V C P zero padding data n 0 received_data zero padding data n 0 if SPDIFIN_CONFIG U_V_P_report is 0 n is dependent on SPDIFIN_CH_STATUS_1 word_length when SPDIFIN_CONFIG data_type is 0 for PCM Or n is 15 when SPDIFIN_CONFIG data_type is 1 for stream 0x00 3 151 PCM OR STREAM DATA FOR 1ST BURST OF HDMI SPDIFIN_DATA_BUF_...

Page 1566: ...accesses SPDIFIN_DATA_BUF_0 and SPDIFIN_DATA_BUF_1 together Endian of each data 0x00 3 155 PCM OR STREAM DATA FOR 2ND BURST OF HDMI SPDIFIN_DATA_BUF_1_2 R W ADDRESS 0XF030_ 5074 SPDIFIN_DATA_BUF_1_2 Bit Description Reset Value received_data 7 0 PCM or stream data for 2nd burst of HDMI 0x00 3 156 PCM OR STREAM DATA FOR 2ND BURST OF HDMI SPDIFIN_DATA_BUF_1_3 R W ADDRESS 0XF030_ 5078 SPDIFIN_DATA_BUF...

Page 1567: ...d 0x0 HAES_START 0 HAES Start signal If specified amount of data is decrypted and written in memory then HAES start signal goes to 0 Before HAES_START is set s w should ensure that HAES_KEY_DONE is set 0 HAES does not decrypt data 1 HAES starts to decrypt data from MEM_encr to generate HDCP Key 0 3 159 HAES DATA SIZE IN BYTES TO DECRYPT HAES_DATA_SIZE_L R W ADDRESS 0XF030_ 6020 HAES_DATA_SIZE_L Bi...

Page 1568: ...multiple of 128 bits zeros should be padded 128bit align Maximum number is 120h Internal memory size limits the maximum data size Default value 288 bytes 0x01 3 161 ENCRYPTED DATA TO BE WRITTEN IN MEMORY BEFORE DECRYPTION HAES_DATA W ADDRESS 0XF030_ 6030 HAES_DATA Bit Description Reset Value Reserved 31 8 Reserved 24 hXX HAES_DATA 7 0 Encrypted data to be written in memory before decryption Memory...

Page 1569: ...ferent standards the codec can support upto two standards The top level of the FIMV MFC V4 0 contains the hardware modules which includes an ARM 7 CPU The hardware and the firmware in the ARM 7 CPU performs the decoding functions for H 264 baseline main and high profiles DIVX versions 4 x 5 x 6 x and MPEG 4 simple and advanced simple profile MPEG 2 simple and main profile VC 1 and H 263 profile3 a...

Page 1570: ...F VSP_ HOSTIF VSP_DMA VSP_DMA ITB_ MUX ITB_ MUX D BUS I BUS DMA BUS Coefficient RW SRAM Protocol ITB BUS VME_ ACDC VME_ ACDC VME_DCTQ VME_DCTQ VME_MP VME_MP VME_ME VME_ME VME_PRED VME_PRED VME_DB VME_DB VSP_ VME_IF VSP_ VME_IF 64 bit AXI Read 64 bit AXI RW 64 bit AXI RW VSP Video Stream Processor VME Video Macroblock Engine VME_SLICE INFO VME_SLICE INFO VME_RC VME_RC Figure 9 11 1 FIMV MFC V4 0 To...

Page 1571: ...video streams y SMPTE 421M VC 1 upto Adv Profile Level 2 0 decoding 2 2 FEATURES Synthesizable high performance multi format codec FIMV MFC V4 0 is decoding upto 1280x720 resolution image 30fps y Resolutions upto 1280x720 720p D1 VGA QVGA CIF QCIF y Minimum size 32x16 16x32 for decoder 32x32 for encoder y Supports single stream 720p 30fps encoding decoding y Time multiplexed multi stream encoding ...

Page 1572: ...ported in encoding y Supports only DC prediction in MPEG 4 encoding y Rate control CBR Constant Bit Rate and VBR Variable Bit Rate y Frame level H 264 MPEG4 H 263 and macroblock level H 264 rate control can be enabled or disabled selectively y Progressive encoding only support y Non paired field mode is not supported y Startcode must be included at every position of frame or slice in stream at dec...

Page 1573: ... and concealment is supported by FIMV MFC V4 0 The error detection and concealment above picture layer MPEG 4 or slice layer H 264 is performed by software The error detection and concealment is performed by the FIMV MFC V4 0 without software interaction FIMV MFC V4 0 performs error detection e g y Detecting illegal values of syntax elements y Detecting semantic errors e g illegal prediction modes...

Page 1574: ...ed informations from the bitstream to the VME module The VSP performs these operations with the embedded ARM 7 microprocessor and hardware modules The VME module performs the video processing function of the video coding like ac dc prediction quantization transform motion estimation motion compensation deblock filtering and post filter All the functions in this module are implemented in hardware 3...

Page 1575: ...hrough the host interface The host interface provides registers which can be accessed by both the ARM 7 and the host processor A DMA module the VSP reads and writes bitstream to and from the external memory The DMA also initially loads the required firmware into the code memory in the VSP during initialization time The Syntax module performs encoding of syntax of data provided by the ARM 7 during ...

Page 1576: ...nce luminance and chrominance data stored in mempool module The mempool module loads reference data from external memory according to decoded motion vector After prediction is operated reconstructed pixel is filtered by deblocking module VME uses the 64 bit AXI bus interface for data transfer from to an external memory VME_ ACDC VME_ ACDC VME_ ME VME_ ME VME_ PRED VME_ PRED 64 bit AXI Read 64 bit ...

Page 1577: ...T and weighted quantization for high profile MPEG4 transform operates on 8x8 blocks of original data in intra macroblock or residual data after motion compensated prediction MPEG4 decoder support weighted quantization for advanced simple profile H 264 transform operates on 4x4 blocks of residual data after motion compensated prediction or Intra prediction The transform is based on the DCT but with...

Page 1578: ... path is similar to the decoder operation Residual values of this second decoding path are added to the predictor and the results go to the VME_DB part In Encoder no DMA module is used The VME_PRED uses only 1 reference frame for the prediction 3 2 5 DEBLOCKING FILTER Deblocking filter removes blocking artifacts resulted from quantization The MFC4 0 deblocking filter supports on the fly H 264 in l...

Page 1579: ...for chroma coefficients Memory word width is 44bits four pixels unit to support VC1 overlap smoothing filter In the case of VC1 predicted coefficient is not clamped so the bit width of predicted coefficient is 10 During the overlap smoothing filter bit overflow can be happened Deblock filter is composed in two stages one is filtering operation Stage0 and the other is DMA operation Stage1 Predicted...

Page 1580: ...ream processor writes the overlap smoothing filer control value conditional overlap flag slice type profile and so on VC1 In loop Filter VC 1 deblocking filtering process operates on the pixels that border neighboring blocks For P pictures the block boundaries may occur at every 4 th 8th 12th etc pixel row or column depending on whether an inverse transform type For I pictures filtering occurs at ...

Page 1581: ... size for Cb Cr frame buffer is half of the Y frame buffer Luma Y 0 1 2 3 4pixel Y Y Y Y Chroma Cb Cr 4pixel Cb Cr Cb Cr Figure 9 11 6 Luma Chroma Pixel 8byts aligned Frame can be stored in two ways linear memory structure or tile mode memory structure The host sets external memory parameters and memory structure method The physical memory address of each pixel data is determined with memory struc...

Page 1582: ... TILE4 TILE5 TILE6 TILE7 TILE8 TILE9 TILE10 TILE11 64 65 66 127 128 129 130 191 1984 1985 1986 2047 2048 2049 2050 2111 2112 2113 2114 2175 2176 2177 2178 2239 2176 2177 2178 4095 4096 4097 4098 4159 4160 4161 4162 4223 4224 4225 4226 4287 6080 6081 6082 6143 6144 6145 6146 6207 6208 6209 6210 6271 8128 8129 8130 8191 8192 8193 8194 8255 8256 8257 8258 8319 10176 10177 10178 10239 BLK0 BLK2 BLK2 F...

Page 1583: ...S5PC100 USER S MANUAL REV1 0 MFC MULTI FORMAT CODEC 9 11 15 5 ENCODING DECODING COMMAND FLOW 5 1 DECODING FLOW Figure 9 11 10 Decoding Flow ...

Page 1584: ...MFC MULTI FORMAT CODEC S5PC100 USER S MANUAL REV1 0 9 11 16 5 2 ENCODING FLOW Figure 9 11 11 Encoding Flow ...

Page 1585: ...ing the request the firmware again waits for the next command The commands used in the multi channel implementation can be divided into four types Those are INIT_CODEC r CHANNEL_SET and CHANNEL_END Each command is controlled by CH_ID channel id This is useful for multi stream encoding decoding For example if you want to decode MPEG4 decoder and H 264 decoder at the same time time multiplexing you ...

Page 1586: ...ality can be understood for the diagram given below In case of multi channel decoder the input to the system is the bit steams of same or different in case of multi standard support standard and the output will be store buffer of each channel In case of multi channel encoder the input to the system is the YUV data and the output will be the bit stream of required standard ...

Page 1587: ...c standard STANDARD_SEL Decoding Encoding STANDARD_SEL Command type MFC_COMMAND_TYPE y Set the FRAME_START 1 y Host wait for OPERATION_DONE 1 ARM7 process y Backup the values setting in Host according to CH_ID Standard codec type etc y Set the command status as SET in the command status array y DMA the program data to the internal memory for the selected codec if it is not DMADONE earlier y Set OP...

Page 1588: ...he SDRAM areas according to image size and write DEC_DPB_ADDR DPB_COMV_ADDR POST_ADDR register HOST processor waits until OPERATION_DONE regitser will be high after wrting to SEQ_START regitser This command has to be executed once for a particular channel and it is an error if it is tried to be executed after that Host process y Channel ID write Host Interface Register CH_ID y Aloocated channel wo...

Page 1589: ...e values of DISPLAY_Y_ADDR register and DISPLAY_C_ADDR register The address values stored in those registers enable the current image to be displayed When encoding HOST processor has to check the encoding end signal And then prepares next encoding Host process y Write the Channel ID y Update the required host interface registers Decoding Update decoder control register Encoding Update Encoder cont...

Page 1590: ...irmware will complete the function of the selected command and it will send OPERATION _ DONE Signal to the Host Wait till it receives the Operation _ Done signal from the Firmware Host processing start Wait till it receive FRAME_START signal For a Command INIT_ CODEC CHANNEL _SET processing Once per Channel FRAME _RUN processing CHANNEL _END processing Select Command If All Channels Done End host ...

Page 1591: ...ssing For running one complete frame the sequence of command execution should be like CHANNEL_SET INIT_CODEC and FRAME_RUN The command CHANNEL_SET and INIT_CODEC should execute once per each channel If the host wants to stop the execution of one channel then the CHANNEL_END command is executed During one command processing other command shouldn t be issued For one successful frame running the abov...

Page 1592: ... and SEI and the frame data which may contain several slices The Host shall notify to the VSP_DMA where the stream for the frame data or the frame data with the stream header is using the Host Interface before starting decoding a frame The following figures show the stream format example for each standard The each stream which is represented as a rectangular contains each frame data and stream hea...

Page 1593: ... frame the Host sets the FRAME_START to decode a frame and checks the OPERATION_DONE In case of the first frame the Host sets the SEQUENCE_START to decode stream header and checks the HEADER_DONE and then the Host sets the FRAME_START to decode a frame and checks the OPERATION_DONE ...

Page 1594: ...lowing figure Except for the first frame the Host sets the FRAME_START to decode a frame and checks the OPERATION_DONE In case of the first frame the Host sets the SEQUENCE_START to decode stream header and checks the HEADER_DONE and then the Host sets the FRAME_START to decode a frame and checks the OPERATION_DONE Because there is no Stream header in the H 263 for the first frame the Host sets th...

Page 1595: ...s are encoded for the corresponding frame using the ENC_UNIT_SIZE The Host should guarantee that the EXT_BUF_START_ADDR and the EXT_BUF_END_ADDR have a range enough to include one frame sized stream in encoding If not it may be stuck H 264 and MPEG4 Case The Stream header is located at the first position of the stream So the encoded stream for the first frame shall contain stream header as well as...

Page 1596: ...rocess y Channel ID write 1 CH_ID y Write the Command type to SLEEP MFC_COMMAND_TYPE y Set the FRAME_START 1 y Host wait for OPERATION_DONE 1 y MFC can be switched power off 8 2 WAKEUP Host process y Host enable MFC block power on y Load Command Control FW to MFC y Start F W set FW_START 1 y Channel ID write 1 CH_ID y Write the Command type to WAKEUP MFC_COMMAND_TYPE y Host wait for OPERATION_DONE...

Page 1597: ... Encoded Stream Unit Size Register 0x0000_0000 START_BYTE_NUM 0xF100_005C R W Start Byte Number Register 0x0000_0000 ENC_HEADER_SIZE 0xF100_0060 R Encoded Header Size Register 0x0000_0000 COMMAND CONTORL STD_SEL_REG 0xF100_0100 R W Standard Selection Register 0x0000_0000 CH_ID 0xF100_0104 R W Channel ID Register 0x0000_0000 CPU_RESET 0xF100_0108 R W Cpu Reset Register 0x0000_0000 FW_END 0xF100_010...

Page 1598: ...0000_0000 DB_FILTER_OPTION 0xF100_0314 R W Deblocking Filter Control Register 0x0000_0000 SHORT_HD_ON 0xF100_0318 R W Short Header On Off Control Register 0x0000_0000 MSLICE_ENA 0xF100_031C R W Multi Slice Enable Register 0x0000_0000 MSLICE_SEL 0xF100_0320 R W Multi Slice Selection Register 0x0000_0000 MSLICE_MB 0xF100_0324 R W Multi Slice Interval MB Register 0x0000_0000 MSLICE_BYTE 0xF100_0328 R...

Page 1599: ... VERSION RC_CONFIG 0xF100_0a00 R W Rate Control ConfigurationRegister 0x0000_0000 RC_FRAME_RATE 0xF100_0a04 R W Rate Control Framerate Register 0x0000_0000 RC_BIT_RATE 0xF100_0a08 R W Rate Control BitrateRegister 0x0000_0000 RC_QBOUND 0xF100_0a0C R W Quantizer Parameter Boundary Register 0x0000_0000 RC_RPARA 0xF100_0a10 R W Reaction Coefficient Register 0x0000_0000 RC_MB_CTRL 0xF100_0a14 R W Macro...

Page 1600: ...count size of codec firmware to transfer into internal memory using DMA 0 9 1 3 DMA EXTERNAL MEMORY ADDRESS REGISTER DMA_EXT_ADDR R W ADDRESS 0xf100_0014 DMA_EXT_ADDR Bit Description Reset Value DMA_EXTADDR 31 0 Start address of the external memory to transfer Firmware 0 9 1 4 EXTERNAL BUFFER START ADDRESS REGISTER EXT_BUF_START_ADDR R W ADDRESS 0xf100_0018 EXT_BUF_START_ADDR Bit Description Reset...

Page 1601: ...ing If stream buffer size is guaranteed more than one frame size this value should be set EXT_BUF_END_ADDR value 0 9 1 8 LAST DECODING CONTROL REGISTER LAST_DEC R W ADDRESS 0xf100_0028 LAST_DEC Bit Description Reset Value Reserved 31 1 Reserved 0 LAST_DEC 0 When this bit is set to 1 in decoding this shows no more stream will be added in the bitstream buffer HOST_PTR_ADDR register s value indicates...

Page 1602: ...one decoding frame in the stream has 0 9 1 12 ENCODED STREAM UNIT SIZE ENC_UNIT_SIZE R ADDRESS 0xf100_0058 ENC_UNIT_SIZE Bit Description Reset Value ENC_UNIT_SIZE 31 0 MFC informs the host of the encoded frame size 0 9 1 13 START BYTE NUMBER START_BYTE_NUM R W ADDRESS 0xf100_005c START_BYTE_NUM Bit Description Reset Value START_BYTE_NUM 3 0 Remaining byte position of the stream when it is not word...

Page 1603: ...its Enc_ON is 1 0 MPEG 4 1 H 264 Enc_ON is 0 0 MPEG 4 Divx XviD 1 H 264 4 H 263 5 MPEG 2 6 VC 1 0 9 2 2 CHANNEL ID REGISTER CH_ID R W ADDRESS 0xf100_0104 CH_ID Bit Description Reset Value Reserved 31 5 Reserved 0 CH_ID 4 0 Channel index is an ID identifying host s job during multi channel encoding or decoding 0 9 2 3 CPU RESET REGISTER CPU_RESET R W ADDRESS 0xf100_0108 CPU_RESET Bit Description Re...

Page 1604: ...RESS 0xf100_0110 BUS_MASTER Bit Description Reset Value Reserved 31 1 Reserved 0 BUS_MASTER 0 This register sets the master of DMA before the setting of DMA in external host If 1 external bus master is the host 0 bus master is MFC ex MFC can write DMA register 1 bus master is Host ex Host can write DMA register 0 9 2 6 FRAME START REGISTER FRAME_START R W ADDRESS 0xf100_0114 FRAME_START Bit Descri...

Page 1605: ..._SIZE_Y Bit Description Reset Value Reserved 31 16 Reserved 0 IMG_SIZE_Y 15 0 Vertical image real size Note In Encoder Write only register In Decoder Read only register 0 9 2 9 MPEG4 POST FILTER ON OFF CONTROL REGISTER POST_ON R W ADDRESS 0xf100_0124 POST_ON Bit Description Reset Value Reserved 31 1 Reserved 0 POST_ON 0 mpeg4 post filter on off signal 0 off 1 on 0 9 2 10 FRAME RATE SETTING REGISTE...

Page 1606: ... Value Reserved 31 1 Reserved 0 SW_RESET 0 Software reset control signal 1 S W reset 0 normal Note This bit is reset to 0 automatically 0 9 2 13 FIRMWARE START REGISTER FW_START R W ADDRESS 0xf100_0134 FW_START Bit Description Reset Value Reserved 31 1 Reserved 0 FW_START 0 When this bit is set to 1 the FW starts encoding decoding 1 9 2 14 ARM ENDIAN SETTING REGISTER ARM_ENDIAN R W ADDRESS 0xf100_...

Page 1607: ...RMAT CODEC 9 11 39 9 2 15 ERROR CONTROL SETTING REGISTER ERR_CTRL R W ADDRESS 0xf100_013c ERR_CTRL Bit Description Reset Value Reserved 31 1 Reserved 0 ERR_CTRL 0 When error mets 0 Concealment ON and decoding one frame 1 Interrrupt and stop 0 ...

Page 1608: ...T ADDRESS REGISTER FW_STT_ADDR_2 R W ADDRESS 0xf100_0208 FW_STT_ADDR Bit Description Reset Value FW_STT_ADDR_2 31 0 This is H 264 encoder F W start address 0 9 3 4 FIRMWARE START ADDRESS REGISTER FW_STT_ADDR_3 R W ADDRESS 0xf100_020c FW_STT_ADDR Bit Description Reset Value FW_STT_ADDR_3 31 0 This is H 264 decoder F W start address 0 9 3 5 FIRMWARE START ADDRESS REGISTER FW_STT_ADDR_4 R W ADDRESS 0...

Page 1609: ...TTING REGISTER VSP_BUF_ADDR R W ADDRESS 0xf100_0230 FW_STT_ADDR Bit Description Reset Value VSP_BUF_ADDR 31 0 VSP temporal buffer start address VSP temporal buffer use temporal SPS PPS data saving area The size needs about 327 kbytes Or 81 75K Words 0 9 3 9 DEBLOCK LINE BUFFER SETTING ADDRESS DB_STT_ADDR R W ADDRESS 0xf100_0234 FW_STT_ADDR Bit Description Reset Value DB_STT_ADDR 31 0 Deblock Line ...

Page 1610: ...supported 1 1 3 1 ex 31 stands for level 3 1 When RC is disable Host must set 31 0 Reserved 7 5 reserved PROFILE 4 0 MPEG4 0 SP 1 ASP H 264 0 Baseline 1 Main 2 High H 264 0 Baseline 0 9 4 2 I PICTURE PERIOD REGISTER I_PERIOD R W ADDRESS 0xf100_0308 I_PERIOD Bit Description Reset Value Reserved 31 16 Reserved 0 I_PERIOD 15 0 The number of P picture 16 hFFFF all sequence P picture 16 h0 all sequence...

Page 1611: ...ved 31 12 Reserved SLICE_ALPHA_C0_OFFSE T_DIV2 11 7 Slice_alpah_c0_offset_div2 value in slice header This value is 2 s complement value This value s range is 6 to 6 0x00 SLICE_BETA_OFFSET_ DIV2 6 2 Slice_beta_offset_div2 value in slice header This value is 2 s complement value This value s range is 6 to 6 0x00 DISABLE_DEBLOCKING_FILT ER_IDC 1 0 Disable deblocking filter IDC in slice header 0 All b...

Page 1612: ...cing is done by MB count value 1 Multi slicing is done by byte count value 2 Multi slicing is done by variable MB count value 0 9 4 8 MULTI SLICE INTERVAL REGISTER MSLICE_MB R W ADDRESS 0xf100_0324 MSLICE_MB Bit Description Reset Value MSLICE_MB 31 0 This register is used MSLICE_ENA 1 and When MSLICE_SEL 0 number of MB per slice MSLICE_MB value can be 1 to Horizontal image size Vertical image size...

Page 1613: ...ay Chrominance address 0 9 5 3 DISPLAY STATUS REGISTER DISPLAY_STATUS R ADDRESS 0xf100_0408 DISPLAY_STATUS Bit Description Reset Value Reserved 31 4 Reserved 0 ERROR_GEN 4 1 Error detected at the current frame decoding 0 No error 0 DISPLAY_STATUS 3 0 This register shows the status of display 0 decoding only 1 0 0 decoding only no display 1 decoding and display 2 display only 2 0 progressive frame ...

Page 1614: ...polling mode 0 interrupt enable 1 interrupt disable 0 9 6 2 INTERRUPT LEVEL SELECTION CONTROL REGISTER INT_PULSE_SEL R W ADDRESS 0xf100_0504 INT_PULSE_SEL Bit Description Reset Value Reserved 31 1 Reserved 0 INT_PULSE_SEL 0 0 Level Interrupt 1 Pulse Interrupt 0 9 6 3 INTERRUPT CLEAR REGISTER INT_DONE_CLEAR R W ADDRESS 0xf100_0508 INT_DONE_CLEAR Bit Description Reset Value Reserved 31 1 Reserved 0 ...

Page 1615: ...0xf100_0514 INT_STATUS Bit Description Reset Value Reserved 31 9 Reserved 0 FRAME_DONE_STAT 8 Frame done status 0 DMA_DONE_STAT 7 DMA done status 0 Reserved 6 Reserved 0 FW_DONE_STAT 5 FW done status 0 Reserved 4 0 Reserved 0 9 6 7 INTERRUPT ENABLE REGISTER INT_ENABLE_REG R W ADDRESS 0xf100_0518 INT_MASK_REG Bit Description Reset Value Reserved 31 9 Reserved 0 FRAME_DONE_ENABLE 8 Frame done enable...

Page 1616: ...nterrupt signal IREQ is active HIGH and is retained till the host processor clears it by writing 1 to interrupt clear register of the host interface As interrupt sources there re 3 signals 1 Frame done signal means the end of frame s encoding decoding 2 DMA done signal means the end of DMA s whole job in VSP during a job of loading initial F W 3 F W done signal means that F W s job ends completely...

Page 1617: ... when encoder wants to set tile mode Decoder has to set 3 only when decoder wants to set tile mode 0 Tile mode memory size calculation fomular One frame size can be calculated using below formular if luma pixel_x hor_img_size hor_img_offset ex 1280 pixel_y ver_img_size ver_img_offset ex 720 else chorma pixel_x hor_img_size hor_img_offset ex 1280 pixel_y ver_img_size ver_img_offset 2 ex 360 pixel_x...

Page 1618: ...This vaule is added value for making multiple by 16 ex IMG_OFFSET is 3 when IMG_SIZE is 77 Ex DPB_addr_0 base_addr DPB_addr_1 base_addr pic_range 13 Table 9 11 3 Example of Pic_range image_size pic_range 1280x720 115 720x480 45 352x288 14 176x144 5 NOTE1 example address DPB_addr_0 12 0 Base_addr must be set to 0 i e All base address lower 13 bit must be set to 0 Value NOTE2 At this case picure ver...

Page 1619: ...R 31 0 External memory setting address Current Cb Cr image start address This chrominance format is 2 plane interleaving mode 0 9 8 3 ENCODER DPB START ADDRESS REGISTER ENC_DPB_ADDR R W ADDRESS 0xf100_080c ENC_DPB_ADDR Bit Description Reset Value ENC_DPB_ADDR 31 0 DPB start address Encoder DPB area is two frame data size Frame size calcultion methods have to confer MEM_STRUCT_SET register 0 9 8 4 ...

Page 1620: ...n of errors for too long a time This is done by intra coding a few macroblocks per frame In CIR for a macroblock to be considered refreshed it has to be intra coded a predefined number of macroblock Thus this technique has one control parameters of macroblck numbers In Figure 9 11 16 that case macrblock number is 10 Cyclic Intra refresh CIR is set by external host at the first Special Function Reg...

Page 1621: ...er 2 frame VC 1 decoder 4 frame 0 9 9 2 COLOCATED MOTION VECTOR BUFFER ADDRESS REGISTER DPB_COMV_ADDR R W ADDRESS 0xf100_0904 DPB_COMV_ADDR Bit Description Reset Value DPB_COMV_ADDR 31 0 Exteranl temporal address DPB Colocated MV saving buffer start address NOTE Make reference of DPB_COMV_ADDR buffer size below value H 264 decoder DPB_Colocated_buffer_size 128 byte x hor_img_size hor_img_offset 16...

Page 1622: ... this register uses DPB buffer for Display VC1 No use this register uses DPB buffer for Display H 263 No use this register uses DPB buffer for Display MPEG4 MPEG2 3 frame buffer sizes 0 9 9 4 DECODED PICTURE BUFFER SIZE RETURN VALUE SETTING REGISTER DPB_SIZE R ADDRESS 0xf100_090c DPB_SIZE Bit Description Reset Value Reserved 31 8 Reserved 0 DPB_SIZE 7 0 MFC indicates to host about decoded picture ...

Page 1623: ...se RC_CONFIG 9 8 is 2 b00 Constant quantization parameter QP is applied to all macroblocks in the current picture Case RC_CONFIG 9 8 is 2 b01 Quantization parameter QP of the first macroblock in the current frame The QP of the next macroblocks can be obtained by macroblock adaptive scaling Case RC_CONFIG 9 8 is 2 b10 FRAME_QP can be changed by the difference between the numbers of target bit and g...

Page 1624: ...d 0 MAX_QP 13 8 Maximum quantization parameter 0 51 at H 264 encoding 1 31 at H 263 MPEG4 encoding 0 Reserved 7 6 Reserved 0 MIN_QP 5 0 Minimum quantization parameter 0 51 at H 264 encoding 1 31 at H 263 MPEG4 encoding 0 NOTE For the unbounded range of quantization parameter you have to set this register to 0x0000_3300 e g MAX_QP 51 MIN_QP 0 NOTE MAX_QP must be greater than or equal to MIN_QP 9 10...

Page 1625: ...sable Static Region Adaptive feature 0 Enable Static Region Adaptive feature QP of static MB may be smaller than frame QP 1 Disable Static Region Adaptive feature 0 ACT_DISABLE 0 Disable MB Activity Adaptive feature 0 Enable MB Activity Adaptive feature QP of MB that has small activity may be smaller than frame QP and QP of MB that has large activity may be larger than frame QP 1 Disable MB Activi...

Page 1626: ...S5PC100 USER S MANUAL REV1 0 9 11 58 9 11 MFCV VERSION REGISTER 9 11 1 MFC4 VERSION MFC4_VERSION R ADDRESS 0xf100_0b00 MFC4_VERSION Bits Description Reset Value MFC_VERSION 31 0 MFC codec version checking register 0x0000_0040 ...

Page 1627: ... left offset information 0 NOTE When DISPLAY_STATUS 3 is 1 It is valid 9 12 2 MFC4 CROPPING INFORMATION REGISTER TWO MFC_CROP2 R ADDRESS 0xf100_0c04 MFC_CROP1 Bits Description Reset Value CROP_BOTTOM_OFFSET 31 16 Cropping bottom offset information 0 CROP_TOP_OFFSET 15 0 Cropping top offset information 0 NOTE When DISPLAY_STATUS 3 is 1 It is valid 9 12 3 MFC4 Decoded Frame Size MFC_DEC_FRM_SIZE R A...

Page 1628: ...DDRESS 0xf100_0c0c FRAME_TYPE Bits Description Reset Value Reserved 31 2 Reserved 0 FRAME_TYPE 1 0 Encoding 0 Not coded frame 1 I frame 2 P frame Decoding 0 Not coded frame 1 I frame 2 P frame 3 B frame 0 9 14 2 Number of extra dpb register NUM_EXTRA_DPB W Address 0xf100_0d04 NUM_EXTRA_DPB Bits Description Reset Value DISPLAY_DELAY 31 16 Number of frames for display delay MFC is forced to return f...

Page 1629: ... the same as the decode order regardless of POC type The decoded frame can be displayed immediately and therefore DISPLAY_STATUS 1 0 1 always 0 Normal operation 1 Disable reordering for immediate display 0 INSERT_NOTCODED_FRAME 1 A not coded frame is inserted in the middle of MPEG4 encoding 0 Normal operation 1 Not coded frame insertion 0 INSERT_I_FRAME 0 An I frame is inserted in the middle of an...

Page 1630: ...e audio playback time The Audio Sub system has an AHB bus component an I2S controller and an SRAM wrapper The SRAM wrapper uses the RAM of CAMIF0 and CAMIF1 as a buffer for sound data To save power efficiently CPU saves sound data to the SRAM wrapper Then all the other power domains are turned off while the Audio Sub system plays the data ...

Page 1631: ...0 Scaler Rotator SRAM FIMC1 Scaler Rotator SRAM AHB Slave Interface W Addr W Data W Addr W Data FIMC CLK HCLKD2 CLK R Data AHB BUS CPU Write DMA Read R Addr R Addr R Addr R Data AHB M Signal Protector APB Interface I2S 5 1 Ch APB 0x1FFFF 128K 0x00 AUDIO Sub System Figure 10 1 1 Audio Sub system Block Diagram ...

Page 1632: ...e instead of enlarging I2S internal buffer In S5PC100x to make 128 KB buffer for I2S in low power MP3 mode SRAM wrapper module has rotation SRAM buffers in CAMIF0 and CAMIF1 The address range on SRAM related to CAMIF is 0xC000_0000 0xC000_1FFF if LPMP3_MODE_SEL bit in Clock Controller module is on SRAM wrapper also has AHB slave interface AHB slave interface handles single read transactions from I...

Page 1633: ...per switches rotation buffers in CAMIF to temporary sound buffers CPU can transfer decoded MP3 data to SRAM wrapper in Audio sub system If the proper size of MP3 decoded data is in SRAM wrapper internal DMA in I2S is turned on to supply decoded MP3 data from SRAM wrapper to I2S internal FIFO After CPU transfers all the decoded MP3 data to SRAM wrapper S5PC100 enters to Deep IDLE mode 4 Exit from D...

Page 1634: ...ed and DMA transfer mode to transmit or receive samples is supported I2S specific clock is supplied from internal system clock controller through I2S clock divider or direct clock source I2S V5 0 I2S0 handles up to 2 sound sources For example default system sound using OS s w sound mixer is delivered to primary sound path and special application bypassing OS s w sound mixer to secondary sound path...

Page 1635: ...onal block diagram of I2S interface 4 1 MASTER SLAVE MODE Set IMS bit of I2SMOD register to select master or slave mode In master mode I2SSCLK and I2SLRCLK are generated internally and supplied to external device Therefore a root clock is needed for generating I2SSCLK and I2SLRCLK The I2S pre scaler clock divider generates a root clock with divided frequency from internal system clock In external ...

Page 1636: ...TXFIFO_S and RXFIFO I2S mixes primary sound in TXFIFO0 and secondary sound in TXFIFO_S and output mixed sound stream to external codec logic In the external DMA transfer mode the transmitter or receiver FIFO are accessible by external DMA controller DMA service request is activated internally by the transmitter or receiver FIFO state The FTXEMPT FRXEMPT FTXFULL and FRXFULL bits of I2SCON register ...

Page 1637: ...ode in the internal DMA transfer mode the internal DMA is activated if TXFIFO_S is not full If activated internal DMA runs according to SFR configurations and signals an interrupt after completion 4 1 3 Sound Mixing I2S mixes primary sound in TXFIFO0 and secondary sound in TXFIFO_S if two sound sourses have the same sampling rate and PCM format I2S Sound Source 1 Sound Source N 1 Sound Source N Vo...

Page 1638: ...SLRCLK is changed either on a trailing or leading edge of the serial clock but it does not need to be symmetrical In the slave this signal is latched on the leading edge of the clock signal The I2SLRCLK line changes one clock period before the MSB is transmitted This allows the slave transmitter to derive synchronous timing of the serial data that is set up for transmission Furthermore it enables ...

Page 1639: ...T SD MSB Justified Left Justified Format N 8 or 16 BCLK LRCLK LEFT RIGHT SD LSB Justified Right Justified Format N 8 or 16 MSB 1st 2nd Bit N 1th Bit MSB 1st 2nd Bit N 1th Bit MSB 1st 2nd Bit N 1th Bit MSB 1st 2nd Bit N 1th Bit 1st Bit N 2th Bit LSB N 1th 1st Bit N 2th Bit LSB N 1th Figure 10 2 5 I2S Audio Serial Data Formats ...

Page 1640: ...880 16 3840 22 5792 24 5760 384fs 3 0720 4 2336 6 1440 8 4672 12 2880 16 9344 18 4320 24 5760 33 8688 36 8640 512fs 4 0960 5 6448 8 1920 11 2900 16 3840 22 5790 24 5760 32 7680 45 1580 49 1520 768fs CODE CLK MHz 6 1440 8 4672 12 2880 16 9340 24 5760 33 8690 36 8640 49 1520 67 7380 73 7280 5 5 I2S CLOCK MAPPING TABLE Before selecting BFS RFS and BLC bits of I2SMOD register please refer to the Table...

Page 1641: ...e For more information refer to Section 5 1 Master Slave 2 To configure I2SMOD register and I2SPSR I2S pre scaler register properly 3 To operate system in stability the internal TXFIFO should be almost full before transmission Starts DMA to fill TXFIFO 4 Basically I2S bus does not support the interrupt Therefore you check state by polling through accessing SFR 5 If TXFIFO is full assert the I2SACT...

Page 1642: ...PCLK and CODCLKI are coming correctly to the I2S controller and FLUSH the TX FIFO using the TFLUSH bit in the I2SFIC Register I2S FIFO Control Register Please ensure that I2S Controller is configured in one of the following modes TX only mode TX RX simultaneous mode This is done by programming the TXR bit in the I2SMOD Register I2S Mode Register 1 Then Program the following parameters according to...

Page 1643: ...e TX FIFO for 8 bit channel or 16 bit channel BLC are shown in below figure 0 15 16 31 LOC 0 7 BLC 00 BLC 01 RIGHT CHANNEL LEFT CHANNEL LOC 1 LOC 2 LOC 3 LOC 4 LOC 5 LOC 6 LOC 7 LOC 8 LOC 9 LOC 10 LOC 11 LOC 12 LOC 13 LOC 14 LOC 15 Figure 10 2 6 TX FIFO Structure for BLC 00 or BLC 01 ...

Page 1644: ...the serial data transmission on the I2SSDO The transmission is stopped once the current Left Right channel is transmitted If the control registers in the I2SCON Register I2S Control Register and I2SMOD Register I2S Mode Register are to be reprogrammed then it is advisable to disable the TX channel If the TX channel is enabled while the FIFO is empty no samples are read from the FIFO The Status of ...

Page 1645: ...oller is configured in any of the following modes Receive only Receive Transmit simultaneous mode This is done by Programming the TXR bit in the I2SMOD Register I2S Mode Register 1 Then Program the following parameters according to the need IMS SDF BFS BLC LRP For Programming the above mentioned fields please refer to I2SMOD Register I2S Mode Register 2 After ensuring that the input clocks for I2S...

Page 1646: ... CONTROLLER 5 1CH 10 2 13 0 15 16 31 LOC 0 7 BLC 00 BLC 01 RIGHT CHANNEL LEFT CHANNEL LOC 1 LOC 2 LOC 3 LOC 4 LOC 5 LOC 6 LOC 7 LOC 8 LOC 9 LOC 10 LOC 11 LOC 12 LOC 13 LOC 14 LOC 15 Figure 10 2 8 RX FIFO Structure for BLC 00 or BLC 01 ...

Page 1647: ... Left Right channel is received If the control registers in the I2SCON Register I2S Control Register and I2SMOD Register I2S Mode Register are to be reprogrammed then it is advisable to disable the RX channel Check the Status of RX FIFO by checking the bits in the I2SFIC Register I2S FIFO Control Register LOC 0 LOC 1 LOC 2 LOC 3 LOC 4 LOC 5 LOC 6 LOC 7 LOC 8 LOC 9 LOC 10 LOC 11 LOC 12 LOC 13 LOC 1...

Page 1648: ...Xi2s0SCLK Dedicated I2S0_LRCK I O LR Channel Clock Input Xi2s0LRCK Dedicated I2S0_CDCLK I O Codec Clock Out Xi2s0CDCLK Dedicated I2S0_SDI I I2S Serial Data Input Xi2s0SDI Dedicated I2S0_SDO 0 O I2S Serial Data Out 0 Xi2s0SDO 0 Dedicated I2S0_SDO 1 O I2S Serial Data Out 1 Xi2s0SDO 1 Dedicated I2S0_SDO 2 O I2S Serial Data Out 2 Xi2s0SDO 2 Dedicated ...

Page 1649: ...Address Register 0x0 I2SSIZE 0xF200_0028 R W I2S AHB DMA Size Register 0x8000_0000 I2STRNCNT 0xF200_002C R I2S AHB DMA Transfer Count Register 0x0 I2SLVL0ADDR 0xF200_0030 R W I2S AHA DMA Interrupt Level 0 Register 0x0000_0000 I2SLVL1ADDR 0xF200_0034 R W I2S AHA DMA Interrupt Level 1 Register 0x0000_0000 I2SLVL2ADDR 0xF200_0038 R W I2S AHA DMA Interrupt Level 2 Register 0x0000_0000 I2SLVL3ADDR 0xF2...

Page 1650: ...t full 1 TX FIFO_S is full R 0 TXSDMAPAUSE 20 Tx DMA operation for secondary TX FIFIO_S pause command Note If this bit is activated at any time the DMA request halts after current on going DMA transfer is complete 0 No pause DMA operation for TX FIFO_S 1 Pause DMA operation for TX FIFO_S R W 0 Reserved 19 Reserved R 0 TXSDMACTIVE 18 Tx DMA active for secondary TX FIFO_S start DMA request Note If t...

Page 1651: ...dication 0 FIFO is not empty ready for transmit data to channel 1 FIFO is empty not ready for transmit data to channel R 0 FRXEMPT 9 Rx FIFO empty status indication 0 FIFO is not empty 1 FIFO is empty R 0 FTX0FULL 8 Primary Tx FIFO0 full status indication 0 FIFO is not full 1 FIFO is full R 0 FRXFULL 7 Rx FIFO full status indication 0 FIFO is not full Ready to receive data from channel 1 FIFO is f...

Page 1652: ...A operation is forced to stop immediately 0 Inactive 1 Active R W 0 RXDMACTIVE 1 Rx DMA active start DMA request Note If this bit is set from high to low the DMA operation is forced to stop immediately 0 Inactive 1 Active R W 0 I2SACTIVE 0 I2S interface active start operation 0 Inactive 1 Active R W 0 8 2 I2S INTERFACE MODE REGISTER I2SMOD R W ADDRESS 0XF200_0004 I2SMOD Bit Description R W Reset V...

Page 1653: ...00 Reserved 23 22 Reserved R 00 CDD2 21 20 Channel 2 Data Discard Discard means zero padding It only supports 8 16 bit mode 00 No Discard 01 I2STXD 15 0 Discard 10 I2STXD 31 16 Discard 11 Reserved R W 00 CDD1 19 18 Channel 1 Data Discard Discard means zero padding It only supports 8 16 bit mode 00 No Discard 01 I2STXD 15 0 Discard 10 I2STXD 31 16 Discard 11 Reserved R W 00 DCE 17 16 Data Channel E...

Page 1654: ...igure 10 2 2 and Figure 10 2 3 R W 00 TXR 9 8 Transmit or receive mode select 00 Transmit only mode 01 Receive only mode 10 Transmit and receive simultaneous mode 11 Reserved R W 00 LRP 7 Left Right channel clock polarity select 0 Low for left channel and high for right channel 1 High for left channel and low for right channel R W 0 SDF 6 5 Serial data format 00 I2S format 01 MSB justified left ju...

Page 1655: ...X FIFO flush command 0 No flush 1 Flush R W 0 FTX0CNT 14 8 Primary TX FIFO0 data count FIFO has 16 dept therefore value ranges from 0 to 16 N Data count N of FIFO R 0x00 RFLUSH 7 RX FIFO flush command 0 No flush 1 Flush R W 0 FRXCNT 6 0 RX FIFO data count FIFO has 16 dept so value ranges from 0 to 16 N Data count N of FIFO R 0x00 8 4 I2S INTERFACE CLOCK DIVIDER CONTROL REGISTER I2SPSR R W ADDRESS ...

Page 1656: ...RESS 0XF200_0014 I2SRXD Bit Description R W Reset Value I2SRXD 31 0 RX FIFO read data Note The left right channel data is allocated as the following bit fields R 31 16 L 15 0 if 16 bit BLC R 23 16 L 7 0 if 8 bit BLC Refer to Figure 10 2 9 if 24 bit BLC R 0x00 8 7 I2S INTERFACE TXFIFO_S CONTROL REGISTER I2SFICS R W ADDRESS 0XF200_0018 I2SFICS Bit Description R W Reset Value Reserved 31 16 Reserved ...

Page 1657: ...VL1EN 25 Enable buffer level 1 interrupt 0 Disables I2SLVL1INT 1 Enables I2SLVL1INT R W 0 I2SLVL0EN 24 Enable buffer level 0 interrupt 0 Disables I2SLVL0INT 1 Enables I2SLVL0INT R W 0 I2SLVL3INT 23 Buffer level 3 interrupt status flag During DMA operation if generated address in DMA matches with I2SLVL3ADDR this flag is set To clear this flag use I2SLVL3CLR field R 0 I2SLVL2INT 22 Buffer level 2 i...

Page 1658: ...to reload I2S internal DMA Configuration if DMA operation is done and re start I2S internal DMA automatically 0 Disables auto reload function 1 Enables auto reload function Before switching to 0 from 1 s w must check if DMA_EN is set R W 0 Reserved 4 Reserved R 0 I2SINTMASK 3 Disable interrupt request signal 0 Enables interrupt request if DMA auto reload is on 1 Disables interrupt request if DMA a...

Page 1659: ...n for AHB and TXFIFO0 holds data returned by DMA Warning If I2SDMARLD is set I2SDMAEN bit is automatically cleared when all the transfer specified in SFR is done Then I2SDMAEN bit is automatically set after auto reload operation is done If auto reload operation is ongoing s w intervention on this field causes mal function of internal DMA operations To manipulate I2SAHB register s w must check that...

Page 1660: ...ned address only To get best performance I2SSTR should be 64 word aligned address Valid address range for I2SSTR is from 0xC000_0000 to 0xC01F_FFFF R W 0x00 8 11 I2S AHB DMA SIZE REGISTER I2SSIZE R W ADDRESS 0XF200_0028 I2SSIZE Bit Description R W Reset Value TRNS_SIZE 31 16 Transfer block size for I2S internal DMA If I2S internal DMA is enabled I2S internal DMA transfers TRNS_SIZE word s data fro...

Page 1661: ...pped R 8 13 I2S AHB DMA LEVEL 0 INTERRUPT ADDRESS REGISTER I2SLVL0ADDR R W ADDRESS 0XF200_0030 I2SLVL0ADD R Bit Description R W Reset Value I2SLVL0ADDR 31 10 AHB DMA level 0 interrupt address While I2SLVL0EN in I2SAHB register is set AHB DMA compares this register to generated address in DMA If two values match I2SLVL0INT in I2SAHB is set Valid address range for I2SLVL0ADDR is from 0xC000_0000 to ...

Page 1662: ...on 1 Stop DMA operation if DMA working addresses is matched with I2SLVL1ADDR I2SDMAEN in I2SAHB is turned off automatically R W 0 8 15 I2S AHB DMA LEVEL 2 INTERRUPT ADDRESS REGISTER I2SLVL2ADDR R W ADDRESS 0XF200_0038 I2SLVL2ADD R Bit Description R W Reset Value I2SLVL2ADDR 31 10 AHB DMA level 2 interrupt address While I2SLVL2EN in I2SAHAB register is set AHB DMA compares this register to generate...

Page 1663: ...While I2SLVL3EN in I2SAHB register is set AHB DMA compares this register to generated address in DMA If two values match I2SLVL3INT in I2SAHB is set Valid address range for I2SLVL3ADDR is from 0xC000_0000 to 0xC01F_FFFF R 0x00 Reserved 9 1 Reserved R 0x00 I2SLVL3STOP 0 Precise stop enable 0 Do not stop DMA operation 1 Stop DMA operation if DMA working addresses is matched with I2SLVL3ADDR I2SDMAEN...

Page 1664: ...S5PC100 USER S MANUAL REV1 0 I2S CONTROLLER 5 1CH 10 2 31 NOTES ...

Page 1665: ... a line for two time multiplexed data channels a word select line and a clock line I2S interface transmits or receives sound data from external stereo audio codec To transmit or receive data two 32x16 First In First Out FIFO data structures are included and DMA transfer mode to transmit or receive samples is supported I2S specific clock is supplied from internal system clock controller through I2S...

Page 1666: ...Therefore a root clock is needed for generating I2SSCLK and I2SLRCLK by dividing The I2S pre scaler clock divider generates a root clock with divided frequency from internal system clock In external master mode the root clock is fed directly from external I2S The I2SSCLK and I2SLRCLK are supplied from the pin GPIOs in slave mode Master Slave mode is different with TX RX Master Slave mode presents ...

Page 1667: ...ctivation the data read or write operation should be performed Reference DMA request point TX mode FIFO is not full and TXDMACTIVE is active RX mode FIFO is not empty and RXDMACTIVE is active 4 3 AUDIO SERIAL DATA FORMAT 4 3 1 I2S bus format The I2S bus has four lines including serial data input I2SSDI serial data output I2SSDO left right channel select clock I2SLRCLK and serial bit clock I2SBCLK ...

Page 1668: ...UAL REV1 0 10 3 4 This allows the slave transmitter to derive synchronous timing of the serial data that will be set up for transmission Furthermore it enables the receiver to store the previous word and clears the input for the next word ...

Page 1669: ...SLRCLK transition Figure 10 3 3 shows the audio serial format of I2S MSB justified and LSB justified Note that in this figure the word length is 16 bit and I2SLRCLK makes transition every 24 cycle of I2SBCLK BFS is 48 fs where fs is sampling frequency I2SLRCLK frequency BCLK LRCLK LEFT RIGHT SD I 2 S Format N 8 or 16 BCLK LRCLK LEFT RIGHT SD MSB Justified Left Justified Format N 8 or 16 BCLK LRCLK...

Page 1670: ...2 2880 16 3840 22 5792 24 5760 384fs CODECLK 3 0720 4 2336 6 1440 8 4672 12 2880 16 9344 18 4320 24 5760 33 8688 36 8640 MHz 512fs 4 0960 5 6448 8 1920 11 2900 16 3840 22 5790 24 5760 32 7680 45 1580 49 1520 768fs 6 1440 8 4672 12 2880 16 9340 24 5760 33 8690 36 8640 49 1520 67 7380 73 7280 4 3 5 I2S clock mapping table Before selecting BFS RFS and BLC bits of I2SMOD register please refer to Table...

Page 1671: ... MODE WITH DMA 1 RXFIFO is flushed before operation If you do not distinguish between Master Slave mode and TX RX mode you must study Master Slave mode and TX RX mode For more information refer to Section Master Slave chapter 2 To configure I2SMOD register and I2SPSR I2S pre scaler register properly 3 To operate system in stability the internal RXFIFO should have minimum one data before DMA operat...

Page 1672: ... 0 10 3 8 TX RX simultaneous mode TBD 0 15 16 31 LOC 0 7 BLC 00 BLC 01 RIGHT CHANNEL LEFT CHANNEL LOC 1 LOC 2 LOC 3 LOC 4 LOC 5 LOC 6 LOC 7 LOC 8 LOC 9 LOC 10 LOC 11 LOC 12 LOC 13 LOC 14 LOC 15 Figure 10 3 4 TX FIFO Structure for BLC 00 or BLC 01 ...

Page 1673: ...de Data is received from the input line and transferred into the RX FIFO The processor then reads this data via an APB read or a DMA access can access this data RX Channel has a 16X32 bit wide RX FIFO where the processor or DMA reads upto 16 left right data samples after enabling the channel for reception LOC 0 LOC 1 LOC 2 LOC 3 LOC 4 LOC 5 LOC 6 LOC 7 LOC 8 LOC 9 LOC 10 LOC 11 LOC 12 LOC 13 LOC 1...

Page 1674: ... MANUAL REV1 0 10 3 10 TBD 0 15 16 31 LOC 0 7 BLC 00 BLC 01 RIGHT CHANNEL LEFT CHANNEL LOC 1 LOC 2 LOC 3 LOC 4 LOC 5 LOC 6 LOC 7 LOC 8 LOC 9 LOC 10 LOC 11 LOC 12 LOC 13 LOC 14 LOC 15 Figure 10 3 6 RX FIFO Structure for BLC 00 or BLC 01 ...

Page 1675: ...BLC as shown in the figure below Figure 10 3 7 RX FIF0 Structure for BLC 10 24 bit channel TBD LOC 0 LOC 1 LOC 2 LOC 3 LOC 4 LOC 5 LOC 6 LOC 7 LOC 8 LOC 9 LOC 10 LOC 11 LOC 12 LOC 13 LOC 14 LOC 15 BLC 10 24 bit channel 0 23 31 LEFT CHANNEL RIGHT CHANNEL LEFT CHANNEL RIGHT CHANNEL INVALID INVALID INVALID INVALID ...

Page 1676: ... I2S1_SCLK Input Output I2S1 Bit Clock Input Output Xi2s1SCLK muxed I2S1_LRCK Input Output I2S1 LR Channel Clock Input Output Xi2s1LRCK muxed I2S1_SDI Input I2S1 Serial Data Input Xi2s1SDI muxed I2S1_SDO Output I2S1 Serial Data Out Xi2s1SDO muxed I2S2_CDCLK Input Output I2S2 Codec Clock Input Output Xmmc2CMD muxed I2S2_SCLK Input Output I2S2 Bit Clock Input Output Xmmc2CLK muxed I2S2_LRCK Input Ou...

Page 1677: ...unit with STR LDR instructions 8 2 DETAILED DESCRIPTION 8 2 1 I2S interface control register I2SCON R W Address 0XF210_0000 0XF220_0000 y I2SCON1 R W Address 0XF210_0000 y I2SCON2 R W Address 0XF220_0000 I2SCON Bit Description R W Reset Value Reserved 31 20 Reserved R W FRXOFSTATUS 19 RX FIFO OverFlow Interrupt Status This is used by interrupt clear bit If this is high write 1 to clear interrupt 0...

Page 1678: ...DMAPAUSE 6 Tx DMA operation pause command Note If this bit is activated at any time the DMA request halts after current on going DMA transfer is complete 0 No pause DMA operation 1 Pause DMA operation R W RXDMAPAUSE 5 Rx DMA operation pause command Note If this bit is activated at any time the DMA request halts after current on going DMA transfer is complete 0 No pause DMA operation 1 Pause DMA op...

Page 1679: ... Bit Description R W Reset Value RXDMACTIVE 1 Rx DMA active start DMA request Note If this bit is set from high to low the DMA operation is forced to stop immediately 0 Inactive 1 Active R W I2SACTIVE 0 I2S interface active start operation 0 Inactive 1 Active R W ...

Page 1680: ...W IMS 11 10 I2S master internal external or slave mode select 00 Master mode divide mode using PCLK 01 Master mode bypass mode using I2SCLK 10 Slave mode divide mode using PCLK 11 Slave mode bypass mode using I2SCLK For more information refer to Figure 10 3 2 R W TXR 9 8 Transmit or receive mode select 00 Transmit only mode 01 Receive only mode 10 Transmit and receive simultaneous mode 11 Reserved...

Page 1681: ...mand 0 No flush 1 Flush R W Reserved 14 13 Reserved R W FTXCNT 12 8 TX FIFO data count FIFO has 16 dept therefore value ranges from 0 to 16 N Data count N of FIFO R RFLUSH 7 RX FIFO flush command 0 No flush 1 Flush R W Reserved 6 5 Reserved R W FRXCNT 4 0 RX FIFO data count FIFO has 16 dept therefore value ranges from 0 to 16 N Data count N of FIFO R 8 2 4 I2S Interface Clock Divider Control Regis...

Page 1682: ...2S CONTROLLER 2CH S5PC100 USER S MANUAL REV1 0 10 3 18 I2SPSR Bit Description R W Reset Value PSVALA 13 8 Pre scaler Clock divider A division value N Division factor is N 1 R W Reserved 7 0 Reserved R W ...

Page 1683: ...e information refer to Figure10 3 4 10 3 5 R L 23 0 when 24 bit BLC R 31 16 L 15 0 when 16 bit BLC R 23 16 L 7 0 when 8 bit BLC W 8 2 6 I2S Interface Receive Data Register I2SRXD R Address 0XF210_0014 0XF220_0014 y I2SRXD1 R Address 0XF210_0014 y I2SRXD2 R Address 0XF220_0014 I2SRXD Bit Description R W Reset Value I2SRXD 31 0 RX FIFO read data Note that the left right channel data is allocated as ...

Page 1684: ...audio sample to an analog audio waveform The Controller receives the stereo PCM data and the mono Mic data from Codec then stores in memories This chapter describes the programming model for the AC97 Controller Unit The prerequisite to understand this chapter requires a knowledge of the AC97 revision 2 0 specifications 2 FEATURE The AC97 Controller includes the following features Independent chann...

Page 1685: ...the functional block diagram of S5PC100 AC97 Controller The AC97 signals form the AC link which is a point to point synchronous serial inter connecting that supports full duplex data transfers All digital audio streams and command status information are communicated through AC link APB I F DMA Engine Interrupt Control MIC in FIFO PCM out FIFO PCM in FIFO SFR AC link I F FSM Control APB AC link Fig...

Page 1686: ...uffers which consist of 16 bit and 16 entries buffer It also has 20 bit I O shift register via AC link Command Addr Register Command Data Register PCM Out Buffer Regfile 16 bit x 2 x 16 Entry PWDATA Response Data Register Mic In Buffer RegFile 16 bit x16 Entry PCM In Buffer Regfile 16 bit x 2 x 16 Entry PRDATA Input Shift Register 20 bit Output Shift Register 20 bit SDATA_IN SDATA_OUT Figure 10 4 ...

Page 1687: ... you must de assert codec ready interrupt Now transmit data from memory to register or from register to memory by using DMA or PIO directly to write data to register If internal FIFOs TX FIFO or RX FIFO are not empty then let data be transmitted In addition you can previously turn on AC Link System reset or Cold reset Set GPIO and Release INTMSK SUBINTMSK bits Enable Codec Ready interrupt Codec Re...

Page 1688: ...ase contains one bit that identifies a valid frame and 12 bits that identify the time slots in the Data Phase that contain valid data Each time slot in the Data Phase is 20 bits long A frame begins when SYNC goes high The amount of time that SYNC is high corresponds to the Tag Phase AC97 frames occur at fixed 48 kHz intervals and are synchronous to the 12 288 MHz bit rate clock BITCLK The controll...

Page 1689: ...9 4 is valid data Slot 3 PCM Playback Left channel Slot 3 which is audio output frame is the composite digital audio left stream If a sample has a resolution that is less than 16 bits the AC97 controller fills all training non valid bit positions in the slot with zeroes Slot 4 PCM Playback Right channel Slot 4 which is audio output frame is the composite digital audio right stream If a sample has ...

Page 1690: ...ess issued during the most recent read command For multiple sample rate output the CODEC examines its sample rate control registers its FIFOs states and the incoming SDATA_OUT tag bits at the beginning of each audio output frame to determine which SLOTREQ bits to set active low SLOTREQ bits asserted during the current audio input frame indicates which output slots require data from the controller ...

Page 1691: ...el audio Slot 4 which is audio input frame is the right channel audio output of the AC97 Codec If a sample has a resolution less than 16 bits the AC97 Codec fills all training non valid bit positions in the slot with zeroes Slot 6 Microphone Record Data The AC97 Controller only supports 16 bit resolution for the MIC in channel SDATA_OUT BIT_CLK SYNC AC 97 samples SYNC assertion here AC 97 Controll...

Page 1692: ...ire the Codec to process other data when it receives a power down request If the Codec processes the request it immediately transitions BITCLK and SDATA_IN to a logic low level The AC97 Controller drives SYNC and SDATA_OUT to a logic low level after programming the AC_GLBCTRL register 3 6 2 Waking up the AC link Wake Up Triggered by the AC97 Controller AC link protocol provides a cold AC97 reset a...

Page 1693: ...ctivates BITCLK and SDATA_OUT All AC97 control registers are initialized to their default power on reset values nRESET is an asynchronous AC97 input 3 6 4 Warm AC97 Reset A Warm AC97 reset reactivates the AC link without altering the current AC97 register values A warm reset is generated if BITCLK is absent and SYNC is driven high In normal audio frames SYNC is a synchronous AC97 input If BITCLK i...

Page 1694: ...CODEC_READY TRANS_DATA POWER_DOWN WARM_RESET ACLINK_ON 5 CODEC_WAKEUP 5 4 3 6 8 7 6 7 8 2 3 4 9 9 9 9 9 9 COLD_RESET PRESETn Figure 10 4 9 AC97 State Diagram This is the state diagram of AC97 controller It is helpful to understand AC97 controller state machine State above figure is synchronized by peripheral clock PCLK It is able to monitor state at AC_GLBSTAT register ...

Page 1695: ... For mode information refer to the Chapter GPIO Funtion Signal I O Description Pad Type AC97_RESETn Output Active low CODEC Reset Xi2s1CDCLK muxed AC97_BITCLK Input 12 288MHz Bit Rate Clock Xi2s1SCLK muxed AC97_SYNC Output 48 kHz Frame Indicator and Synchronizer Xi2s1LRCK muxed AC97_SDO Output Serial Audio Output Data Xi2s1SDO muxed AC97_SDI Input Serial Audio Input Data Xi2s1SDI muxed ...

Page 1696: ...000 This is the global register of the AC97 controller There are interrupt control registers DMA control registers AC Link control register data transmission control register and related reset control register AC_GLBCTRL Bit Description Reset Value Reserved 31 Reserved 0 Codec ready interrupt clear 30 1 Interrupt clear write only 0 PCM out channel underrun interrupt clear 29 1 Interrupt clear writ...

Page 1697: ...hreshold interrupt enable 16 0 Disables 1 Enables FIFO is half full 0 Reserved 15 14 Reserved 00 PCM out channel transfer mode 13 12 00 Off 01 PIO 10 DMA 11 Reserved 00 PCM in channel transfer mode 11 10 00 Off 01 PIO 10 DMA 11 Reserved 00 MIC in channel transfer mode 9 8 00 Off 01 PIO 10 DMA 11 Reserved 00 Reserved 7 4 Reserved 0000 Transfer data enable using AC link 3 0 Disables 1 Enables 0 AC L...

Page 1698: ...d interrupt 17 0 Not requested 1 Requested 0 MIC in channel threshold interrupt 16 0 Not requested 1 Requested 0 Reserved 15 3 Reserved 0x000 Controller main state 2 0 000 Idle 001 Init 010 Ready 011 Active 100 LP 101 Warm 001 5 2 3 AC97 Codec Command Register AC_CODEC_CMD R W Address 0xF230_0008 When you control writing or reading you must set the Read enable bit If you want to write data to the ...

Page 1699: ...eps 1 Write command address and data on the AC_CODEC_CMD register with Bit 23 1 2 Have a delay time 3 Read command address and data from AC_CODEC_STAT register 5 2 5 AC97 PCM Out In Channel FIFO Address Register AC_PCMADDR R Address 0xF230_0010 To index the internal PCM FIFOs address AC_PCMADDR Bit Description Reset Value Reserved 31 28 Reserved 0000 Out read address 27 24 PCM out channel FIFO rea...

Page 1700: ...Channel FIFO Data Register AC_PCMDATA R W Address 0xF230_0018 This is PCM out in channel FIFO data register AC_PCMDATA Bit Description Reset Value Right data 31 16 PCM out in right channel FIFO data Read PCM in right channel Write PCM out right channel 0x0000 Left data 15 0 PCM out in left channel FIFO data Read PCM in left channel Write PCM out left channel 0x0000 5 2 8 AC97 MIC In Channel FIFO D...

Page 1701: ...AC97 CONTROLLER S5PC100 USER S MANUAL REV1 0 10 4 18 NOTES ...

Page 1702: ...dec 1 1 FEATURE The PCM Audio interface includes the following features ARM APB interface Master mode only this block always sources the main shift clock All PCM serial timings and strobes including the main shift clock are based on an external PCM Audio clock input Optional timing based on the internal APB PCLK Input and output FIFOs to buffer data Optional DMA interface for Tx and or Rx ...

Page 1703: ...being shifted out the PCMSIN input is used to serially shift data in from the external codec The data is received MSB first and is clocked on the falling edge of PCMSCLK The position of the first bit is programmable to correspond with the PCMSYNC or one PCMSCLK later The first 16 bit are serially shifted into the PCM_DATAIN register which is then loaded into the RX FIFO Subsequent bits are ignored...

Page 1704: ... 5 1 PCM Timing POS_MSB_WR RD 0 Figure 10 5 2 shows a PCM transfer with the MSB configured one shift clock after the PCMSYNC This MSB positioning corresponds to setting the MSB_POS_WR and MSB_POS_RD bits in DSP_PCMCTL register to be HIGH PCMSYNC PCMSOUT 15 14 1 0 dont care 15 output output output PCMSCLK input pcm_irq sync to DSP clk 15 14 1 0 dont care 15 input internal PCMSIN PCMCODEC_CLK datain...

Page 1705: ...PTIONS Funtion Signal I O Description Pad Type PCM0_SCLK Output PCM0 Serial Shift Clock Xmmc2CLK muxed PCM0_EXTCLK Input PCM0 External Clock source Xmmc2CMD muxed PCM0_FSYNC Output PCM0 Serial Data Indicator and Synchronizer Xmmc2DATA 0 muxed PCM0_SIN Input PCM0 Serial Input Data Xmmc2DATA 1 muxed PCM0_SOUT Output PCM0 Serial Output Data Xmmc2DATA 2 muxed PCM1_SCLK Output PCM1 Serial Shift Clock X...

Page 1706: ...xF240_0014 R O PCM0 Interrupt Status 0x00000000 PCM_0_FIFO_STAT 0xF240_0018 R O PCM0 Tx Defualt Value 0x00000000 PCM_0_CLRINT 0xF240_0020 W O PCM0 Interrupt Clear PCM_1_CTL 0xF250_0000 R W PCM1 Main Control 0x00000000 PCM_1_CLKCTL 0xF250_0004 R W PCM1 Clock and Shift control 0x00000000 PCM_1_TXFIFO 0xF250_0008 R W PCM1 TxFIFO write port 0x00010000 PCM_1_RXFIFO 0xF250_000C R W PCM1 RxFIFO read port...

Page 1707: ...XDMA uses almost_full as the DMA request keep requesting data until the FIFO is almost full In some circumstances the DMA write one more word after the DMA_req goes away Thus the almost_full flag most go active with at least space for one extra word in the FIFO 0 RXFIFO _DIPSTICK 12 7 Determines if the almost_full and almost_empty flags go active for the RXFIFO Almost_empty fifo_depth fifo_dipstic...

Page 1708: ...falling edge of PCMSCLK during the same cycle that PCMSYNC is high 1 MSB is captured on the falling edge of PCMSCLK during the cycle after the PCMSYNC is high 0 PCM_TXFIFO _EN 2 Enable the TXFIFO If the enable is LOW the internal FIFOs clears and reinitialize 0 PCM_RXFIFO _EN 1 Enable the RXFIFO If the enable is LOW the internal FIFOs clears and reinitialize 0 PCM_PCM _ENABLE 0 PCM enable signal E...

Page 1709: ...PCMCODEC_CLK Final clock is source_clk 2 sclk_div 1 000 SYNC_DIV 8 0 Controls the frequency of the PCMSYNC signal based on the PCMSCLK 000 6 3 THE PCM TX FIFO REGISTER y PCM_0_TXFIFO R W Address 0xF240_0008 y PCM_1_TXFIFO R W Address 0xF250_0008 The bit definitions for the PCM_n_TXFIFO Register are described below PCM_n_TXFIFO Bit Description Reset Value Reserved 31 17 Reserved 0 TXFIFO_DVALID 16 ...

Page 1710: ...d TXFIFO is read using the APB interface 0 6 5 PCM INTERRUPT CONTROL REGISTER y PCM_0_IRQ_CTL R W Address 0xF240_0010 y PCM_1_IRQ_CTL R W Address 0xF250_0010 The PCM_n_IRQ_CTL register is used to control the various aspects of the PCM interrupts The bit definitions for the PCM_n_IRQ_CTL Control Register are described below PCM_n_IRQ_CTL Bit Description Reset Value Reserved 31 15 Reserved 0 EN_IRQ_...

Page 1711: ...VERFLOW 6 Interrupt is generated for TxFIFO overflow ERROR This occurs if the TxFIFO is written when it is already full This is considered as an ERROR and will have unexpected results 1 Enables IRQ source 0 Disables IRQ source 0 RXFIFO_EMPTY 5 Interrupt is generated if the RxFIFO is empty 1 Enables IRQ source 0 Disables IRQ source 0 RXFIFO_ALMOST _EMPTY 4 Interrupt is generated if the RxFIFO is AL...

Page 1712: ...CTL Bit Description Reset Value RXFIFO_ERROR _OVERFLOW 0 Interrupt is generated for RxFIFO overflow ERROR This occurs if the RxFIFO is written when it is already full This is considered as an ERROR and has unexpected results 1 Enables IRQ source 0 Disables IRQ source 0 ...

Page 1713: ...les IRQ source 0 Disables IRQ source 0 TXFIFO_ALMOST _EMPTY 10 Interrupt is generated if the TxFIFO is ALMOST empty Almost empty is defined as FIXME words remaining 1 Enables IRQ source 0 Disables IRQ source 0 TXFIFO_FULL 9 Interrupt is generated if the TxFIFO is full 1 Enables IRQ source 0 Disables IRQ source 0 TXFIFO_ALMOST _FULL 8 Interrupt is generated whenever the TxFIFO is ALMOST full Almost...

Page 1714: ...ce 0 Disables IRQ source 0 RX_FIFO _ALMOST_FULL 2 Interrupt is generated if the RxFIFO is ALMOST full Almost full is defined as FIXME words remaining 1 Enables IRQ source 0 Disables IRQ source 0 RXFIFO_ERROR _STARVE 1 Interrupt is generated for RxFIFO starve ERROR This occurs if the RxFIFO is read when it is still empty This is considered an ERROR and has unexpected results 1 Enables IRQ source 0 ...

Page 1715: ...To indicate RXFIFO usage 0 RXFIFO_EMPTY 3 To indicate whether RXFIFO is empty 0 RXFIFO_ALMOST_EMPTY 2 To indicate whether RXFIFO is almost empty 0 RX_FIFO_FULL 1 To indicate whether RXFIFO is full 0 RX_FIFO_ALMOST_FULL 0 To indicate whether RXFIFO is almost full 0 6 8 PCM INTERRUPT CLEAR REGISTER y PCM_0_CLRINT W O Address 0xF240_0020 y PCM_1_CLRINT W O Address 0xF250_0020 The PCM_n_CLRINT registe...

Page 1716: ... in a broadcasting studio environment the interface is primarily intended to carry monophonic or stereophonic programs at a 48 kHz sampling frequency and with a resolution of up to 24 bit per sample it may alternatively be used to carry one or two signals sampled at 32 kHz In both cases the clock references and auxiliary information are transmitted along with the program Provision is is made to al...

Page 1717: ...rator Block Makes 128fs sampling frequency clock used in out_spdif block from system audio clock MCLK Clock Multiplex Block System audio clock MCLK can be selected as internal MCLK or external MCLK Audio_if_core Block Acts as interface block between data buffer and out_spdif block Finite state machine controls the flow of PCM data spdif_tx Block Inserts burst preamble and executes zero stuffing in...

Page 1718: ...e M However the preamble is changed to preamble B once every 192 frame This unit composed of 192 frames defines the block structure used to organize the channel status information Sub frames of channel 2 right or B in stereophonic operation and secondary channel in monophonic operation always use preamble W In the single channel operation mode in broadcasting studio environment the frame format is...

Page 1719: ...mple bits If the source provides fewer bits than the interface allows 24 or 20 the unused least significant bits is set to a logical 0 By this procedure equipment using different numbers of bits is connected Time slot 28 carries the validity flag associated with the audio sample word This flag is set to logical 0 if the audio sample is reliable Time slot 29 carries one bit of the user data associa...

Page 1720: ...bitstream is transferred using the basic 16 bit data area of the IEC 60958 subframes i e in time slots 12 to 27 Each IEC 60958 frame transfers 32 bit of the non PCM data in consumer application mode If the SPDIF bitstream conveys linear PCM audio the symbol frequency is 64 times the PCM sampling frequency 32 time slots per PCM sample times two channels If a non linear PCM encoded audio bitstream i...

Page 1721: ...e module and inserted depending on subframe counter Channel status data are set in the SPDCSTAS register and used by one bit per frame User data always have zero values For non linear PCM data burst preamble which consists of Pa Pb Pc and Pd must be inserted before burst payload and zero is stuffed from the end of burst payload to the repetition count Pa 16 hF872 and Pb 16 h4E1F is fixed in the mo...

Page 1722: ...nd SPDCNT register because previous information is copied to their respective shadowed registers 4 Set next stream information to SPDBSTAS and SPDCNT register 5 Wait for stream end interrupt which signals the end of the first stream 6 With stream end interrupt the 2nd stream data starts to go out Sets 3rd stream information to registers The usage of user bit registers is similar to that of stream ...

Page 1723: ...MC In order to use these pads for SPDIF GPIO must be set before the SPDIF started For mode information refer to the Chapter GPIO Funtion Signal I O Description Pad Type SPDIF_EXTCLK Input Global Audio Main Clock External MCLK Xi2c1SCL or Xmmc2CDn muxed SPDIF_OUT Output SPDIFOUT Data Output Xi2c1SDA or Xmmc2DATA 3 muxed ...

Page 1724: ...000 SPDCNT 0XF260_0014 R W Repetition Count Register 0x0000_0000 SPDBSTAS_SHD 0XF260_0018 R Shadowed Burst Status Register 0x0000_0000 SPDCNT_SHD 0XF260_001C R Shadowed Repetition Count Register 0x0000_0000 USERBIT1 0XF260_0020 R W Subcode Q1 Q32 0x0000_0000 USERBIT2 0XF260_0024 R W Subcode Q33 Q64 0x0000_0000 USERBIT3 0XF260_0028 R W Subcode Q65 Q96 0x0000_0000 USERBIT1_SHD 0XF260_002C R Shadowed...

Page 1725: ...4 SPDCON Bit Description Reset Value Reserved 31 26 Reserved 0 FIFO Level 25 22 FIFO Level Monitoring Read Only FIFO depth is 8 0 Empty of FIFO Level 8 Full of FIFO Level 0000 FIFO Level Threshold 21 19 FIFO Threshold Level is controllable 000 0 FIFO Level 001 1 FIFO Level 010 2 FIFO Level 011 3 FIFO Level 100 4 FIFO Level 101 5 FIFO Level 110 6 FIFO Level 111 7 FIFO Level 000 FIFO transfer mode 1...

Page 1726: ...out in PCM data s 23th bit 0 User Data Interrupt Status 11 Read Operation 0 No interrupt pending 1 Interrupt pending when 96bit of user data is out Write Operation 0 No effect 1 Clear this flag 0 User Data Interrupt Enable 10 0 Interrupt masked 1 Interrupt enable 0 Buffer Empty Interrupt Status 9 Read Operation 0 No interrupt pending 1 Interrupt pending Write Operation 0 No effect 1 Clear this fla...

Page 1727: ... Address 0XF260_0008 SPDBSTAS Bit Description Reset Value Burst data length bit 31 16 ES size in bits Burst Preamble Pd ES size Elementary Stream size This indicates Burst payload length 0 Bitstream number 15 13 Bit_stream_number shall be set to 0 0 Data type dependent info 12 8 Data type dependent information 0 Error flag 7 0 Error flag indicating a valid burst_payload 1 Error flag indicating tha...

Page 1728: ...n status of the material 0 Channel status mode 7 6 00 Mode 0 Others Reserved 0 Emphasis 5 3 If bit1 0 000 2 audio channels without pre emphasis 001 2 audio channels with 50us 15us pre emphasis If bit1 1 000 Default State 0 Copyright assertion 2 0 Copyright 1 No copyright 0 Audio sample word 1 0 Linear PCM 1 Non linear PCM 0 Channel status block 0 0 Consumer format 1 Professional format 0 6 2 5 SPD...

Page 1729: ...ror Flag 7 0 Error flag indicating a valid burst_payload 1 Error flag indicating that the burst payload may contain errors 0 Reserved 6 5 Reserved 0 Compressed Data Type 4 0 00000 Null Data 00001 AC 3 00010 Reserved 00011 Pause 00100 MPEG1 layer1 00101 MPEG1 layer2 3 MPEG2 bc 00110 MPEG2 extension 00111 Reserved 01000 MPEG2 layer1 lsf 01001 MPEG2 layer2 layer3 lsf Others Reserved 0 6 2 8 Shadowed ...

Page 1730: ...ken out in a row 0 6 2 10 Shadowed User Data Register Shadowed Register Userbit1 USERBIT1_SHD R Address 0XF260_002C Shadowed Register Userbit2 USERBIT2_SHD R Address 0XF260_0030 Shadowed Register Userbit3 USERBIT3_SHD R Address 0XF260_0034 USERBIT_SHD Bit Description Reset Value User Data Bit 31 0 USERBIT1_SHD Q1 Q32 USERBIT2_SHD Q33 Q64 USERBIT3_SHD Q65 Q96 User Data Bit has the Digital Audio Tra...

Page 1731: ...SPDIF TRANSMITTER S5PC100 USER S MANUAL REV1 0 10 6 16 NOTES ...

Page 1732: ...own mode is supported Touch Screen Interface controls input pads XP XM YP and YM to obtain X Y position on the external touch screen device Touch Screen Interface contains three main block these are touch screen pads control logic ADC interface logic and interrupt generation logic 2 FEATURES The ADC Touch Screen interface includes the following features Resolution 10 bit 12 bit optional Differenti...

Page 1733: ...erter ADC interface Touch screen control ADC input control Interrupt generation INT_ADC INT_PNDNUP Waiting for interrupt VDDA_ADC VDDA_ADC AIN9 XP AIN8 XM AIN7 YP AIN6 YM AIN 5 0 VDDA_ADC Figure 10 7 1 ADC and Touch Screen Interface Functional Block Diagram NOTE If Touch Screen device is used XM or YM is only connected to ground for Touch Screen I F If Touch Screen device is not used XM or YM conn...

Page 1734: ...ch is automatically on and ADC channel selection bits are automatically changed to 5 The end of X position conversion can be notified by interrupt INT_ADC Y position measurement state is operated as the following way set XY_PST is 2 and read out the converted data Y position from ADCDAT1 When XY_PST is 2 YP and YM switch is automatically on and ADC channel selection bits are automatically changed ...

Page 1735: ...3 PULL_UP is 0 XP_SEN is 1 XM_SEN is 0 YP_SEN is 1 and YM_SEN is 1 After touch screen controller generates interrupt signal INT_PNDNUP waiting for interrupt Mode must be cleared XY_PST sets to the No operation Mode Mode XP XM YP YM Waiting for Interrupt Mode VDDA_ADC Pull up enable Hi z Hi z VSSA_ADC 5 Standby Mode Set ADCCON 2 to 1 to activate Standby mode In this mode A D conversion operation ha...

Page 1736: ...polling method by checking the ADCCON 15 end of conversion flag bit the read time from ADCDAT register can be determined A D conversion can be activated in different way After ADCCON 1 A D conversion start by read mode is set to 1 A D conversion starts simultaneously when converted data is read Figure 10 7 2 ADC and Touch Screen Operation Signal If pen down up interrupt is used as an wakeup source...

Page 1737: ...og AIN 6 Input ADC Channel 6 Analog Input XadcAIN 6 Analog AIN 5 Input ADC Channel 5 Analog Input XadcAIN 5 Analog AIN 4 Input ADC Channel 4 Analog Input XadcAIN 4 Analog AIN 3 Input ADC Channel 3 Analog Input XadcAIN 3 Analog AIN 2 Input ADC Channel 2 Analog Input XadcAIN 2 Analog AIN 1 Input ADC Channel 1 Analog Input XadcAIN 1 Analog AIN 0 Input ADC Channel 0 Analog Input XadcAIN 0 Analog ADC_V...

Page 1738: ...ol Register 0x0000_0058 ADCDLY 0xF300_0008 R W ADC Start or Interval Delay Register 0x0000_00FF ADCDAT0 0xF300_000C R ADC Conversion Data Register ADCDAT1 0xF300_0010 R ADC Conversion Data Register ADCUPDN 0xF300_0014 R W Stylus Up or Down Interrupt Register 0x0000_0000 ADCCLRINT 0xF300_0018 W Clear ADC Interrupt ADCMUX 0xF300_001C R W Analog input channel selection 0x0000_0000 ADCCLRINTPNDNUP 0xF...

Page 1739: ...lue Data value 5 255 Note that division factor is N 1 if the prescaler value is N NOTE ADC frequency should be set less than PCLK by 5 times Ex If PCLK 10MHz ADC Frequency 2MHz This A D converter is designed to operate at maximum 5MHz clock 0xFF Reserved 5 3 Reserved 0 STDBM 2 Standby mode select 0 Normal operation mode 1 Standby mode 1 READ_ START 1 A D conversion start by read 0 Disables start b...

Page 1740: ...ull up Switch Enable 0 Enables XP Pull up 1 Disables XP Pull up 1 AUTO_PST 2 Automatic sequencing conversion of X Position and Y Position 0 Normal ADC conversion 1 Auto Sequential measurement of X position and Y position 0 XY_PST 1 0 Manually measurement of X Position or Y Position 00 No operation mode 01 X position measurement 10 Y position measurement 11 Waiting for Interrupt Mode 0 NOTES 1 Whil...

Page 1741: ...3 In case of IDLE or STOP mode If stylus down occurs in IDLE or STOP mode Wake Up signal is generated after counting the value of DELAY bits Counting clock can be system clock or RTC clock by the value of FLKCLKsrc bit Wake up Interrupt generation delay value Before entering STOP mode set FLKCLKsrc bit to only 1 b1 to use RTC clock 8 5 ADC CONVERSION DATA REGISTER ADCDAT0 R ADDRESS 0XF300_000C ADC...

Page 1742: ...a value 0x0 0xFFF 8 7 ADC TOUCH SCREEN UP DOWN REGISTER ADCUPDN R W ADDRESS 0XF300_0014 ADCUPDN Bit Description Reset Value TSC_UP 1 Stylus Up Interrupt history After check this bit should be cleared manually 0 No stylus up state 1 Stylus up interrupt has occurred 0 TSC_DN 0 Stylus Down Interrupt history After check this bit should be cleared manually 0 No stylus down state 1 Stylus down interrupt...

Page 1743: ...IN 0 0001 AIN 1 0010 AIN 2 0011 AIN 3 0100 AIN 4 0101 AIN 5 0110 YM 0111 YP 1000 XM 1001 XP 0 NOTE SEL_MUX is invalid when TSADC is set as 1 Separate X Y position conversion Mode or 2 Auto Sequential X Y Position Conversion Mode 8 10 ADC TOUCH SCREEN PEN DOWN UP INTERRUPT CLEAR REGISTER ADCCLRINTPNDNUP W ADDRESS 0XF300_0020 ADCCLRINTPNDNUP Bit Description Reset Value INTPNDNUPCLR 0 INT_PNDNUP inte...

Page 1744: ...S5PC100 USER S MANUAL REV1 0 ADC AND TOUCH SCREEN INTERFACE 10 7 13 NOTES ...

Page 1745: ...r key release are detected to the CPU by an interrupt If interrupt occurs from row lines the software must scan the column lines using the proper procedure to detect one or multiple key press or release It provides interrupt status register bits at the moment of key pressed or key released or both cases If two interrupt conditions are enabled To prevent the switching noises internal debouncing fil...

Page 1746: ...or USB_XTI Filter width Filter width Filter width Figure 10 8 2 Internal Debouncing Filter Operation 3 FILTER CLOCK KEYPAD interface debouncing filter clock FCLK is divided from FLT_CLK that is OSC_IN You can set compare value for 10 bit up counter KEYIFFC If filter enable bit FC_EN is HIGH filter clock divider is ON The frequency of FCLK is frequency of FLT_CLK KEYIFFC 1 x 2 On the contrary FC_EN...

Page 1747: ...the others to the KEYIFCOL register Each write time the CPU reads the value of the KEYIFROW register and detects if one key of the corresponding column line is pressed When the scanning procedure is end the pressed key one or more can be detected S5PC100X SCAN_X 7 0 SCAN_Y 7 0 0 1 2 3 4 8 9 10 11 12 16 17 18 19 20 24 25 26 27 28 32 33 34 35 36 5 13 21 29 37 40 41 42 43 44 45 48 49 50 51 52 53 56 5...

Page 1748: ...S5PC100 USER S MANUAL REV1 0 10 8 4 Figure 10 8 4 Keypad Scanning Procedure II Figure 10 8 5 Keypad Scanning Procedure III NOTE Delay time is needed between setting a column data register and reading a row data register ...

Page 1749: ... key is detected row column 2nd Row Key pressed state 1st Row Key interrupt set to Released key state 2nd Row Key interrupt S W in ISR pressed key is detected S W detect when the 1st Row Key pressed state 2nd Row Key Interrupt set to Released key state 1st Row Key pressed state Pressed Key filtered view 1st Row Key 2nd Row Key Figure 10 8 6 Keypad Scanning Procedure when the Two Key Pressed with D...

Page 1750: ...KEYPAD INTERFACE S5PC100 USER S MANUAL REV1 0 10 8 6 Figure 10 8 7 Keypad I F Block Diagram ...

Page 1751: ... Column 5 Data XEINT 21 Muxed KP_COL 4 Output KEYPAD Interface Column 4 Data XEINT 20 Muxed KP_COL 3 Output KEYPAD Interface Column 3 Data XEINT 19 Muxed KP_COL 2 Output KEYPAD Interface Column 2 Data XEINT 18 Muxed KP_COL 1 Output KEYPAD Interface Column 1 Data XEINT 17 Muxed KP_COL 0 Output KEYPAD Interface Column 0 Data XEINT 16 Muxed NOTE Type field indicates whether pads are dedicated to the ...

Page 1752: ...AD wakeup source 0 FC_EN 3 10 bit counter for Debouncing digital filter clock enable 0 Disables Division counter is not used FCLK FLT_CLK 1 Enables Use division counter FCLK FLT_CLK KEYIFFC 9 0 1 x 2 0 DF_EN 2 KEYPAD input port debouncing filter enable 0 Disables 1 Enables 0 INT_R_EN 1 KEYPAD input port rising edge key released interrupt 0 Disables 1 Enables 0 INT_F_EN 0 KEYPAD input port falling ...

Page 1753: ...e Write 1 to clear Pressed interrupt The P_INT 7 0 indicate that each key released from 0 to 7 has a dedicated interrupt to it from P_INT 0 to P_INT 7 0x00 NOTE Keypad wakeup interrupt is cleared if the write access to the KEYIFSTSCLR 7 3 KEYPAD INTERFACE COLUMN DATA OUTPUT REGISTER KEYIFCOL R W ADDRESS 0XF310_0008 KEYIFCOL Bit Description Reset Value Reserved 31 8 Reserved 0x0000FF KEYIFCOL 7 0 K...

Page 1754: ...R W ADDRESS 0XF310_0010 KEYIFFC Bit Description Reset Value Reserved 31 10 Reserved 0x000000 KEYIFFC 9 0 KEYPAD interface debouncing filter clock division register User can set compare value for 10 bit up counter This register value means when FC_EN bit is HIGH FCLK FLT_CLK KEYIFFC 9 0 1 x 2 FLT_CLK is OSC_IN or USB_XI 0x000 ...

Page 1755: ...S5PC100 USER S MANUAL REV1 0 KEYPAD INTERFACE 10 8 11 NOTES ...

Page 1756: ...G key has value is also provided S5PC100 provides not only TrustZone HW access control as previsous Samsung AP such as S5PC64xx it also provide Samsung s own secure access control solution which uses TrustZone HW Samsung s own solution named Mobile Device Security Platform MDSP is composed of Secure Domain Manager SDM HW module and its secure SW solution 128 bit e fuse ROM is also provided as root...

Page 1757: ...ROM for secure boot key hash value Secure JTAG Samsung s own multi level Hardware H W authentication module 80 bit e fuse ROM for secure JTAG key hash value Secure Access Control Using TrustZone H W access control scheme Provide Mobile Device Security Platform MDSP Samsung s own secure domain managing solution 128 bit e fuse ROM for root key Security Engines DES TDES AES SHA 1 PRNG and PKA ...

Page 1758: ...d the secure domain is also introduced as shown in Figure 11 2 1 Generally all applications are running as user mode in normal domain If one of the applications needs security function it calls secure function in previliged mode If that function is successfully authenticated working domain is changed to secure domain and the secure function is progressed in secure domain After secure function is c...

Page 1759: ...ogram execution environment The purpose of switching over the special domain for secure program is to protect the secure resources of system from normal program that may have threat codes by permitting only secure program to access secure resources Secure Domain State from secure boot state and DMZ entrance to end of the secure programs and all slave memory areas are accessible Non Secure Domain A...

Page 1760: ...rom ARM Home page www arm com 2 SDM FUNCTIONAL DESCRIPTION SDM is the main block of domain isolation Hardware scheme in S5PC100 It provides the secure access control function by replacing CPU s AxPROT 1 with own access control signal Therefore it does not need TZ Software Figure 11 2 3 shows system level block diagram of SDM SDM controls its own secure domain on bit by observing cortexA8 s bus sig...

Page 1761: ...SECURE DOMAIN MANAGER S5PC100 USER S MANUAL REV1 0 11 2 4 SM Decoder ARM Decoder NM Decoder Figure 11 2 3 System Level Block Diagram of SDM ...

Page 1762: ...10_0008 R SDM Status Register 0x0000_0080 SDM_FIQ2SBITON_DLY 0xF510_000C R W SDM FIQ On to SBIT On Interval Delay Cycle Count Register 0x0000_0000 SDM_IMZOFF2DMZ_ DLY 0xF510_0010 R W SDM IMZ OFF to DMZ Entrance Interval Delay Cycle Count Register 0x0000_0000 SDM_RANDOM_BR_ADDR 0xF510_0014 R W SDM DMZ Entrance Mode 2 NC PA Random Branch Start Address Register 0x0000_0000 SDM_RANDOM_BR_CNT 0xF510_00...

Page 1763: ... 3rd Instruction Register 0x0000_0000 INITSCODE0_3 0xF510_0044 R W DMZ Configurable Initial Secure Code 0 Area 4th Instruction Register 0x0000_0000 INITSCODE0_4 0xF510_0048 R W DMZ Configurable Initial Secure Code 0 Area 5th Instruction Register 0x0000_0000 INITSCODE0_5 0xF510_004C R W DMZ Configurable Initial Secure Code 0 Area 6th Instruction Register 0x0000_0000 INITSCODE0_6 0xF510_0050 R W DMZ...

Page 1764: ...igurable Initial Secure Code 0 Area 24th Instruction Register 0x0000_0000 INITSCODE0_24 0xF510_0098 R W DMZ Configurable Initial Secure Code 0 Area 25th Instruction Register 0x0000_0000 INITSCODE0_25 0xF510_009C R W DMZ Configurable Initial Secure Code 0 Area 26th Instruction Register 0x0000_0000 INITSCODE0_26 0xF510_00A0 R W DMZ Configurable Initial Secure Code 0 Area 27th Instruction Register 0x...

Page 1765: ...000 INITSCODE1_1 0xF510_00D4 R W DMZ Configurable Initial Secure Code 1 Area 2nd Instruction Register 0x0000_0000 INITSCODE1_2 0xF510_00D8 R W DMZ Configurable Initial Secure Code 1 Area 3rd Instruction Register 0x0000_0000 INITSCODE1_3 0xF510_00DC R W DMZ Configurable Initial Secure Code 1 Area 4th Instruction Register 0x0000_0000 INITSCODE1_4 0xF510_00E0 R W DMZ Configurable Initial Secure Code ...

Page 1766: ...DMZ Entrance Mode 2 Fail Handling Select Bit 0 Fail Not Violation 1 Fail Violation 1 b0 SCodeOnlyExecution 5 Secure Domain Secure Code Only Execution Select Bit 0 Normal Secure Code Execution 1 Secure Code Only Execution 1 b0 NCodeViolaMode 8 6 Normal Code State Violation Mode Select Bit 3 b001 IRQ 3 b010 FIQ 3 b100 System Reset 1 b0 NCPABrViolaMode 11 9 NC PA Random Branch State Violation Handlin...

Page 1767: ...us Bit 1 b0 NCPABrFailCase4 5 NC PA Random Branch Fail Case 4 Status Bit 1 b0 SCodeViolaDetect 6 Secure Code Violation Detect Status Bit 1 b0 SDMSecureDomainOn 7 Secure Domain On Status Bit 1 b1 Reserved 31 8 Reserved 25 h0 3 4 SDM FIQ ON TO SBIT ON INTERVAL DELAY CYCLE COUNT REGISTER SDM_FIQ2SBITON_DLY R W ADDRESS 0XF510_000C SDM_FIQ2SBITON_DLY Bit Description Reset Value Fiq2SBitOnDly 15 0 FIQ O...

Page 1768: ...S5PC100 USER S MANUAL REV1 0 SECURE DOMAIN MANAGER 11 2 11 RandomBrAddr 31 0 DMZ Entrance Mode 2 NC PA Random Branch Start Address Bit 32 h0 ...

Page 1769: ...t 30 h0 Reserved 31 30 2 b0 3 9 SDM DMZ ENTRANCE ADDRESS REGISTER SDM_DMZ_ENTR_ADDR R W ADDRESS 0XF510_0020 SDM_DMZ_ENTR_ADDR Bit Description Reset Value DmzEntrAddr 31 0 DMZ Entrance Address Bit 32 h0 3 10 SDM DMZ EXIT ADDRESS REGISTER SDM_DMZ_EXIT_ADDR R W ADDRESS 0XF510_0024 SDM_DMZ_EXIT_ADDR Bit Description Reset Value DmzExitAddr 31 0 DMZ Exit Address Bit 32 h0 3 11 SDM SECURE CODE ENTRANCE A...

Page 1770: ...it Description Reset Value InitScode0_0 31 0 DMZ Configurable Initial Secure Code 0 Area 1st Instruction Bit 32 h0 3 16 DMZ CONFIGURABLE INITIAL SECURE CODE 0 AREA 2ND INSTRUCTION REGISTER INITSCODE0_1 R W ADDRESS 0XF510_003C INITSCODE0_1 Bit Description Reset Value InitScode0_1 31 0 DMZ Configurable Initial Secure Code 0 Area 2nd Instruction Bit 32 h0 3 17 DMZ CONFIGURABLE INITIAL SECURE CODE 0 A...

Page 1771: ... INITSCODE0_6 Bit Description Reset Value InitScode0_6 31 0 DMZ Configurable Initial Secure Code 0 Area 7th Instruction Bit 32 h0 3 22 DMZ CONFIGURABLE INITIAL SECURE CODE 0 AREA 8TH INSTRUCTION REGISTER INITSCODE0_7 R W ADDRESS 0XF510_0054 INITSCODE0_7 Bit Description Reset Value InitScode0_7 31 0 DMZ Configurable Initial Secure Code 0 Area 8th Instruction Bit 32 h0 3 23 DMZ CONFIGURABLE INITIAL ...

Page 1772: ...NITSCODE0_12 Bit Description Reset Value InitScode0_12 31 0 DMZ Configurable Initial Secure Code 0 Area 13th Instruction Bit 32 h0 3 28 DMZ CONFIGURABLE INITIAL SECURE CODE 0 AREA 14TH INSTRUCTION REGISTER INITSCODE0_13 R W ADDRESS 0XF510_006C INITSCODE0_13 Bit Description Reset Value InitScode0_13 31 0 DMZ Configurable Initial Secure Code 0 Area 14th Instruction Bit 32 h0 3 29 DMZ CONFIGURABLE IN...

Page 1773: ...NITSCODE0_18 Bit Description Reset Value InitScode0_18 31 0 DMZ Configurable Initial Secure Code 0 Area 19th Instruction Bit 32 h0 3 34 DMZ CONFIGURABLE INITIAL SECURE CODE 0 AREA 20TH INSTRUCTION REGISTER INITSCODE0_19 R W ADDRESS 0XF510_0084 INITSCODE0_19 Bit Description Reset Value InitScode0_19 31 0 DMZ Configurable Initial Secure Code 0 Area 20th Instruction Bit 32 h0 3 35 DMZ CONFIGURABLE IN...

Page 1774: ...NITSCODE0_24 Bit Description Reset Value InitScode0_24 31 0 DMZ Configurable Initial Secure Code 0 Area 25th Instruction Bit 32 h0 3 40 DMZ CONFIGURABLE INITIAL SECURE CODE 0 AREA 26TH INSTRUCTION REGISTER INITSCODE0_25 R W ADDRESS 0XF510_009C INITSCODE0_25 Bit Description Reset Value InitScode0_25 31 0 DMZ Configurable Initial Secure Code 0 Area 26th Instruction Bit 32 h0 3 41 DMZ CONFIGURABLE IN...

Page 1775: ...DRESS REGISTER INITSCODE1ADDR0 R W ADDRESS 0XF510_00B0 INITSCODE1ADDR0 Bit Description Reset Value InitScode1Addr0 19 0 DMZ Configurable Initial Secure Code 1 Area 1st Instruction Address Bit 20 h0 Reserved 31 20 Reserved 12 h0 3 46 DMZ CONFIGURABLE INITIAL SECURE CODE 1 AREA 2ND INSTRUCTION ADDRESS REGISTER INITSCODE1ADDR1 R W ADDRESS 0XF510_00B4 INITSCODE1ADDR1 Bit Description Reset Value InitSc...

Page 1776: ...ABLE INITIAL SECURE CODE 1 AREA 6TH INSTRUCTION ADDRESS REGISTER INITSCODE1ADDR5 R W ADDRESS 0XF510_00C4 INITSCODE1ADDR5 Bit Description Reset Value InitScode1Addr5 19 0 DMZ Configurable Initial Secure Code 1 Area 6th Instruction Address Bit 20 h0 Reserved 31 20 Reserved 12 h0 3 51 DMZ CONFIGURABLE INITIAL SECURE CODE 1 AREA 7TH INSTRUCTION ADDRESS REGISTER INITSCODE1ADDR6 R W ADDRESS 0XF510_00C8 ...

Page 1777: ...8 INITSCODE1_2 Bit Description Reset Value InitScode1_2 31 0 DMZ Configurable Initial Secure Code 1 Area 3rd Instruction Bit 32 h0 3 56 DMZ CONFIGURABLE INITIAL SECURE CODE 1 AREA 4TH INSTRUCTION REGISTER INITSCODE1_3 R W ADDRESS 0XF510_00DC INITSCODE1_3 Bit Description Reset Value InitScode1_3 31 0 DMZ Configurable Initial Secure Code 1 Area 4th Instruction Bit 32 h0 3 57 DMZ CONFIGURABLE INITIAL...

Page 1778: ...eset Value InitScode1_6 31 0 DMZ Configurable Initial Secure Code 1 Area 7th Instruction Bit 32 h0 3 60 DMZ CONFIGURABLE INITIAL SECURE CODE 1 AREA 8TH INSTRUCTION REGISTER INITSCODE1_7 R W ADDRESS 0XF510_00EC INITSCODE1_7 Bit Description Reset Value InitScode1_7 31 0 DMZ Configurable Initial Secure Code 1 Area 8th Instruction Bit 32 h0 NOTE All SDM SFR Write is protected after Secure Boot Operati...

Page 1779: ...SECURE DOMAIN MANAGER S5PC100 USER S MANUAL REV1 0 11 2 22 NOTES ...

Page 1780: ...with dedicated 2KB memory for large number modular multiplication up to 2048 bit modulus This modular multiplier is used for implementing public key cryptographic functions like RSA Additionally ACE has a secure JTAG controller This controller applies the authentication mechanism to check the authorized user and the access mode The system protects the system access from the unauthorized user throu...

Page 1781: ...served areas The base address of each area is determined by the host and you can customize according to your requirement The four areas are AHB Rx area Memory space and SFRs connected to AHB Rx bus incl FIFO Rx AHB Tx area Memory space and SFRs connected to AHB Tx bus incl FIFO Tx DMA Rx area Memory space and SFRs in FIFO Rx DMA Tx area Memory space and SFRs in FIFO Tx Figure 11 3 2 ACE Area Memor...

Page 1782: ...SFRs output buffer DES 3DES SFRs output buffer AES SFRs output buffer Reserved FIFO Tx Reserved Reserved 0x0000_0000 0x0001_0000 0x0004_0000 0x0005_0000 0x0006_0000 0x0007_0000 0x000F_FFFF 0x0002_0000 0x0002_0000 0x0009_0000 AHB Tx Area FIFO Rx Reserved 0x0000_0000 0x0001_0000 0x000F_FFFF DMA Rx Area FIFO Tx Reserved 0x0000_0000 0x0001_0000 0x000F_FFFF DMA Tx Area Figure 11 3 3 ACE Internal Memory...

Page 1783: ...Mode ECB CBC and CTR Mode Key Length 128 bit 192 bit and 256 bit Support On the fly Key Scheduler Througput 931Mbps 80MHz Key 128 bit 788Mbps 80MHz Key 192 bit 683 80MHz Key 256 bit 2 2 TDES DES DATA ENCRYPTION STANDARD ENGINE ACE TDES is one of the symmetric encryption modules and operates in 64 bit key DES mode and 64 bit key Triple DES mode It supports ECB CBC operation mode TDES engine s featu...

Page 1784: ...ecided by the e fuse ROM Secure Access Type bit Set this bit to 0 to debug the all region include secure part Table 11 3 1 Secure JTAG Debug Mode Selection Secure Access Type Secure JTAG Lock on Debug Mode 1 0 Non secure non protection mode 0 0 Secure non protection mode 1 1 Non secure soft lock mode 0 1 Secure soft lock mode It receives the password sequences through AHB bus from debugger and aut...

Page 1785: ...66MHz ARM AXI_C0 32b 2x7 166MHz 0 0 0 1 1 1 1 5 CSSYS AHB AP 6 JTAG detector Authentication path DBGEN NIDEN SPIDEN SPNIDEN DBGEN NIDEN SPIDEN SPNIDEN Access controller SecAccessEn NSecAccessEn SMode JTAGDetect DBGEN 1 NIDEN 1 SPIDEN 1 SPNIDEN 1 Memory sub system Figure 11 3 4 Secure JTAG System in S5PC100 ...

Page 1786: ...x FIFO Write Data to Rx FIFO Polls Tx FIFO Transfer Done Read Data from Tx FIFO 3 3 DMA MODE Sets Control Registers of crypto engine Sets DMA and Interrupt control register of the ACE Sets Control Register of Rx Tx FIFO Start Rx Tx FIFO Write Data to Memory DMA Rx Channel Start Write Data to Rx FIFO DMA Tx Channel Start Read Data from Tx FIFO Polls Tx DMA Operation Done Polls Tx FIFO Transfer Done...

Page 1787: ...O DMA Request of 3 4 CHANGE FROM FIFO MODE TO DMA MODE stepd Main TxClearReq 1 void TxClearReq unsigned int channel const unsigned int SECSS_PERI_NUM 1 static unsigned int flush_code channel 0x00000007 flush_code 0xff000035 SECSS_PERI_NUM 11 DMA_DBGINST0 0x00a00000 channel 24 DMA_DBGINST1 unsigned int flush_code DMA_DMBCMD 0x0 ...

Page 1788: ...0420_0000 FRx_MLen 0xF401_0004 R W FIFO Rx Message Length Register 0x0000_0000 FRx_BlkSz 0xF401_0008 R W FIFO Rx Crypto Algorithm Block Size Register 0x0000_0000 FRx_DestAddr 0xF401_000C R W FIFO Rx Inout Buffer Address Register 0x0000_0000 FRx_MLenCnt 0xF401_0010 R W FIFO Rx Message Count Register Number of words left 0x0000_0000 FRx_WrBuf 0xF401_0040 0xF401_0080 W FIFO Rx write buffer 32x32 bit ...

Page 1789: ...lgorithm Block Size Register 0x0000_0000 FTx_SrcAddr 0xF411_000C R W FIFO Tx Output Buffer Address Register 0x0000_0000 FTx_MLenCnt 0xF411_0010 R W FIFO Tx Message Count Register Number of words left 0x0000_0000 FTx_RdBuf 0xF411_0040 0xF411_0080 R FIFO Tx read buffer 32x32 bit 0x0000_0000 NOTE Read access to FTx_WrBuf makes FIFO Tx to read data from the FIFO memory regardless of the address given ...

Page 1790: ...r 04 0x0000_0000 AES_Rx_KEY_05 0xF404_0090 R W AES Rx Key Input Register 05 0x0000_0000 AES_Rx_KEY_06 0xF404_0094 R W AES Rx Key Input Register 06 0x0000_0000 AES_Rx_KEY_07 0xF404_0098 R W AES Rx Key Input Register 07 0x0000_0000 AES_Rx_KEY_08 0xF404_009C R W AES Rx Key Input Register 08 0x0000_0000 AES_Rx_IV_01 0xF404_00A0 R W AES Rx IV Input Register 01 0x0000_0000 AES_Rx_IV_02 0xF404_00A4 R W A...

Page 1791: ...ster 3_0 0x0000_0000 TDES_Rx_KEY3_1 0xF405_0024 R W DES TDES Rx Key Input Register 3_1 0x0000_0000 TDES_Rx_INPUT_0 0xF405_0040 R W DES TDES Rx Data Input Register 0 0x0000_0000 TDES_Rx_INPUT_1 0xF405_0044 R W DES TDES Rx Data Input Register 1 0x0000_0000 TDES_Rx_OUTPUT_0 0xF405_0048 R DES TDES Rx Output Data Register 0 0x0000_0000 TDES_Rx_OUTPUT_1 0xF405_004C R DES TDES Rx Output Data Register 1 0...

Page 1792: ... 1 b1 0x0000_0000 SEED_DATA_07 0xF406_0020 W PRNG Seed data 223 192 If HASH_CONTROL 5 1 b1 0x0000_0000 SEED_DATA_08 0xF406_0024 W PRNG Seed data 255 224 If HASH_CONTROL 5 1 b1 0x0000_0000 SEED_DATA_09 0xF406_0028 W PRNG Seed data 287 256 If HASH_CONTROL 5 1 b1 0x0000_0000 SEED_DATA_10 0xF406_002C W PRNG Seed data 319 288 If HASH_CONTROL 5 1 b1 0x0000_0000 HASH_STATUS 0xF406_0030 R Status check 0x0...

Page 1793: ...68 R HASH_MIDOUT 63 32 0x0000_0000 HASH_MIDOUT_05 0xF406_006C R HASH_MIDOUT 31 0 0x0000_0000 HASH_IV_01 0xF406_0070 W HASH initial value 01 0x0000_0000 HASH_IV_02 0xF406_0074 W HASH initial value 02 0x0000_0000 HASH_IV_03 0xF406_0078 W HASH initial value 03 0x0000_0000 HASH_IV_04 0xF406_007C W HASH initial value 04 0x0000_0000 HASH_IV_05 0xF406_0080 W HASH initial value 05 0x0000_0000 PRE_MSG_LENG...

Page 1794: ...16_0048 R PRNG Output 0x0000_0000 PRNG_OUTPUT_07 0xF416_004C R PRNG Output 0x0000_0000 PRNG_OUTPUT_08 0xF416_0050 R PRNG Output 0x0000_0000 PRNG_OUTPUT_09 0xF416_0054 R PRNG Output 0x0000_0000 PRNG_OUTPUT_10 0xF416_0058 R PRNG Output 0x0000_0000 4 1 10 PKA Memory and SFRs AHB Rx Area Register Address R W Description Reset Value PKA_MEM 0xF407_0000 0xF407_07FF R W PKA Memory 2KB 0x0000_0000 PKA_SFR...

Page 1795: ...ister 0xxxxx_xxxx SJ_STATUS_REG 0xF408_0004 R Secure JTAG Status Register 0x0000_0000 SJ_RESULT_REG 0xF408_0008 R Secure JTAG Result Register 0x0000_0000 SJ_HEADER_INFO_ REG 0xF408_000C R Secure JTAG Header Information Register 0x0000_0000 SJ_PASSWORD_REG 0xF408_0020 R W Secure JTAG Password Register 0x0000_0000 SJ_PASSWORD_ CTRL_REG 0xF408_0024 W Secure JTAG Password Control Register 0x0000_0000 ...

Page 1796: ... read 1 b0 FRx_intr_Status 16 FIFO Rx interrupt status Resets to 0 if read 1 b0 Reserved 15 Reserved SHA_intr_En 14 SHA 1 PRNG interrupt enabled 1 b0 DES_intr_En 13 DES TDES interrupt enabled 1 b0 AES_intr_En 12 AES interrupt enabled 1 b0 Reserved 11 10 Reserved FTx_intr_En 9 FIFO Tx interrupt enabled 1 b0 FRx_intr_En 8 FIFO Rx interrupt enabled 1 b0 Reserved 7 Reserved TxTrgLevel 6 5 Tx side DMA ...

Page 1797: ...GINE BLOCK S5PC100 USER S MANUAL REV1 0 11 3 18 4 When users change SECSS operation mode from FiFo mode to DMA mode the first SECSS Tx FiFo DMA request must be cleared by executing DMA ACK instruction DMAFLUSHP ...

Page 1798: ...y Sets to 1 if FRx_Start bit resets to 0 Resets to 0 on FRx_Reset 1 Read only 1 b0 FRx_Wd2Write 23 16 Number of words that is written to FIFO memory FRx_WrBuf Resets to 0 on FRx_Reset 1 Read only 8 h20 FRx_Wd2Read 15 8 Number of words that is read from FIFO memory FRx_WrBuf Resets to 0 on FRx_Reset 1 Read only 8 h00 FRx_Dest_Module 7 6 Destination module selection 00 AES 01 DES TDES 10 SHA 1 PRNG ...

Page 1799: ...ister is set Read Write 2 b0 FRx_BlkSz 15 0 Block size of destination module in word 32 bit unit FIFO Rx transfers FRx_BlkSz word and then triggers the destination module to start processing The destination module is selected by FRx_Dest_Module field in FRx_Ctrl Resets to its reset value if FRx_Reset field of FRx_Ctrl register is set Read Write 16 b0 4 3 4 FIFO Rx Destination Address Register FRx_...

Page 1800: ...is empty Resets to 1 on FTx_Reset 1 Read only 1 b1 FTx_Done 25 Sets to 1 if FIFO Tx has finished transferring FTx_MLen words of data from the source Resets to 0 on FTx_Reset 1 or on read access to FTx_Ctrl register Read only 1 b0 FTx_Running 24 Sets to 1 if FIFO Tx is transferring data from the source or waiting for source output buffer is ready Sets to 1 when FTx_Start bit resets to 0 Resets to 0...

Page 1801: ...odule in word 32 bit unit FIFO Tx transfers FTx_BlkSz word and then triggers the destination module to start processing The destination module is selected by FTx_Dest_Module field in FTx_Ctrl Resets to its reset value if FTx_Reset field of FTx_Ctrl register is set Read Write 32 b0 4 3 10 FIFO Tx Source Address Register FTx_SrcAddr R W Address 0xF411_000C FTx_SrcAddr Bit Description Reset Value FTx...

Page 1802: ...ch occurs Read only Read Clear 1 b0 RdPrivMismatch 30 SFR Read Access Privilege Mismatch Status bit If set to 1 SFR Read Access Privilege Mismatchoccurs Read only Read Clear 1 b0 Reserved 29 11 Reserved 19 h0 AesOutReady 10 If set to 1 AES Output Buffer is Full and ARM or Rx FiFo is permitted to Read current 128bits result data Read only 1 b0 AesInReady 9 If set to 1 AES Input Buffer is Empty and ...

Page 1803: ...ES Data Input Register 02 AES_Rx_DIN_02 R W Address 0xF404_0014 AES_Rx_DIN_02 Bit Description Reset Value AesDin02 31 0 AES 2nd 32 bit Data Input Register 32 h0 4 4 4 AES Data Input Register 03 AES_Rx_DIN_03 R W Address 0xF404_0018 AES_Rx_DIN_03 Bit Description Reset Value AesDin03 31 0 AES 3rd 32bit Data Input Register 32 h0 4 4 5 AES Data Input Register 04 AES_Rx_DIN_04 R W Address 0xF404_001C A...

Page 1804: ...t02 31 0 AES 2nd 32 bit Data Output Register 32 h0 4 4 10 AES Data Output Register 03 AES_Rx_DOUT_03 R Address 0xF404_0028 AES_Rx_DOUT_03 Bit Description Reset Value AesDout03 31 0 AES 3rd 32 bit Data Output Register 32 h0 4 4 11 AES Data Output Register 03 AES_Tx_DOUT_03 R Address 0xF414_0028 AES_Tx_DOUT_03 Bit Description Reset Value AesDout03 31 0 AES 3rd 32 bit Data Output Register 32 h0 4 4 1...

Page 1805: ... AesKey03 31 0 AES 3rd 32 bit Key Input Register 32 h0 4 4 17 AES Key Input Register 04 AES_Rx_KEY_04 R W Address 0xF404_008c AES_Rx_KEY_04 Bit Description Reset Value AesKey04 31 0 AES 4th 32 bit Key Input Register 32 h0 4 4 18 AES Key Input Register 05 AES_Rx_KEY_05 R W Address 0xF404_0090 AES_Rx_KEY_05 Bit Description Reset Value AesKey05 31 0 AES 5th 32 bit Key Input Register 32 h0 4 4 19 AES ...

Page 1806: ... Input Register 32 h0 4 4 24 AES IV Input Register 03 AES_Rx_IV_03 R W Address 0xF404_00a8 AES_Rx_IV_03 Bit Description Reset Value AesIv03 31 0 AES 3rd 32 bit IV Input Register 32 h0 4 4 25 AES IV Input Register 04 AES_Rx_IV_04 R W Address 0xF404_00ac AES_Rx_IV_04 Bit Description Reset Value AesIv04 31 0 AES 4th 32 bit IV Input Register 32 h0 4 4 26 AES Counter Preload Input Register 01 AES_Rx_CT...

Page 1807: ...W Address 0xF404_00b8 AES_Rx_CTR_03 Bit Description Reset Value AesCtr03 31 0 AES 3rd 32 bit Counter Preload Input Register 32 h0 4 4 29 AES Counter Preload Input Register 04 AES_Rx_CTR_04 R W Address 0xF404_00bc AES_Rx_CTR_04 Bit Description Reset Value AesCtr04 31 0 AES 4th 32 bit Counter Preload Input Register 32 h0 ...

Page 1808: ... result data Read only 1 b0 TdesInReady 6 If set to 1 TDES Input Buffer is Empty and ARM or Rx FiFo is permitted to write next 128 bits data Read only 1 h1 DesOrTdes 5 DES or TDES Operation Selection Bit 0 DES Only Mode 1 TDES Mode Read Write 1 b0 TdesMode 4 3 TDES Mode Selection Bit 01 ECB Mode 10 CBC Mode Read Write 2 b00 TdesOpDirection 2 TDES Operation Direction Selection Bit 0 Encryption 1 De...

Page 1809: ...ion Reset Value TdesKey2_1 31 0 TDES 4th 32 bit Key Input Register 32 h0 4 5 6 TDES Key Input Register 3_0 TDES_Rx_KEY3_0 R W Address 0xF405_0020 TDES_Rx_KEY3_0 Bit Description Reset Value TdesKey3_0 31 0 TDES 5th 32 bit Key Input Register 32 h0 4 5 7 TDES Key Input Register 3_1 TDES_Rx_KEY3_1 R W Address 0xF405_0024 TDES_Rx_KEY3_1 Bit Description Reset Value TdesKey3_1 31 0 TDES 6th 32 bit Key In...

Page 1810: ...1 Most Significant TDES_Rx_OUTPUT_1 R Address 0xF405_004C TDES_Rx_OUTPUT_1 Bit Description Reset Value TdesDout1 31 0 TDES 2nd 32 bit Data Output Register 32 h0 4 5 13 TDES Data Output Register 1 Most Significant TDES_Tx_OUTPUT_1 R Address 0xF415_004C TDES_Tx_OUTPUT_1 Bit Description Reset Value TdesDout1 31 0 TDES 2nd 32 bit Data Output Register 32 h0 4 5 14 TDES IV Input Register 0 TDES_Rx_IV_0 ...

Page 1811: ...HA text byte 00 First byte LSB in 32 bit 01 Second byte 10 Third byte 11 Fourth byte full 32 bit Write Auto reset 2 b00 SEED_SETTING_ENABLE 5 Seed setting enable 1 b1 Read Write 1 b0 Hash_input_finished 4 Finished the hash input Cleared by hardware Write Auto reset 1 b0 Hash_start 3 Start the hash software reset Automatically cleared by hardware Write Auto reset 1 b0 Data_Selection 2 Indicates whe...

Page 1812: ... 0xF406_0010 SEED_DATA_03 Bit Description Reset Value SEED_DATA_03 31 0 PRNG seed data 95 64 HASH_CONTROL 5 1 b1 0x0000_0000 4 6 6 PRNG Seed Data 04 SEED_DATA_04 W Address 0xF406_0014 SEED_DATA_04 Bit Description Reset Value SEED_DATA_04 31 0 PRNG seed data 127 96 HASH_CONTROL 5 1 b1 0x0000_0000 4 6 7 PRNG Seed Data 05 SEED_DATA_05 W Address 0xF406_0018 SEED_DATA_05 Bit Description Reset Value SEE...

Page 1813: ...CONTROL 5 1 b1 0x0000_0000 4 6 13 Hash status HASH_STATUS R Address 0xF406_0030 HASH_STATUS Bit Description Reset Value Reserved 31 5 Reserved BUFFER_IN_ENABLE 4 1 Enables Buffer Input Buffer is empty 0 Buffer Input Not Enable Buffer is full Read 1 b1 HASH_engine_ready 3 Ready to receive next 64 bytes of input data Cleared by software after checking Read Reset on read 1 b0 Random_Number_Ready 2 Ra...

Page 1814: ...4 6 15 Hash Output 02 or PRNG Output 63 32 HASH_OUTPUT_02 PRNG_OUTPUT_02 R Address 0xF406_0038 HASH_OUTPUT_02 PRNG_OUTPUT_02 Bit Description Reset Value HASH_OUTPUT_02 31 0 PRNG_output 63 32 if Engine_selection 1 0 2 b10 Else Hash_output 63 32 0x0000_0000 4 6 16 Hash Output 03 or PRNG Output 95 64 HASH_OUTPUT_03 PRNG_OUTPUT_03 R Address 0xF406_003C HASH_OUTPUT_03 PRNG_OUTPUT_03 Bit Description Res...

Page 1815: ... 128 if Engine_selection 1 0 2 b10 Else Hash_output 159 128 0x0000_0000 4 6 19 PRNG_output 191 160 PRNG_OUTPUT_06 R Address 0xF406_0048 PRNG_OUTPUT_06 Bit Description Reset Value PRNG_OUTPUT_06 31 0 PRNG_output 191 160 0x0000_0000 4 6 20 PRNG_output 223 192 PRNG_OUTPUT_07 R Address 0xF406_004c PRNG_OUTPUT_07 Bit Description Reset Value PRNG_OUTPUT_07 31 0 PRNG_output 223 192 0x0000_0000 4 6 21 PRN...

Page 1816: ...6 26 HASH_MIDOUT 95 64 HASH_MIDOUT_03 R Address 0xF406_0064 HASH_MIDOUT_03 Bit Description Reset Value HASH_MIDOUT_03 31 0 HASH_MIDOUT 95 64 0x0000_0000 4 6 27 HASH_MIDOUT 63 32 HASH_MIDOUT_04 R Address 0xF406_0068 HASH_MIDOUT_04 Bit Description Reset Value HASH_MIDOUT_04 31 0 HASH_MIDOUT 63 32 0x0000_0000 4 6 28 HASH_MIDOUT 31 0 HASH_MIDOUT_05 R Address 0xF406_006c HASH_MIDOUT_05 Bit Description ...

Page 1817: ... 0 HASH_IV 63 32 0x0000_0000 4 6 33 HASH_IV 31 0 HASH_IV_05 W Address 0xF406_0080 HASH_IV_05 Bit Description Reset Value HASH_IV_05 31 0 HASH_IV 31 0 0x0000_0000 4 6 34 PRE_MSG_LENGTH 63 32 PRE_MSG_LENGTH_01 W Address 0xF406_0084 PRE_MSG_LENGTH_01 Bit Description Reset Value PRE_MSG_LENGTH_01 31 0 PRE_MSG_LENGTH 63 32 0x0000_0000 4 6 35 PRE_MSG_LENGTH 31 0 PRE_MSG_LENGTH_02 W Address 0xF406_0088 P...

Page 1818: ...ed 25 b0 CHNK_SZ 6 3 Chunk Size Bits 0000 Do not use Default 0001 Do not use 0010 Do not use 0011 128 bits 0100 160 bits 0101 192 bits 0110 224 bits 0111 256 bits 1000 288 bits 1001 320 bits 1010 352 bits 1011 384 bits 1100 416 bits 1101 448 bits 1110 480 bits 1111 512 bits 4 b0 Reserved 2 Reserved 1 b0 PREC_ID 1 0 Precision Bits 00 Single Precision Default 01 Double Precision 10 Triple Precision ...

Page 1819: ...un execution Default 1 Run Execution 1 b0 4 7 3 PKA Special Function Register 2 PKA_SFR2 R W Address 0xF407_1008 PKA_SFR2 Bit Description Reset Value Reserved 31 29 Reserved 3 b0 A_SEG_ID 28 24 Multiplicand A Memory Segment ID Bits 00000 Segment 0 Default 00001 Segment 1 00010 Segment 2 00011 Segment 3 00100 Segment 4 00101 Segment 5 00110 Segment 6 00111 Segment 7 01000 Segment 8 01001 Segment 9 ...

Page 1820: ...egment 8 01001 Segment 9 01010 Segment 10 01011 Segment 11 01100 Segment 12 01101 Segment 13 01110 Segment 14 01111 Segment 15 10000 Segment 16 10001 Segment 17 10010 Segment 18 10011 Segment 19 10100 Segment 20 10101 Segment 21 10110 Segment 22 10111 Segment 23 11000 Segment 24 11001 Segment 25 11010 Segment 26 11011 Segment 27 11100 Segment 28 11101 Segment 29 11110 Do not use 11111 Do not use 5...

Page 1821: ...ent 23 11000 Segment 24 11001 Segment 25 11010 Segment 26 11011 Segment 27 11100 Segment 28 11101 Segment 29 11110 Do not use 11111 Do not use Reserved 7 5 Reserved 3 b0 S_SEG_ID 4 0 Result S Memory Segment ID Bits 00000 Segment 0 Default 00001 Segment 1 00010 Segment 2 00011 Segment 3 00100 Segment 4 00101 Segment 5 00110 Segment 6 00111 Segment 7 01000 Segment 8 01001 Segment 9 01010 Segment 10 ...

Page 1822: ...INE BLOCK 11 3 43 PKA_SFR2 Bit Description Reset Value 10101 Segment 21 10110 Segment 22 10111 Segment 23 11000 Segment 24 11001 Segment 25 11010 Segment 26 11011 Segment 27 11100 Segment 28 11101 Segment 29 11110 Do not use 11111 Do not use ...

Page 1823: ...nt 13 is positive xx_xxxx_xxxx_xxxx_xx1x_xxxx_xxxx_xxxx Segment 13 is negative xx_xxxx_xxxx_xxxx_x0xx_xxxx_xxxx_xxxx Segment 14 is positive xx_xxxx_xxxx_xxxx_x1xx_xxxx_xxxx_xxxx Segment 14 is negative xx_xxxx_xxxx_xxxx_0xxx_xxxx_xxxx_xxxx Segment 15 is positive xx_xxxx_xxxx_xxxx_1xxx_xxxx_xxxx_xxxx Segment 15 is negative xx_xxxx_xxxx_xxx0_xxxx_xxxx_xxxx_xxxx Segment 16 is positive xx_xxxx_xxxx_xxx...

Page 1824: ... PKA_SFR4 Bit Description Reset Value Reserved 31 7 Reserved 25 b0 SEG_SIZE 6 5 Segment Size Bits 00 256 bytes 2048 bits Default 01 128 bytes 1024 bits 10 64 bytes 512 bits 2 b0 Reserved 4 1 Reserved 4 b0 FUNC_ID 0 Montgomery Product Function ID 0 Montgomery Multiplication A by B Default 1 Montgomery Multiplication A by 1 1 b0 ...

Page 1825: ... Hash Engine Busy 0 Hash Engine Ready 1 b0 SJ_JTAG_DETECT 0 Secure JTAG detection flag 1 JTAG access detection 0 No JTAG access detection 1 b0 4 8 3 Secure JTAG result register SJ_RESULT_REG R Address 0xF408_0008 SJ_RESULT_REG Bit Description Reset Value Reserved 31 16 Reserved 16 b0 SJ_ACCESS_MODE 15 8 Secure JTAG access mode 8 b0 Reserved 7 6 Reserved 2 b0 SJ_SEC_ACCESS_EN 5 Secure JTAG Secure A...

Page 1826: ...ormation 24 b0 4 8 5 Secure JTAG Password Register SJ_PASSWORD_REG R W Address 0xF408_0020 SJ_PASSWORD_REG Bit Description Reset Value sj_password 31 0 Secure JTAG password register 32 b0 4 8 6 Secure JTAG Password Control Register SJ_PASSWORD_CTRL_REG W Address 0xF408_0024 SJ_PASSWORD_CTRL_REG Bit Description Reset Value Reserved 31 2 Reserved 30 b0 SJ_PWD_FINISH 1 Secure JTAG password finish com...

Page 1827: ...ed for encryption decryption of security data 80 bit electrical fuse ROM1 2 for Secure boot key Secure boot key is used as a public key hash value for integrity check in secure booting sequence In booting time 1st boot loader reads secure boot key And if secure boot key is all zero then it boots without security check 96 bit electrical fuse ROM3 for Secure JTAG key Secure JTAG key is used as key f...

Page 1828: ...L REV1 0 11 4 2 1 2 BLOCK DIAGRAM SECKEY block e from Command FSM Register bank APB interface APB interface signals E from test ports Sensing start System Controller PMU Bus system Sensing done Figure 11 4 1 Security Key Block Diagram ...

Page 1829: ...e of debugging transaction 0 Non secure Access 1 Secure Access JTAG soft lock 1 Authentication on off 0 JTAG Security Check Off 1 JTAG Security Check On e fuse read lock for Root key 1 E from test port read disable 0 Enables e fuse port read 1 Disables e fuse port read e fuse read lock for Secure JTAG key 1 E from test port read disable 0 Enables e fuse port read 1 Disables e fuse port read e fuse...

Page 1830: ...nal I O Description Pad Type efrom_fsource_0 I Programming voltage VDD to program fuses VSS at all other time XefFSOURCE_0 Analog efrom_fvgate_0 I Separate power supply for programming FET gate and selection logic VSS to program fuses VDD 1 2V at all other time XefVGATE_0 Analog ...

Page 1831: ..._0038 R SPARE E fuse Area Register 0x0000_07FF NOTES 1 Although the reset value of registers is 0xXXXX_XXXX as power on sequence is progressing the e fuse values are loaded to the registers Hence SW cannot read register reset value itself but it can only read the loaded current e fuse values 2 The initial value of all e fuse bit is 0 4 1 ROOT KEY 0 REGISTER ROOTKEY0 R ADDRESS 0XF500_0000 ROOTKEY0 ...

Page 1832: ...DRESS 0XF500_0020 SECKEY2 Bit Description Reset Value Seckey2 31 0 Secure Boot Key 95 64 0xXXXX_XXXX 4 8 SECURE BOOT KEY 3 REGISTER SECKEY3 R ADDRESS 0XF500_0024 SECKEY3 Bit Description Reset Value Seckey3 31 0 Secure Boot Key 127 96 0xXXXX_XXXX 4 9 SECURE BOOT KEY 4 REGISTER SECKEY4 R ADDRESS 0XF500_0028 SECKEY4 Bit Description Reset Value Seckey4 31 0 Secure Boot Key 159 128 0xXXXX_XXXX 4 10 SPA...

Page 1833: ...L VDD_MPLL VDD_EPLL VDD_HPLL VDD_INT VDD_ALIVE VDD_ARM VDD12_UOTG VDD12_HDMI VDD12_MIPI 1 8 VDD18_MIPI_PLL VDDQ18_MIPI VDDQ_DDR 2 5 DC Power Supply VDDQ_M0 VDDQ_AUD VDDQ_CAN VDDQ_EXT VDDQ_MSM VDDQ_LCD VDDQ_MMC2 VDDQ_SYS0 VDDQ_SYS2 VDDQ_SYS5 VDDQ_MMC2 VDDQ_CI VDD33_UOTG VDDQ_UHOST VDD_RTC VDD30_DAC_A VDD30_DAC_D VDD33_ADC 4 6 1 8v Input Buffer 2 5 3 3v Input Buffer 4 6 DC Signal Input 3 3v with 5v ...

Page 1834: ... 1 25 For ARM Clk 667Mhz VDD_ARM 1 30 1 35 1 40 For ARM Clk 833Mhz VDDQ_AUD 1 7 1 8 3 3 3 6 VDDQ_CAN 1 7 1 8 3 3 3 6 VDDQ_EXT 1 7 1 8 3 3 3 6 VDDQ_MSM 1 7 1 8 3 3 3 6 VDDQ_LCD 1 7 1 8 3 3 3 6 VDDQ_SYS0 1 7 1 8 3 3 3 6 VDDQ_SYS2 1 7 1 8 3 3 3 6 VDDQ_SYS5 1 7 1 8 3 3 3 6 VDDQ_MMC2 1 7 1 8 3 3 3 6 VDDQ_CI 1 7 1 8 3 3 3 6 1 7 1 8 1 9 For mDDR DDR2 VDDQ_DDR 1 15 1 2 1 25 For LPDDR2 VDDQ_M0 1 7 1 8 3 3 ...

Page 1835: ...w Level Input Voltage Vil LVCMOS Interface 0 3 0 3 VDD V ΔV Hysteresis Voltage 0 1 VDD V High Level Input Current Input Buffer Vin VDD 10 10 uA Tolerant Input Buffer Vin Vext 10 10 uA VDD 3 3V 20 70 130 VDD 2 5V 10 40 80 Input Buffer with pull down Vin VDD VDD 1 8V 5 20 40 uA Vin 5V VDD 3 3V 10 30 60 Vin 3 3V VDD 2 5V 6 16 50 Iih Tolerant Input Buffer with pull up Vin 3 3V VDD 1 8V 2 8 18 uA Low L...

Page 1836: ...ffer Vin Vext 10 10 uA VDD 2 5V 10 40 80 Input Buffer with pull down Vin VDD VDD 1 8V 5 20 40 uA Vin 3 3V VDD 2 5V 3 10 40 Iih Tolerant Input Buffer with pull up Vin 3 3V VDD 1 8V 1 4 10 uA Low Level Input Current Input Buffer Vin VSS 10 10 uA VDD 2 5V 80 40 10 Iil Input Buffer with pull up Vin VSS VDD 1 8V 40 20 5 uA Voh Type A B C Ioh 100uA VDD 0 2 V Vol Type A B C Iol 100uA 0 2 V Ioz Tri State ...

Page 1837: ...ogic Low 0 3 0 3 VDDm0 V IIH High Level Input Current 10 10 uA IIL Low Level Input Current 10 10 uA High Level Input Current with Pull Down VDD 3 3V 20 70 130 uA High Level Input Current with Pull Down VDD 2 5V 10 40 80 uA IIH High Level Input Current with Pull Down VDD 1 8V 5 20 40 uA Low Level Input Current with Pull Up VDD 3 3V 130 70 20 uA Low Level Input Current with Pull Up VDD 2 5V 80 40 10...

Page 1838: ...el Input Current 10 10 uA High Level Input Current with Pull Down VDD 2 5V 10 40 80 uA IIH High Level Input Current with Pull Down VDD 1 8V 5 20 40 uA Low Level Input Current with Pull Up VDD 2 5V 80 40 10 uA IIL Low Level Input Current with Pull Up VDD 1 8V 40 20 5 uA VOH Output High Voltage Ioh 100uA VDDm1 0 2 V VOL Output Low Voltage Iol 100uA 0 2 V Table 12 1 7 USB DC Electrical Characteristic...

Page 1839: ...rameter Min Type Max Unit Output supply voltage CD0 of XrtcXTI PAD is one 1 7 1 8 2 2 2 3 V VDDrtc Output supply voltage CD0 of XrtcXTI PAD is zero 2 3 2 5 3 3 3 6 V VIH DC input logic high 0 7 VDDrtc V VIL DC input logic low 0 3 VDDrtc V IIH High level input current 10 10 μA IIL Low level input current 10 10 μA ...

Page 1840: ...cteristics also include a derating factor which indicates how much the AC timings might vary with different loads 1 2 VDD_SYS 1 2 VDD_SYS tXTALCYC NOTE The clock input from the XTIpll pin Figure 12 1 1 XTIpll Clock Timing tEXTHIGH 1 2 VDD_SYS VIL VIL VIH VIH 1 2 VDD_SYS tEXTLOW tEXTCYC NOTE The clock input from the EXTCLK pin Figure 12 1 2 EXTCLK Clock Input Timing HCLK internal EXTCLK tEX2HC Figu...

Page 1841: ...S5PC100 USER S MANUAL REV1 0 ELECTRICAL DATA 12 1 9 EXTCLK tRESW nRESET Figure 12 1 4 Manual Reset Input Timing ...

Page 1842: ...SER S MANUAL REV1 0 12 1 10 XTIpll VCO Output Clock Disable FCLK Several slow clock cycles XTIpll or EXTCLK Sleep mode is initiated tOSC2 EXTCLK Wake up from sleep mode Figure 12 1 5 Sleep Mode Return Oscillation Setting Timing ...

Page 1843: ...ion tOSC 10 cycle Oscillator stabilization to nRESET and nTRST high tOR 1 us External clock input high level pulse width tEXTHIGH 25 ns External clock to HCLK without PLL tEX2HC 5 10 ns HCLK internal to CLKOUT tHC2CK 4 10 ns HCLK internal to SCLK tHC2SCLK 2 8 ns Reset assert time after clock stabilization tRESW 4 XTIpll or EXTCLK APLL and MPLL Lock Time tPLL 300 us EPLL Lock Time 300 us Sleep mode...

Page 1844: ...ELECTRICAL DATA S5PC100 USER S MANUAL REV1 0 12 1 12 5 ROM SRAM AC ELECTRICAL CHARACTERISTICS Figure 12 1 6 ROM SRAM Timing Tacs 0 Tcos 0 Tacc 2 Tcoh 0 Tcah 0 PMC 0 ST 0 DW 16 bit ...

Page 1845: ... Delay tRCD 2 06 7 04 ns ROM SRAM Chip Select 2 Delay tRCD 2 34 7 69 ns ROM SRAM Chip Select 3 Delay tRCD 1 90 6 42 ns ROM SRAM Chip Select 4 Delay tRCD 2 00 6 70 ns ROM SRAM Chip Select 5 Delay tRCD 1 66 5 95 ns ROM SRAM nOE Output Enable Delay tROD 2 34 7 12 ns ROM SRAM nWE Write Enable Delay tRWD 2 29 7 27 ns ROM SRAM Byte Enable Delay tRBED 1 76 6 56 ns ROM SRAM Output Data Delay tRDD 1 70 8 0...

Page 1846: ...ELECTRICAL DATA S5PC100 USER S MANUAL REV1 0 12 1 14 6 ONENAND AC ELECTRICAL CHARACTERISTICS Figure 12 1 7 OneNand Flash Timing ...

Page 1847: ...H 6 ns OneNAND ADRVALID Setup time to SMCLK tAVDS 4 ns OneNAND ADRVALID Hold time to SMCLK tAVDH 6 ns OneNAND Write Data Setup time to SMCLK tWDS 4 ns OneNAND Write Data Hold time to SMCLK tWDH 2 ns OneNAND WEn Setup time to SMCLK tWES 4 ns OneNAND WEn Hold time to SMCLK tWEH 6 ns OneNAND ADRVALID high to OEn low tAVDO 0 ns OneNAND Access time from CSn low tCE 76 ns OneNAND Asynchronous Access tim...

Page 1848: ...R S MANUAL REV1 0 12 1 16 Parameter Symbol Min Max Unit OneNAND Data Hold time tDH 0 ns OneNAND CSn Setup time tCS 0 ns OneNAND CSn Hold time tCH 0 ns OneNAND WEn Pulse width low tWPL 40 ns OneNAND WEn Pulse width high tWPH 30 ns ...

Page 1849: ...OMMAND TWRPH 0 TWRPH 1 ADDRESS Xm0 DATA HCLK tCLED tCLED tWED tWED tWDD tWDD tALED tWED tALED tWED tWDD TACLS tWDD HCLK TWRPH0 TWRPH 1 Xm0DATA HCLK TWRPH0 TWRPH 1 Xm0DATA RDATA tWED tWED tWDD tRED tRED tRDS tRDH tWDD WDATA Xm0 DATA HCLK Xm0FCLE Xm0FWEn Xm0FWEn Xm0FALE Xm0FWEn Xm0FREn Figure 12 1 8 NAND Flash Timing ...

Page 1850: ...6V Parameter Symbol Min Max Unit NFCON Chip Enable delay tCED 8 06 ns NFCON CLE delay tCLED 7 63 ns NFCON ALE delay tALED 8 16 ns NFCON Write Enable delay tWED 7 75 ns NFCON Read Enable delay tRED 7 18 ns NFCON Write Data delay tWDD 7 96 ns NFCON Read Data Setup requirement time tRDS 1 00 ns NFCON Read Data Hold requirement time tRDH 0 20 ns ...

Page 1851: ...S5PC100 USER S MANUAL REV1 0 ELECTRICAL DATA 12 1 19 8 LPDDR1 MDDR SDRAM ELECTRICAL CHARACTERISTICS Figure 12 1 9 LPDDR1 SDRAM Read Write Timing Trp 2 Trcd 2 Tcl 2 DW 16 bit ...

Page 1852: ...DRAM Output data access time from CK tSAC 2 00 5 50 ns DDR SDRAM Row Precharge time tRP 18 00 ns DDR SDRAM RAS to CAS delay tRCD 18 00 ns DDR SDRAM Write recovery time tWR 12 00 ns DDR SDRAM Clock low level width tCL 0 45 0 55 tCK DDR SDRAM Read Preamble tRPRE 0 90 1 10 tCK DDR SDRAM Read Postamble tRPST 0 40 0 60 tCK DDR SDRAM Write Postamble time tWPST 0 40 0 60 tCK DDR SDRAM Clock to valid DQS ...

Page 1853: ...CTRICAL DATA 12 1 21 9 LCD CONTROLLER AC ELECTRICAL CHARACTERISTICS VSYNC HSYNC VDEN Tf2hsetup Tf2hhold Tvspw Tvbpd Tvfpd HSYNC VCLK VD VDEN Tl2csetup Tvclkh Tvclk Tvclkl Tvdhold Tvdsetup Tve2hold Figure 12 1 10 LCD Controller Timing ...

Page 1854: ...th Tvspw VSPW 1 Phclk 2 Vertical back porch delay Tvbpd VBPD 1 Phclk Vertical front porch dealy Tvfpd VFPD 1 Phclk Hsync setup to VCLK falling edge Tl2csetup 0 3 Pvclk VDEN setup to VCLK falling edge Tde2csetup 0 3 Pvclk VDEN hold from VCLK falling edge Tde2chold 0 3 Pvclk VD setup to VCLK falling edge Tvd2csetup 0 3 Pvclk VD hold from VCLK falling edge Tvd2chold 0 3 Pvclk VSYNC setup to HSYNC fal...

Page 1855: ...e 12 1 15 LCD I80 Interface Signal Timing Constants VDD_INTNT 1 2V 0 05V TA 40 to 85 C VDDlcd 1 7V 3 6V Parameter Symbol Min Typ Max Units SYS_RS to SYS_CSn Low Tcssetup LCD_CS_SETUP 1 Pvclk SYS_CSn Low to SYS_WR Low Twrsetup LCD_WR_SETUP 1 Pvclk SYS_WE Pulse Width Twract LCD_WR_ACT 1 Pvclk SYS_WE Hight to SYS_CSn High Twrhold LCD_WR_HOLD 1 Pvclk NOTE Internal VCLK period ...

Page 1856: ... CAM_HREF_B Figure 12 1 12 Camera Interface HREF Timing Figure 12 1 13 Camera Interface Data Timing Table 12 1 16 Camera Controller Module Signal Timing Constants VDD_INTNT 1 2V 0 05V TA 40 to 85 C VDDext 1 7V 3 6V Parameter Symbol Min Typ Max Units XciHREF CAM_HREF_A input Setup time Tsshrefa 3 15 PA 0 59 ns XciHREF CAM_HREF_A input Hold time Thhrefa 0 59 PA 3 15 ns XciDATA CAM_DATA_A input Setup...

Page 1857: ...XEINT 26 CAM_HREF_B input Setup time Tsshrefb 0 98 PA 2 88 ns XEINT 26 CAM_HREF_B input Hold time Thhrefb 2 88 PB 0 98 ns XEINT 23 16 CAM_DATA_B input Setup time Tssdatab 0 93 PA 3 78 ns XEINT 23 16 CAM_DATA_B input Hold time Thdatab 3 78 PB 0 93 ns NOTE PB denotes period ns of CAM_PCLK_B ...

Page 1858: ... 1V Parameter Symbol Min Type Max Unit SD Command output Delay time tSDCD 1 0 14 0 ns SD Command input Setup time tSDCS 4 0 1 ns SD Command input Hold time tSDCH 0 1 ns SD Data output Delay time tSDDD 1 0 14 0 ns SD Data input Setup time tSDDS 4 0 2 ns SD Data input Hold time tSDDH 0 1 ns NOTE 1 2 This values shows when the Rx Feedback Clock selections are enabled If the Rx Feedback Clock selectio...

Page 1859: ...TRICAL DATA 12 1 27 12 SPI AC ELECTRICAL CHARACTERISTICS SPICLK tSPIMIH tSPIMIS XspiMOSI MO XspiMOSI SI XspiMISO MI tSPIMOD tSPISIS tSPISIH XspiMISO SO tSPISOD XspiCS tSPICSSS tSPICSSD Figure 12 1 15 SPI Interface Timing CPHA 0 CPOL 1 ...

Page 1860: ... Delay 0nS 4 ns SPI MISO Master Input Hold time Feedback Delay 2nS 5 ns SPI MISO Master Master Input Hold time Feedback Delay 4nS 7 ns SPI MISO Master Input Hold time Feedback Delay 6nS tSPIMIH 9 ns SPI MOSI Slave Input Setup time tSPISIS 3 ns SPI MOSI Slave Input Hold time tSPISIH 3 ns SPI MISO Slave output Delay time tSPISOD 10 ns SPI nSS Master Output Delay time tSPICSSD 23 ns Ch 0 SPI nSS Slav...

Page 1861: ...PI nSS Master Output Delay time tSPICSSD 23 ns SPI nSS Slave Input Setup time tSPICSSS 20 ns SPI MOSI Master Output Delay time tSPIMOD 4 ns SPI MISO Master Input Setup time Feedback Delay 0nS tSPIMIS 3 ns SPI MISO Master Input Setup time Feedback Delay 2nS 2 ns SPI MISO Master Input Setup time Feedback Delay 4nS 1 ns SPI MISO Master Input Setup time Feedback Delay 6nS 1 ns SPI MISO Master Input Ho...

Page 1862: ...12 1 30 Parameter Symbol Min Typ Max Unit SPI MOSI Slave Input Hold time tSPISIH 3 ns SPI MISO Slave Output Delay time tSPISOD 10 ns SPI nSS Master Output Delay time tSPICSSD 23 ns SPI nSS Slave Input Setup time tSPICSSS 20 ns NOTE SPICLKout 50MHz ...

Page 1863: ... 4 7 fast 1 3 μs Bus free time between STOP and START tBUF std 4 7 fast 1 3 μs START hold time tSTARTS std 4 0 fast 0 6 μs SDA hold time tSDAH std 0 fast 0 std fast 0 9 μs SDA setup time tSDAS std 250 fast 100 μs STOP setup time tSTOPH std 4 0 fast 0 6 μs NOTES std stands for Standard Mode and fast means Fast Mode 1 The IIC data hold time tSDAH is Min 0ns IIC data hold time is Min 0ns for standard...

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