Samsung S5PC100, User Manual, Page: 185 / 1863

S5PC100 USER’S MANUAL (REV1.0) CLOCK CONTROLLER
2.3-35
10.3 CLOCK DIVIDER CONTROL REGISTER
S5PC100 has several clock dividers to support various operating clock frequency. CLK_DIV0, CLK_DIV1,
CLK_DIV2, CLK_DIV3, CLK_DIV4, and CLK_DIV_5 controls clock divider ratio.
There are operating frequency limitations. The maximum operating frequency of DOUT
MPLL,
DOUT
MPLL2,
DOUT
D1_BUS
, HCLKD1, and PCLKD1 are 266MHz, 266MHz, 133MHz, 133MHz, and 66MHz respectively. These
operating clock conditions must be met through CLK_DIVX configuration.
10.3.1 Set Clock Divider Ratio 0 (Main D0 domain) (CLK_DIV0, R/W, Address = 0xE010_0300)
Main D0 domain divider
CLK_DIV0 Bit Description Reset Value
Reserved [31:19] Reserved -
SECSS_RATIO [18:16]
DIV
SECSS
clock divider ratio,
HCLKD0_SECSS = DOUT
D0_BUS
/ RATIO ( RATIO =
SECSS 1 )
SECSS (Secure Sub-System) operating clock cannot exceed
83MHz.
0x1
Reserved [15] Reserved -
PCLKD0_RATIO [14:12]
DIV
PCLKD0
clock divider ratio,
PCLKD0 = HCLKD0 / RATIO ( RATIO = PCLKD0 1 )
0x1
Reserved [11] Reserved -
DO_BUS_RATIO [10:8]
DIV
D0_BUS
clock divider ratio,
HCLKD0 = DOUT
ARM
/ RATIO ( RATIO = D0_BUS 1 )
0x0
RESERVED [7] RESERVED -
ARM_RATIO [6:4]
DIV
ARM
clock divider ratio,
ARMCLK = DOUT
APLL
/ RATIO ( RATIO = ARM 1 )
0x0
Reserved [3:1] Reserved -
APLL_RATIO [0]
DIV
APLL
clock divider ratio,
DOUT
APLL
= MOUT
APLL
/ RATIO ( RATIO = APLL 1 )
0x0
At least one of the ARM clock dividers (DIV
APLL
and DIV
ARM
) must be set to more than 1. For more information
refer to “Section 7.1”.