Samsung S5PC100, User Manual

Page: 356 / 1863

ASYNC BRIDGE S5PC100 USER’S MANUAL (REV1.0)
3.4-14
3 REGISTER DESCRIPTION
Register Address R/W Description Reset Value
HALFSYNC 0xE340_0000 R/W 1/2 cycle synchronizer selection 0x00
ASYNC_INDEX 0xE340_0004 R/W Async index register for write enhancing 0x00
DMASTER 0xE340_0008 R/W Optimizing delay for default master 0x00
NOTE: If async bridge has highest priority in AXI interconnect, then async bridge is handled as a default master.
3.1 HALFSYNC REGISTER (HALFSYNC, R/W, 0XE340_0000)
HALFSYNC Bit Description Reset Value
Reserved [31:1] Reserved 0
HALFSYNC SEL
[0] 0 = Using 1 cycle synchronizer
1 = Using 1/2 cycle synchronizer
0
3.2 ASYNCINDEX REGISTER (ASYNCINDEX, R/W, 0XE340_0004)
ASYNCINDEX Bit Description Reset Value
Reserved [31:3] Reserved 0
ASYNC_INDEX
[2:0]
0 = D0 clock : D1 clock = 1: 1 & W channel BW improve off
1 = D0 clock : D1 clock = 6: 5 & W channel BW improve on
2 = D0 clock : D1 clock = 5: 4 & W channel BW improve on
3 = D0 clock : D1 clock = 4: 3 & W channel BW improve on
4 = D0 clock : D1 clock = 3: 2 & W channel BW improve on
5 = D0 clock : D1 clock = 2: 1 & W channel BW improve on
0x0
3.3 DMASTER REGISTER (DMASTER, R/W, 0XE340_0008)
Name Bit Description Reset Value
Reserved [31:1] Reserved 0
DEFAULT_MASTER
[0]
0 = Optimizing AW channel delay to non-default master
1 = Optimizing AW channel delay to default master
0x0
NOTE: All SFR can be programmed at anytime