ASYNC BRIDGE
S5PC100 USER’S MANUAL (REV1.0)
3.4-6
T1
Data is written into the FIFO.
T2
The write pointer update occurs.
T3
The first synchronization stage of this value to the read side occurs because enough time has elapsed
since the write pointer updated.
T4
The second synchronization stage occurs and enables synchronized pointer visible to the read side.
T5
The read side asserts its valid signal because it has compared the read and synchronized write pointers
and they are different.
T6
The data is read.
T7
The read pointer update occurs. The old or new value being captured is unpredictable because this
value is changing on the ACLKS edge, when the synchronizer is sampling. In this case the old value is
captured.
T8
The read pointer starts synchronizing to the write side.
T9
Synchronization is complete.
After T9
The read side can again indicate that it is ready to accept data.
1.3.2 Gray Code
The Gray code used for an N-entry FIFO has 2N values in its sequence, and the order of the values is chosen so
that each value, when XORed with the value N places away from it, gives the same result and does not give that
result when XORed with any other value in the sequence. This enables the fullness and emptiness to be
determined by comparing the two counters:
•
Emptiness is shown by the read and write counters being the same.
•
Fullness is shown by the result of XORing the read and write counters being the first value in the second half
of the sequence, at position N.
The required Gray code can be calculated by an algorithm:
•
The number of bits required in the Gray code, k, can be calculated as:
k = ceil(log2(N)) +1
Where ceil represents a function that rounds its argument up to the nearest integer.
•
The first N values, positions 0 to N-1 in the sequence, are derived from the binary value of their position in the
sequence: Bits of the binary value B[k-1:0] is mapped to the bits of Gray coded value G[k-1:0] using the
following rules:
G[k-1] = B[k-1] (== 0)
G[i] = B[i] XOR B[i+1]
where
0<=i<k-1
Summary of Contents for S5PC100
Page 21: ...MEMORY MAP S5PC100 USER S MANUAL REV1 0 1 2 2 ...
Page 34: ...S5PC100 USER S MANUAL REV1 0 BALL MAP SIZE POP 1 1 9 1 4 MCP CONNECTION ...
Page 49: ...IROM CODE S5PC100 USER S MANUAL REV1 0 2 6 4 12 Mhz 300 0 Mhz 100 0 Mhz 79 5 Mhz 20 6 Mhz ...
Page 174: ...CLOCK CONTROLLER S5PC100 USER S MANUAL REV1 0 2 3 24 Rs 0ohm Rf 1Mohm CL 10 35pF ...
Page 322: ...CORESIGHT S5PC100 USER S MANUAL REV1 0 3 2 4 Figure 3 2 2 S5PC100 Coresight Structure ...
Page 330: ...CORESIGHT S5PC100 USER S MANUAL REV1 0 3 2 12 Figure 3 2 7 ETB Block Diagram ...
Page 345: ...S5PC100 USER S MANUAL REV1 0 ASYNC BRIDGE 3 4 3 Figure 3 4 2 Asynchronous Bridge Components ...
Page 359: ...S5PC100 USER S MANUAL REV1 0 VECTORED INTERRUPT CONTROLLER 4 1 3 Figure 4 1 2 VIC Daisy Chain ...
Page 651: ...S5PC100 USER S MANUAL REV1 0 UART 8 1 27 Figure 8 1 10 UINTSP UINTP and UINTM block diagram ...
Page 652: ...UART S5PC100 USER S MANUAL REV1 0 8 1 28 NOTES ...
Page 743: ...S5PC100 USER S MANUAL REV1 0 MIPI HSI INTERFACE CONTROLLER 8 6 13 ...
Page 756: ...MIPI HSI INTERFACE CONTROLLER S5PC100 USER S MANUAL REV1 0 8 6 26 NOTES ...
Page 800: ...MIPI CSIS S5PC100 USER S MANUAL REV1 0 8 8 10 NOTES ...
Page 816: ...USB HOST CONTROLLER S5PC100 USER S MANUAL REV1 0 8 9 16 ...
Page 935: ...S5PC100 USER S MANUAL REV1 0 MODEM INTERFACE 8 11 13 NOTES ...
Page 1111: ...S5PC100 USER S MANUAL REV1 0 IMAGE ROTATOR 9 2 3 3 4 180 DEGREE ROTATION ...
Page 1112: ...IMAGE ROTATOR S5PC100 USER S MANUAL REV1 0 9 2 4 3 5 90 AND 270 DEGREE ROTATION ...
Page 1118: ...S5PC100 USER S MANUAL REV1 0 CAMERA INTERFACE 9 3 3 Figure 9 3 2 Camera Interface Overview ...
Page 1181: ...JPEG S5PC100 USER S MANUAL REV1 0 9 4 6 Figure 9 4 5 YCbCr4 2 2 Color Format ...
Page 1199: ...JPEG S5PC100 USER S MANUAL REV1 0 9 4 24 NOTES ...
Page 1245: ...3D ACCELERATOR S5PC100 USER S MANUAL REV1 0 9 6 18 ...
Page 1353: ...TVOUT VIDEO DAC S5PC100 USER S MANUAL REV1 0 9 7 32 ...
Page 1452: ...S5PC100 USER S MANUAL REV1 0 VIDEO PROCESSOR 9 8 43 NOTES ...
Page 1482: ...MIXER S5PC100 USER S MANUAL REV1 0 9 9 30 NOTES ...
Page 1664: ...S5PC100 USER S MANUAL REV1 0 I2S CONTROLLER 5 1CH 10 2 31 NOTES ...
Page 1701: ...AC97 CONTROLLER S5PC100 USER S MANUAL REV1 0 10 4 18 NOTES ...
Page 1731: ...SPDIF TRANSMITTER S5PC100 USER S MANUAL REV1 0 10 6 16 NOTES ...
Page 1744: ...S5PC100 USER S MANUAL REV1 0 ADC AND TOUCH SCREEN INTERFACE 10 7 13 NOTES ...
Page 1750: ...KEYPAD INTERFACE S5PC100 USER S MANUAL REV1 0 10 8 6 Figure 10 8 7 Keypad I F Block Diagram ...
Page 1755: ...S5PC100 USER S MANUAL REV1 0 KEYPAD INTERFACE 10 8 11 NOTES ...
Page 1779: ...SECURE DOMAIN MANAGER S5PC100 USER S MANUAL REV1 0 11 2 22 NOTES ...