Samsung S5PC100, User Manual

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ASYNC BRIDGE S5PC100 USER’S MANUAL (REV1.0)
3.4-10
2.2 BANDWIDTH IMPROVEMENT
When the read data transaction is distributed evenly, there will be no penalty in D0 domain with any Async Bridge
in case of the dram utilization is smaller then the clock speed rate between D1/D0.
However, the actual transactions are distributed in burst; you must consider the architecture of Async Bridge.
2.2.1 Read Performance
When the master in slow domain burst reads slave in fast domain, the read FIFO of Async Bridge may overflow. It
causes read data channel stall, and the stalling of data channel creates bubbles in data bus.
Because the read data bubbles are generated after DRAM controller operation, there is no bus component that
can remove these bubbles except Async Bridge.
Fortunately, these read data bubbles can be reduced by increasing read data FIFO size of Async Bridge. In
S5PC100, the read data FIFO size is increased to 32. We assumed the worst case is the 4 successive 16burst is
one bunch of transaction. And the 4 bunch of transaction are serviced with the 10 cycle interval between the
bunch of transactions. Figure 3.4-8 shows the timing diagram of upper situation to help the decision logic of read
data FIFO size.
Figure 3.4-8 Example Timing Diagram of Async Bridge for Deciding the Read Data FIFO Size