Samsung S5PC100, User Manual, Page: 395 / 1863

DRAM CONTROLLER S5PC100 USER’S MANUAL (REV1.0)
5.1-12
To calculate the DDR2 rd_fetch value:
rd_fetch DDR2) = INT((Delay + 0.5T + 0.25T)/T) = INT(Delay/T + 0.75),
Delay: board delay + PHY input/output delay, T: clock period, INT(x): the rounded-up integer value of x
Therefore, rd_fetch must have minimum one value.
T0 T1 T2 T3 T4 T5 T6
CK
DQS
DQ
SDRAM command
Q0 Q2 Q3
T7
READ
{Q1, Q0} {Q3, Q2}
{Q1, Q0} {Q3, Q2}
PHY read input FIFO
AXI read channel
RL = 3
RL + rd_fetch = 4
T8
90' phase shifted DQS
Q1
negedge
sampling
negedge
sampling
tDQSCK
Figure 5.1-7 Timing Diagram of Read Data Capture
(LPDDR/LPDDR2, zero delay, RL=3, rd_fetch=1)
An LPDDR/LPDDR2 does not have an internal DLL. Without an internal DLL as you may see in Figure 5.1-7, the
data is sent out after tDQSCK before the read latency is over. Even if we assume zero delay, since tDQSCK
becomes relatively large in high frequencies, the read fetch cycle should be set to one.
Delay
T0 T1 T2 T3 T4 T5 T6
CK
DQS
DQ
SDRAM command
Q0 Q2 Q3
T7
READ
{Q1, Q0} {Q3, Q2}
{Q1, Q0} {Q3, Q2}
PHY read input FIFO
AXI read channel
RL = 3
RL + rd_fetch = 5
T8
90' phase shifted DQS
Q1
negedge
sampling
negedge
sampling
tDQSCK
Figure 5.1-8 Timing Diagram of Read Data Capture
(LPDDR/LPDDR2, non-zero delay, RL=3, rd_fetch=2)
If a delay exists such as Figure 5.1-8, a bigger value should be assigned to rd_fetch.