Samsung S5PC100, User Manual

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WATCHDOG TIMER S5PC100 USER’S MANUAL (REV1.0)
7.3-2
3 FUNCTIONAL DESCRIPTION
3.1 WATCHDOG TIMER OPERATION
The Figure 7.3-1 shows the functional block diagram of the watchdog timer. The watchdog timer uses PCLK as its
source clock. The PCLK frequency is prescaled to generate the corresponding watchdog timer clock, and the
resulting frequency is divided again.
Reset Signal Generator
WTCNT
(Down Counter)
PCLK
WTCON[4:3]
WTDAT
RESET
1/16
1/32
1/64
1/128
8-bit Prescaler
WTCON[15:8] WTCON[2] WTCON[0]
Interrupt
MUX
Figure 7.3-1 Watchdog Timer Block Diagram
The prescaler value and the frequency division factor are specified in the watchdog timer control (WTCON)
register. Valid prescaler values range from 0 to 28-1. The frequency division factor can be selected as 16, 32, 64,
or 128.
Use the following equation to calculate the watchdog timer clock frequency and the duration of each timer clock
cycle:
t_watchdog = 1/( PCLK / (Prescaler value + 1) / Division_factor )
3.2 WTDAT & WTCNT
Once the watchdog timer is enabled, the value of watchdog timer data (WTDAT) register cannot be automatically
reloaded into the timer counter (WTCNT). For this reason, an initial value must be written to the watchdog timer
count (WTCNT) register, before the watchdog timer starts.
3.3 WDT START
To start WDT, set WTCON[0] and WTCON[5] as 1.
3.4 CONSIDERATION OF DEBUGGING ENVIRONMENT
If the S5PC100 is in debug mode using Embedded ICE, the watchdog timer must not operate.
The watchdog timer determines whether it is currently in the debug mode from the CPU core signal (DBGACK
signal). Once the DBGACK signal is asserted, the reset output of the watchdog timer is not activated as the
watchdog timer is expired.