I2S CONTROLLER(5.1CH)
S5PC100 USER’S MANUAL (REV1.0)
10.2-2
3 BLOCK DIAGRAM
Register
File
TxR
Channel
Control
TxDMA
FSM
RxDMA
FSM
Clock
Control
Tx Shift
Register
Rx Shift
Register
TxFIFO
RxFIFO
TxDREQ
TxDACK
APB
RxDREQ
RxDACK
I2SBCLK
I2SLRCLK
I2SSDO 0
I2SSDI
I2SCODCLKO
I2SCODCLKI
Tx Shift
Register
Tx Shift
Register
I2SSDO 1
I2SSDO 2
AHB DMA
D2_SS
Bus
PCLK Domain
Codec CLK
Domain
S
y
n
c
h
r
o
n
iz
e
r
Synchronizer
Synchronizer
S
y
n
c
h
r
o
n
iz
e
r
S
y
n
c
h
r
o
n
iz
e
r
Core CLK
Domain
Figure 10.2-1 I2S-Bus Block Diagram
4 FUNCTIONAL DESCRIPTIONS
I2S interface consists of register bank, FIFOs, shift registers, clock control, DMA finite state machine, and channel
control block as shown in Figure 10.2-1. Note that each FIFO has 32-bit width * 64 depth structure, which contains
left/ right channel data. Therefore, FIFO access and data transfer are handled with left/ right pair unit. Figure 10.2-
1 shows the functional block diagram of I2S interface.
4.1 MASTER/ SLAVE MODE
Set IMS bit of I2SMOD register to select master or slave mode. In master mode, I2SSCLK and I2SLRCLK are
generated internally and supplied to external device. Therefore a root clock is needed for generating I2SSCLK
and I2SLRCLK. The I2S pre-scaler (clock divider) generates a root clock with divided frequency from internal
system clock. In external master mode, the root clock is fed directly from external I2S. The I2SSCLK and
I2SLRCLK are supplied from the pin (GPIOs) in slave mode.
Master/ Slave mode is different with TX/RX. Master/Slave mode presents the direction of I2SLRCLK and
I2SSCLK. The direction of I2SCDCLK (This is only auxiliary) is not a concern. If I2S bus interface transmits clock
signals to I2S codec, I2S bus is master mode. But if I2S bus interface receives clock signal from I2S codec, I2S
bus is slave mode. TX/RX mode indicates the direction of data flow. If I2S bus interface transmits data to I2S
codec, this is TX mode. Conversely, I2S bus interface receives data from I2S codec that is RX mode. Let us
distinguish Master/ Slave mode from TX/RX mode.
Summary of Contents for S5PC100
Page 21: ...MEMORY MAP S5PC100 USER S MANUAL REV1 0 1 2 2 ...
Page 34: ...S5PC100 USER S MANUAL REV1 0 BALL MAP SIZE POP 1 1 9 1 4 MCP CONNECTION ...
Page 49: ...IROM CODE S5PC100 USER S MANUAL REV1 0 2 6 4 12 Mhz 300 0 Mhz 100 0 Mhz 79 5 Mhz 20 6 Mhz ...
Page 174: ...CLOCK CONTROLLER S5PC100 USER S MANUAL REV1 0 2 3 24 Rs 0ohm Rf 1Mohm CL 10 35pF ...
Page 322: ...CORESIGHT S5PC100 USER S MANUAL REV1 0 3 2 4 Figure 3 2 2 S5PC100 Coresight Structure ...
Page 330: ...CORESIGHT S5PC100 USER S MANUAL REV1 0 3 2 12 Figure 3 2 7 ETB Block Diagram ...
Page 345: ...S5PC100 USER S MANUAL REV1 0 ASYNC BRIDGE 3 4 3 Figure 3 4 2 Asynchronous Bridge Components ...
Page 359: ...S5PC100 USER S MANUAL REV1 0 VECTORED INTERRUPT CONTROLLER 4 1 3 Figure 4 1 2 VIC Daisy Chain ...
Page 651: ...S5PC100 USER S MANUAL REV1 0 UART 8 1 27 Figure 8 1 10 UINTSP UINTP and UINTM block diagram ...
Page 652: ...UART S5PC100 USER S MANUAL REV1 0 8 1 28 NOTES ...
Page 743: ...S5PC100 USER S MANUAL REV1 0 MIPI HSI INTERFACE CONTROLLER 8 6 13 ...
Page 756: ...MIPI HSI INTERFACE CONTROLLER S5PC100 USER S MANUAL REV1 0 8 6 26 NOTES ...
Page 800: ...MIPI CSIS S5PC100 USER S MANUAL REV1 0 8 8 10 NOTES ...
Page 816: ...USB HOST CONTROLLER S5PC100 USER S MANUAL REV1 0 8 9 16 ...
Page 935: ...S5PC100 USER S MANUAL REV1 0 MODEM INTERFACE 8 11 13 NOTES ...
Page 1111: ...S5PC100 USER S MANUAL REV1 0 IMAGE ROTATOR 9 2 3 3 4 180 DEGREE ROTATION ...
Page 1112: ...IMAGE ROTATOR S5PC100 USER S MANUAL REV1 0 9 2 4 3 5 90 AND 270 DEGREE ROTATION ...
Page 1118: ...S5PC100 USER S MANUAL REV1 0 CAMERA INTERFACE 9 3 3 Figure 9 3 2 Camera Interface Overview ...
Page 1181: ...JPEG S5PC100 USER S MANUAL REV1 0 9 4 6 Figure 9 4 5 YCbCr4 2 2 Color Format ...
Page 1199: ...JPEG S5PC100 USER S MANUAL REV1 0 9 4 24 NOTES ...
Page 1245: ...3D ACCELERATOR S5PC100 USER S MANUAL REV1 0 9 6 18 ...
Page 1353: ...TVOUT VIDEO DAC S5PC100 USER S MANUAL REV1 0 9 7 32 ...
Page 1452: ...S5PC100 USER S MANUAL REV1 0 VIDEO PROCESSOR 9 8 43 NOTES ...
Page 1482: ...MIXER S5PC100 USER S MANUAL REV1 0 9 9 30 NOTES ...
Page 1664: ...S5PC100 USER S MANUAL REV1 0 I2S CONTROLLER 5 1CH 10 2 31 NOTES ...
Page 1701: ...AC97 CONTROLLER S5PC100 USER S MANUAL REV1 0 10 4 18 NOTES ...
Page 1731: ...SPDIF TRANSMITTER S5PC100 USER S MANUAL REV1 0 10 6 16 NOTES ...
Page 1744: ...S5PC100 USER S MANUAL REV1 0 ADC AND TOUCH SCREEN INTERFACE 10 7 13 NOTES ...
Page 1750: ...KEYPAD INTERFACE S5PC100 USER S MANUAL REV1 0 10 8 6 Figure 10 8 7 Keypad I F Block Diagram ...
Page 1755: ...S5PC100 USER S MANUAL REV1 0 KEYPAD INTERFACE 10 8 11 NOTES ...
Page 1779: ...SECURE DOMAIN MANAGER S5PC100 USER S MANUAL REV1 0 11 2 22 NOTES ...