Samsung S5PC100, User Manual

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CORESIGHT S5PC100 USER’S MANUAL (REV1.0)
3.2-2
1.2 FEATURES
1.2.1 Debug Access
You gain debug access in CoreSight systems through the Debug Access Port (DAP) that provides:
•
real-time access to physical memory without halting the core and without any target resident code
•
debug control and access to all status registers
The same mechanism provides fast access for downloading code at the start of the debug session. This is faster
than the traditional JTAG mechanism that uses the ARM core to write data to memory. You can still use the ARM
core to write data to virtual memory and to ease migration when the debugger does not support this approach.
Figure 3.2-1 shows an example system with debug components and a DAP in a SoC design.
The DAP provides the following advantages for multi-core SoC designs:
•
There is no requirement to run at the lowest common speed. A slow or powered down component has no
effect on access to other components. This means that power management has minimal impact on debug.
•
The speed of access is not affected by the number of devices in the system. You have direct access to
individual devices.
•
You can add third party debug components with the Advanced Microcontroller Bus Architecture (AMBA)
debug bus interface, AMBA 3 Advanced Peripheral Bus (APB), that provides internal and external access to
the component.
•
More than one core can control debug functionality, rather than restricting this to the core being debugged.
One core can debug another. In particular this enables a multi-core SoC when used as a single core platform
to have complex on-chip debug and analysis features. You could use this, for example, during application
development.
Figure 3.2-1 DAP Connections Inside a SoC