Samsung S5PC100, User Manual

Page: 1139 / 1863

CAMERA INTERFACE S5PC100 USER’S MANUAL (REV1.0)
9.3-24
CIGCTRLn Bit Description
Reset
Value
M
L
IRQ_Ovfen [22]
1 = Enables Overflow interrupt (Interrupt is generated during overflow
occurrence)
0 = Disables Overflow interrupt (normal)
0
X X
Href_mask [21]
1 = Mask out Href during Vsync blank
0 = No mask
0
X X
IRQ_LEVEL [20]
1 = Level interrupt
0 = Edge trigger interrupt (default)
This bit should be set as ‘1’ since S5PC100 uses only level interrupt.
0
X X
IRQ_CLR [19]
This bit is related only Level interrupt. Write IRQ_CLR to ‘1’ to clear
Interrupt. This bit Auto-clear.
0
X X
Reserved [18:17] Reserved 0
X X
IRQ_Enable [16]
1 = Enables Interrupt (default)
0 = Disables Interrupt
1
X X
Reserved [15:8] Reserved 0
X X
Reserved [7] Should be ‘1’ 1
Reserved [6:5] Reserved 0
X X
InvPolHSYNC [4]
1 = Inverse the polarity of HSYNC (this bit is useful only delay count
interlace mode and FIELD port is connected HSYNC)
0 = Normal
0
X X
SelCam_CAMIF [3]
External camera select
1 = Selects MIPI Camera
0 = Selects ITU Camera
0
X X
FIELDMODE [2]
ITU601 Interlace field mode (Do not care this bit in ITU656 mode)
1 = Using the FIELD port mode (FIELD port = FIELD signal)
0 = Edge delay count mode (FIELD port = HSYNC signal)
Note: Check!! FIELD port connection
0
X X
InvPolFIELD [1] 1 = Inverse the polarity of FIELD 0 = Normal 0
X X
Cam_Interlace [0]
External Cameraj scan method
1 = Interlace 0 = Progressive
0
X X