Samsung S5PC100, User Manual

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SD/MMC CONTROLLER S5PC100 USER’S MANUAL (REV1.0)
8.12-72
9.28 ADMA ERROR STATUS REGISTER
ADMA Error Status Register
•
ADMAERR0, R/W, Address = 0xED80_0054
•
ADMAERR1, R/W, Address = 0xED90_0054
•
ADMAERR2, R/W, Address = 0xEDA0_0054
If ADMA Error Interrupt occurs, the ADMA Error States field in this register holds the ADMA state and the ADMA
System Address Register holds the address around the error descriptor. For recovering the error, the Host Driver
requires the ADMA state to identify the error descriptor address as follows:
ST_STOP: Previous location set in the ADMA System Address register is the error descriptor address
ST_FDS: Current location set in the ADMA System Address register is the error descriptor address
ST_CADR: This sate is never set because do not generate ADMA error in this state.
ST_TFR: Previous location set in the ADMA System Address register is the error descriptor address
In case of write operation, the Host Driver should use ACMD22 to get the number of written block rather than
using this information, since unwritten data may exist in the Host Controller.
The Host Controller generates the ADMA Error Interrupt if it detects invalid descriptor data (Valid = 0) at the
ST_FDS state. In this case, ADMA Error State indicates that an error occurs at ST_FDS state. The Host Driver
finds that the Valid bit is not set in the error descriptor.
ADMAERR Bit Description Reset Value
Reserved [31:11] Reserved 0x00
STAADMAFINBLK [10] ADMA Final Block Transferred (ROC)
In ADMA operation mode, this field is set to High if the Transfer
Complete condition and the block are final (no block transfer
remains).
If this bit is Low when the Transfer Complete condition and
Transfer Complete is done due to the Stop at Block Gap, so data
to be transferred still remains.
0
ADMACONTREQ [9] ADMA Continue Request (WO)
If the stop state by ADMA Interrupt, ADMA operation set this bit to
HIGHT to continue.
0
ADMASTAINT [8] ADMA Interrupt Status (RW1C)
This bit is set to HIGH if INT attribute in the ADMA Descriptor
Table is asserted. This bit is not affected by ADMA error interrupt.
0
[7:3] Reserved 0
ADMALENMISERR [2] ADMA Length Mismatch Error
This error occurs in the following 2 cases.
(1) While Block Count Enable being set, the total data length
specified by the Descriptor table is different from that specified by
the Block Count and Block Length.
(2) Total data length can not be divided by the block length.
'0' = No Error
00