Samsung S5PC100, User Manual

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Power Management S5PC100 USER’S MANUAL (REV1.0)
2.4-66
10.5.10 APLL_CON_L8 Register (APLL_CON_L8, R/W, Address = 0xE010_8600)
The register configures P/M/S values for ARM PLL at IEM performance level of 8.
APLL_CON_L8 Bit Description Reset Value
Reserved [31:28] Reserved 0x0
Reserved [27:26] Reserved 00
apll_mval_l8 [25:16] M[9:0] value for ARM PLL at IEM performance level of 8 0x190
Reserved [15:14] Reserved 00
apll_pval_l8 [13:8] P[5:0] value for ARM PLL at IEM performance level of 8t 0x03
Reserved [7:4] Reserved 0x0
Reserved [3] Reserved 0
apll_sval_l8 [2:0] S[2:0] value for ARM PLL at IEM performance level of 8 0x2
Use following equation to calculate frequency of PLL output clock:
Fout (Hz) = (m * Fin) / (p * 2
s
)
where m = (MDIV + 8), p = (PDIV + 2), s = SDIV
apll_mval_l8[9:0] is equal to MDIV[9:0] , apll_pval_l8 is equal to PDIV[5:0], and apll_sval_l8 is equal to SDIV[2:0].
10.5.11 APLL_CON_L1-7 Register
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ARM PLL Control (Performance Level -7) (APLL_CON_L7, R/W, Address = 0xE010_8604)
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ARM PLL Control (Performance Level -6) (APLL_CON_L6, R/W, Address = 0xE010_8608)
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ARM PLL Control (Performance Level -5) (APLL_CON_L5, R/W, Address = 0xE010_860C)
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ARM PLL Control (Performance Level -4) (APLL_CON_L4, R/W, Address = 0xE010_8610)
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ARM PLL Control (Performance Level -3) (APLL_CON_L3, R/W, Address = 0xE010_8614)
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ARM PLL Control (Performance Level -2) (APLL_CON_L2, R/W, Address = 0xE010_8618)
•
ARM PLL Control (Performance Level -1) (APLL_CON_L1, R/W, Address = 0xE010_861C)
Each register of APLL_CON_L1-7 configures P/M/S values for ARM PLL at IEM performance level from 1 to 7.
The description of each field is the same as that of APLL_CON_L8 register.
APLL_CON_L1-7 Bit Description Reset Value
Reserved [31:28] Reserved 0x0
Reserved [27:26] Reserved 00
apll_mval_l1-7 [25:16] M[9:0] value for ARM PLL at IEM performance level from 1 to 7 0x190
Reserved [15:14] Reserved 00
apll_pval_l1-7 [13:8] P[5:0] value for ARM PLL at IEM performance level from 1 to 7 0x03
Reserved [7:4] Reserved 0x0
Reserved [3] Reserved 0
apll_sval_l1-7 [2:0] S[2:0] value for ARM PLL at IEM performance level from 1 to 7 0x2