Samsung S5PC100, User Manual

Page: 259 / 1863

Power Management S5PC100 USER’S MANUAL (REV1.0)
2.4-60
OTHERS Bit Description Reset Value
kept in those power down mode. Then, you should
set this bit to 1 so that EPLL can be used normally.
0 = auto clear by h/w,
1 = de-assert EPLL_RET
Reserved [29] DO NOT CHANGE 0
MIPI_DPHY_EN
(1)
[28]
MIPI_DPHY Enable selection. This bit must be set
to 1 at the system initialization step before
MIPI_DPHY operation begins.
Caution: If MIPI_DPHY is not used in your
system, do not touch this bit.
0 = Disables
1 = Enables
0
Reserved [27] DO NOT CHANGE 0
DAC_EN
(1)
[26]
Digital-to-Analog Converter (DAC) IP Enable
selection. This bit must be set to 1 at the system
initialization step before DAC operation begins.
Caution: If DAC is not used in your system, do
not touch this bit.
0 = Disables
1 = Enables
0
L2RSTDISABLE [25]
Monitors the L2 hardware reset disable bit
0 = L2 valid RAM contents are reset by hardware
1 = L2 valid RAM contents are not reset by
hardware
0
PMU_INT_DISABLE [24]
Interrupt disabling by PMU. Auto-clear by H/W
Usage: Before entry to power down mode, you
should set this bit to 1 before issuing WFI
command. Interrupt to Cortex-A8 after issuing WFI
command should be masked since interrupt after
issuing WFI command malfunctions due to conflict
with power down process performed by H/W.
0 = Enables, 1 = Disables
0
STABLE_COUNTER TYPE [23]
Indicate OSC_STABLE, PWR_STABLE counter
type
0 = Exponential Scale, 1 = Set by SFR
0
SDMMC_IO_RET_RELEASE [22]
SDMMC_IO_RET_RELEASE. SDMMC_IO_RET is
retention control signal to SDMMC I/O pad. If you
want to release SDMMC_IO_RET, set this bit to 1.
After SDMMC_IO_RET is released, this bit will be
cleared to 0.
Usage: After wakeup from DEEP-IDLE (Top domain
off), DEEP-STOP (Top domain off) and SLEEP
mode, you should first set GPIO configurations as
the same ones before those power down mode
since GPIO configurations are not kept in those
power down mode. And then, you should set this bit
0