DISPLAY CONTROLLER
S5PC100 USER’S MANUAL (REV1.0)
9.1-4
3 FUNCTIONAL DESCRIPTION
3.1 BRIEF OF THE SUB-BLOCK
The display controller consists of a VSFR, VDMA, VPRCS, VTIME, and video clock generator. The VSFR has 107
programmable register sets and five 256x32-palette memories. This is used to configure the display controller.
The VDMA is a dedicated display DMA, which transfers the video data in frame memory to VPRCS. By using this
special DMA, displays the video data on the screen without CPU intervention. The VPRCS receives the video data
from VDMA and sends the video data through the data ports (RGB_VD, VEN_VD, V656_VD or SYS_VD ) to the
display device (LCD) after changing them into a suitable data format, for example 8-bit per pixel mode (8 BPP
Mode) or 16-bit per pixel mode (16 BPP Mode). The VTIME consists of programmable logic to support the
variable requirement of interface timing and rates commonly found in different LCD drivers. The VTIME block
generates RGB_VSYNC, RGB_HSYNC, RGB_VCLK, RGB_VDEN, VEN_VSYNC, VEN_HSYNC, VEN_FIELD,
VEN_HREF, V601CLK, V656CLK and SYS_CS0, SYS_CS1, SYS_WE and so on.
3.2 DATA FLOW
FIFO is present in the VDMA. If FIFO is empty or partially empty, VDMA requests data fetching from the frame
memory based on the burst memory transfer mode
.
The data transfer rate determines size of FIFO. The display
controller has five FIFOs because it needs to support the overlay window display mode. Use one FIFO for one
screen display mode. VPRCS fetches data through FIFO, which has a blending, scheduling function for the final
image data. VPRCS supports overlay function. This enables to overlay any image up to 5 window images whose
is smaller or same size can be blended with main window image with programmable alpha blending or color
(chroma) key function. Figure 9.1-2 shows the data flow from system bus to the output buffer. VDMA has 5 DMA
channels and 3 Local Input I/F. Color Space Conversion (CSC) block changes YCbCr (Local input only) data to
RGB data for the blending operation. Alpha values written in SFR determine the level of blending. Data from
Output buffer appears to the Video Data Port.
Summary of Contents for S5PC100
Page 21: ...MEMORY MAP S5PC100 USER S MANUAL REV1 0 1 2 2 ...
Page 34: ...S5PC100 USER S MANUAL REV1 0 BALL MAP SIZE POP 1 1 9 1 4 MCP CONNECTION ...
Page 49: ...IROM CODE S5PC100 USER S MANUAL REV1 0 2 6 4 12 Mhz 300 0 Mhz 100 0 Mhz 79 5 Mhz 20 6 Mhz ...
Page 174: ...CLOCK CONTROLLER S5PC100 USER S MANUAL REV1 0 2 3 24 Rs 0ohm Rf 1Mohm CL 10 35pF ...
Page 322: ...CORESIGHT S5PC100 USER S MANUAL REV1 0 3 2 4 Figure 3 2 2 S5PC100 Coresight Structure ...
Page 330: ...CORESIGHT S5PC100 USER S MANUAL REV1 0 3 2 12 Figure 3 2 7 ETB Block Diagram ...
Page 345: ...S5PC100 USER S MANUAL REV1 0 ASYNC BRIDGE 3 4 3 Figure 3 4 2 Asynchronous Bridge Components ...
Page 359: ...S5PC100 USER S MANUAL REV1 0 VECTORED INTERRUPT CONTROLLER 4 1 3 Figure 4 1 2 VIC Daisy Chain ...
Page 651: ...S5PC100 USER S MANUAL REV1 0 UART 8 1 27 Figure 8 1 10 UINTSP UINTP and UINTM block diagram ...
Page 652: ...UART S5PC100 USER S MANUAL REV1 0 8 1 28 NOTES ...
Page 743: ...S5PC100 USER S MANUAL REV1 0 MIPI HSI INTERFACE CONTROLLER 8 6 13 ...
Page 756: ...MIPI HSI INTERFACE CONTROLLER S5PC100 USER S MANUAL REV1 0 8 6 26 NOTES ...
Page 800: ...MIPI CSIS S5PC100 USER S MANUAL REV1 0 8 8 10 NOTES ...
Page 816: ...USB HOST CONTROLLER S5PC100 USER S MANUAL REV1 0 8 9 16 ...
Page 935: ...S5PC100 USER S MANUAL REV1 0 MODEM INTERFACE 8 11 13 NOTES ...
Page 1111: ...S5PC100 USER S MANUAL REV1 0 IMAGE ROTATOR 9 2 3 3 4 180 DEGREE ROTATION ...
Page 1112: ...IMAGE ROTATOR S5PC100 USER S MANUAL REV1 0 9 2 4 3 5 90 AND 270 DEGREE ROTATION ...
Page 1118: ...S5PC100 USER S MANUAL REV1 0 CAMERA INTERFACE 9 3 3 Figure 9 3 2 Camera Interface Overview ...
Page 1181: ...JPEG S5PC100 USER S MANUAL REV1 0 9 4 6 Figure 9 4 5 YCbCr4 2 2 Color Format ...
Page 1199: ...JPEG S5PC100 USER S MANUAL REV1 0 9 4 24 NOTES ...
Page 1245: ...3D ACCELERATOR S5PC100 USER S MANUAL REV1 0 9 6 18 ...
Page 1353: ...TVOUT VIDEO DAC S5PC100 USER S MANUAL REV1 0 9 7 32 ...
Page 1452: ...S5PC100 USER S MANUAL REV1 0 VIDEO PROCESSOR 9 8 43 NOTES ...
Page 1482: ...MIXER S5PC100 USER S MANUAL REV1 0 9 9 30 NOTES ...
Page 1664: ...S5PC100 USER S MANUAL REV1 0 I2S CONTROLLER 5 1CH 10 2 31 NOTES ...
Page 1701: ...AC97 CONTROLLER S5PC100 USER S MANUAL REV1 0 10 4 18 NOTES ...
Page 1731: ...SPDIF TRANSMITTER S5PC100 USER S MANUAL REV1 0 10 6 16 NOTES ...
Page 1744: ...S5PC100 USER S MANUAL REV1 0 ADC AND TOUCH SCREEN INTERFACE 10 7 13 NOTES ...
Page 1750: ...KEYPAD INTERFACE S5PC100 USER S MANUAL REV1 0 10 8 6 Figure 10 8 7 Keypad I F Block Diagram ...
Page 1755: ...S5PC100 USER S MANUAL REV1 0 KEYPAD INTERFACE 10 8 11 NOTES ...
Page 1779: ...SECURE DOMAIN MANAGER S5PC100 USER S MANUAL REV1 0 11 2 22 NOTES ...