Samsung S5PC100, User Manual

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SECURE DOMAIN MANAGER S5PC100 USER’S MANUAL (REV1.0)
11.2-10
3.2 SDM SECURE BOOT STATUS REGISTER (SDM_SECURE_BOOT_STS, R/W, ADDRESS =
0XF510_0004)
SDM_SECURE_BOOT_STS Bit Description Reset Value
SecureBootSts [0] Secure Boot Status Bit.
(0 = Secure Boot On-going,
1 = Secure Boot Done)
1'b0
Reserved [31:1] Reserved 31'h0
3.3 SDM STATUS REGISTER (SDM_STS, R, ADDRESS = 0XF510_0008)
SDM_STS Bit Description Reset Value
NCodeViolaCase1 [0] Normal Code Violation Case 1 Status Bit. 1'b0
NCodeViolaCase2 [1] Normal Code Violation Case 2 Status Bit. 1'b0
NCPABrFailCase1 [2] NC-PA Random Branch Fail Case 1 Status Bit. 1'b0
NCPABrFailCase2 [3] NC-PA Random Branch Fail Case 2 Status Bit. 1'b0
NCPABrFailCase3 [4] NC-PA Random Branch Fail Case 3 Status Bit. 1'b0
NCPABrFailCase4 [5] NC-PA Random Branch Fail Case 4 Status Bit. 1'b0
SCodeViolaDetect [6] Secure Code Violation Detect Status Bit. 1'b0
SDMSecureDomainOn [7] Secure Domain On Status Bit 1'b1
Reserved [31:8] Reserved 25'h0
3.4 SDM FIQ ON TO SBIT ON INTERVAL DELAY CYCLE COUNT REGISTER (SDM_FIQ2SBITON_DLY,
R/W, ADDRESS = 0XF510_000C)
SDM_FIQ2SBITON_DLY Bit Description Reset Value
Fiq2SBitOnDly [15:0] FIQ On to SBIT On Interval Delay Cycle Count Bit. 16'h0
Reserved [31:16] Reserved 16'h0
3.5 SDM IMZ OFF TO DMZ ENTRANCE INTERVAL DELAY CYCLE COUNT REGISTER
(SDM_IMZOFF2DMZ_DLY, R/W, ADDRESS = 0XF510_0010)
SDM_IMZOFF2DMZ_DLY Bit Description Reset Value
ImzOff2DmzDly [7:0] IMZ OFF to DMZ Entrance Interval Delay Cycle
Count Bit. 8'h0
Reserved [31:8] Reserved 24'h0
3.6 SDM DMZ ENTRANCE MODE 2 NC-PA RANDOM BRANCH START ADDRESS REGISTER
(SDM_RANDOM_BR_ADDR, R/W, ADDRESS = 0XF510_0014)
SDM_RANDOM_BR_ADDR Bit Description Reset Value