Samsung S5PC100, User Manual, Page: 1677 / 1863

S5PC100 USER’S MANUAL (REV1.0) I2S CONTROLLER(2CH)
10.3-13
8 REGISTER DESCRIPTION
8.1 REGISTER OVERVIEW
Table 10.3-3 Register Summary of I2S Interface
Register Address R/W Description Reset Value
I2SCON
0XF210_0000
0XF220_0000
R/W I2S Interface Control Register 0xE00
I2SMOD
0XF210_0004
0XF220_0004
R/W I2S Interface Mode Register 0x0
I2SFIC
0XF210_0008
0XF220_0008
R/W I2S Interface FIFO Control Register 0x0
I2SPSR
0XF210_000C
0XF220_000C
R/W I2S Interface Clock Divider Control Register 0x0
I2STXD
0XF210_0010
0XF220_0010
W I2S Interface Transmit Data Register 0x0
I2SRXD
0XF210_0014
0XF220_0014
R I2S Interface Receive Data Register 0x0
NOTE: All registers of I2S interface are accessible by word unit with STR/LDR instructions.
8.2 DETAILED DESCRIPTION
8.2.1 I2S interface control register (I2SCON, R/W, Address = 0XF210_0000, 0XF220_0000)
y
I2SCON1, R/W, Address = 0XF210_0000
y
I2SCON2, R/W, Address = 0XF220_0000
I2SCON Bit Description R/W Reset
Value
Reserved [31:20] Reserved R/W
FRXOFSTATUS [19] RX FIFO OverFlow Interrupt Status.This is used by
interrupt clear bit. If this is high, write ‘1’ to clear interrupt.
0 = Interrupt did not occurred.
1 = Interrupt occurred. R/W
FRXORINTEN [18] RX FIFO OverFlow Interrupt Enable
0 = Disables RXFIFO Under-run INT
1 = Enables RXFIFO Under-run INT R/W
FTXURSTATUS [17] TX FIFO under-run interrupt status. This is used by
interrupt clear bit. If this is high, write ‘1’ to clear the
interrupt.
0 = Interrupt did not occurred.
1 = Interrupt occurred. R/W
FTXURINTEN [16] TX FIFO Under-run Interrupt Enable
0 = Disables TXFIFO Under-run INT
1 = Enables TXFIFO Under-run INT R/W
Reserved [15:12] Reserved R/W