Samsung S5PC100, User Manual

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S5PC100 USER’S MANUAL (REV1.0) I2S CONTROLLER(5.1CH)
10.2-17
I2SCON Bit Description R/W Reset
Value
FRXORINTEN [25] RX FIFO OverFlow Interrupt Enable
0 = Disables RXFIFO Under-run INT
1 = Enables RXFIFO Under-run INT
R/W 0
FTXSUR
STATUS
[24] Secondary TX FIFO_S under-run interrupt status. This is
used by interrupt clear bit. If this is high, write ‘1’ to clear
the interrupt.
0 = Interrupt did not occur.
1 = Interrupt occurred.
R/W 0
FTXSURINTEN [23] Secondary TX FIFO_S Under-run Interrupt Enable
0 = Disables TXFIFO_S Under-run INT
1 = Enables TXFIFO_S Under-run INT
R/W 0
FTXSEMPT [22] Secondary TX FIFO_S empty Status Indication
0 = TX FIFO_S is not empty (Ready to transmit Data)
1= TX FIFO_S is empty (Not Ready to transmit Data)
R 0
FTXSFULL [21] Secondary TX FIFO_S full Status Indication
0 = TX FIFO_S is not full
1 = TX FIFO_S is full
R 0
TXSDMAPAUSE [20] Tx DMA operation for secondary TX FIFIO_S pause
command.
Note: If this bit is activated at any time, the
DMA request halts after current on-going DMA transfer is
complete.
0 = No pause DMA operation for TX FIFO_S
1 = Pause DMA operation for TX FIFO_S
R/W 0
Reserved [19] Reserved R 0
TXSDMACTIVE [18] Tx DMA active for secondary TX FIFO_S (start DMA
request).
Note: If this bit is set from high to low, the DMA
operation is forced to stop immediately.
0 = Inactive, 1 = Active
R/W 0
FTXURSTATUS [17] Primary TX FIFOx under-run interrupt status. This is used
by interrupt clear bit. If this is high, write ‘1’ to clear the
interrupt.
0 = Interrupt did not occur.
1= Interrupt occurred.
R/W 0
FTXURINTEN [16] Primary TX FIFOx Under-run Interrupt Enable
0 = Disables TXFIFO Under-run INT
1 = Enables TXFIFO Under-run INT
R/W 0
FTX2EMPT [15] Primary TX FIFO2 empty Status Indication
0 = TX FIFO2 is not empty (Ready to transmit Data)
1 = TX FIFO2 is empty (Not Ready to transmit Data)
R 0