Samsung S5PC100, User Manual, Page: 1696 / 1863

S5PC100 USER’S MANUAL (REV1.0) AC97 CONTROLLER
10.4-13
5 REGISTER DESCRIPTION
5.1 REGISTER OVERVIEW
Register Address R/W Description Reset Value
AC_GLBCTRL 0xF230_0000 R/W AC97 Global Control Register 0x00000000
AC_GLBSTAT 0xF230_0004 R AC97 Global Status Register 0x00000001
AC_CODEC_CMD 0xF230_0008 R/W AC97 Codec Command Register 0x00000000
AC_CODEC_STAT 0xF230_000C R AC97 Codec Status Register 0x00000000
AC_PCMADDR 0xF230_0010 R AC97 PCM Out/In Channel FIFO Address Register 0x00000000
AC_MICADDR 0xF230_0014 R AC97 Mic In Channel FIFO Address Register 0x00000000
AC_PCMDATA 0xF230_0018 R/W AC97 PCM Out/In Channel FIFO Data Register 0x00000000
AC_MICDATA 0xF230_001C R/W AC97 MIC In Channel FIFO Data Register 0x00000000
5.2 DETAILED DESCRIPTION
5.2.1 AC97 Global Control Register (AC_GLBCTRL, R/W, Address = 0xF230_0000)
This is the global register of the AC97 controller. There are interrupt control registers, DMA control registers, AC-
Link control register, data transmission control register and related reset control register.
AC_GLBCTRL Bit Description Reset Value
Reserved [31] Reserved 0
Codec ready interrupt clear [30] 1 = Interrupt clear (write only) 0
PCM out channel underrun
interrupt clear [29]
1 = Interrupt clear (write only) 0
PCM in channel overrun
interrupt clear [28]
1 = Interrupt clear (write only) 0
Mic in channel overrun
interrupt clear [27]
1 = Interrupt clear (write only) 0
PCM out channel threshold
interrupt clear [26]
1 = Interrupt clear (write only) 0
PCM in channel threshold
interrupt clear [25]
1 = Interrupt clear (write only) 0
MIC in channel threshold
interrupt clear [24]
1 = Interrupt clear (write only) 0
Reserved [23] Reserved 0
Codec ready interrupt enable [22] 0 = Disables 1 = Enables 0
PCM out channel underrun
interrupt enable [21] 0 = Disables
1 = Enables ( FIFO is empty)
0
PCM in channel overrun
interrupt enable [20] 0 = Disables
1 = Enables ( FIFO is full)
0