Infineon XDPP1100, Technical Reference Manual

Page: 15 / 562

User Manual 15 of 562 V 1.0
2021-08-25
XDPP1100 technical reference manual
Digital power controller
Voltage sense
Figure 3 VS module configuration for single-loop, dual-phase topology
VS configuration for dual-loop topology
This topology has two control loops and the VS module VS0 is configured in a similar way as the interleaved
topology. The simplified voltage module configuration is presented in
Figure 4 . The tasks of different VS
modules for this topology can be summarized as:
•
VS0 senses and processes Loop 0 output voltage through the input pins VSEN/VREF and computes the error
voltage for Loop 0 compensator (PID0) as well as providing the digitalized V
OUT
for telemetry and fault
processing, as described in detail in subsection 2.3.1 .
•
VS1 senses and processes Loop 0 V
RECT
or the input voltage through the input pins VRSEN/VRREF and
computes their digital representation for V
IN
telemetry, fault processing and Phase 2 current sensing and flux
balancing. V
RECT
processing is discussed in subsection 2.3.2 .
•
VS2 senses and processes Loop 1 output voltage through the input pins BVSEN/BVREF and computes the
error voltage for Loop 1 compensator (PID1) as well as providing the digitalized V
OUT
for telemetry and fault
processing, as described in detail in subsection 2.3.1 .
In the dual-loop configuration, if the V
OUT
of Loop 0 is the input voltage of Loop 1, the digitalized voltage from
VS0 can be also used for Loop 1 V
IN
telemetry, fault processing and Phase 2 current sensing. An example of such
configuration is post-buck topology, discussed briefly in subsection 6.2.2 .
Regarding the VS module VS1, it should be noted that if both loops (Loop 0 and Loop 1) share the input voltage,
the voltage information provided by the sense pins VRSEN/VRREF can be used also for Loop 1 V
IN
telemetry,
fault processing and current sensing. However, this information cannot be used for Loop 1 flux balance and so
dual-loop FB with flux balance on both loops is not supported.
VS0
VSEN
VREF
VSP0 PID0
Loop 0 V
OUT
telemetry,
faults
VS1
VRSEN
VRREF
VSP1
Loop 0 V
IN
telemetry,
faults
Phase 1 (ISEN)
current sense,
flux balance
Phase 2
(BISEN)
current sense,
flux balance
VS2
BVRSEN
BVRREF
VSP2
(V
OUT
)
(V
RECT
)
(BV
RECT
)