User Manual 487 of 562 V 1.0
2021-08-25
XDPP1100 technical reference manual
Digital power controller
Central processing unit subsystem
Register name Field name
Access Address
Bits
Description
GPIOIBE
INTEDGE
RW
6004_0408h
6005_0408h
[7:0]
The GPIOIBE register is the
interrupt both edges register. When
the corresponding bit in GPIOIS is
set to detect edges, bits set to high
in GPIOIBE configure the
corresponding pin to detect both
rising and falling edges, regardless
of the corresponding bit in the
GPIOIEV (interrupt event register).
Clearing a bit configures the pin to
be controlled by GPIOIEV. All bits
are cleared by a reset.
For each bit [x]:
0: GPIOx interrupt controlled by
GPIOIEV register
1: GPIOx interrupt on both edges
GPIOIEV
INTEVENT
RW
6004_040Ch
6005_040Ch
[7:0]
The GPIOIEV register is the
interrupt event register. Bits set to
high in GPIOIEV configure the
corresponding pin to detect rising
edges or high levels, depending on
the corresponding bit value in
GPIOIS. Clearing a bit configures
the pin to detect falling edges or
low levels, depending on the
corresponding bit value in GPIOIS.
All bits are cleared by a reset.
For each bit [x]:
0: GPIOx interrupt on rising edge or
high level based on GPIOIS
1: GPIOx interrupt on falling edge or
low level based on GPIOIS
GPIOIE
INTENA
RW
6004_0410h
6005_0410h
[7:0]
The GPIOIE register is the interrupt
enable register. Bits set to high in
GPIOIE allow the corresponding
pins to trigger their individual
interrupts and the combined
GPIOINTR line. Clearing a bit
disables interrupt triggering on that
pin. All bits are cleared by a reset.
For each bit [x]:
0: GPIOx interrupt is disabled
1: GPIOx interrupt is enabled
GPIORIS
INTRAW
R
6004_0414h
6005_0414h
[7:0]
The GPIORIS register is the raw
interrupt status register. Bits read
high in GPIORIS reflect the status of
interrupt trigger conditions
