User Manual 393 of 562 V 1.0
2021-08-25
XDPP1100 technical reference manual
Digital power controller
Central processing unit subsystem
Address
Size
Description
1003_FFFFh
1004_0000h
5001_FFFFh
5002_0000h
OTP configuration registers
5002_0078h
15.4.3.2
OTP configuration interface
It is possible for FW to configure OTP block behavior, or access the OTP macro indirectly or perform a specific
test procedure (BIST) using the registers mapped on APB space starting from 5002_0000h.
OTP macro indirect access allows FW to perform specific commands like a single 128-bit read of a defined
address, a single program of an OTP line (128 bits), a configuration registers change (MRA-MRB-MR) or a specific
transaction (precharge, compare) execution.
Indirect access is mainly useful to program OTP without stalling the microcontroller for the entire duration of
the write. An OTP line (128 bits) program can take from 50 µs up to 1600 µs in case of correct programming. In
case there are any reading mismatches during the verify operation, unsuccessful bits are written again using a
soaking pulse (500 µs) and for a maximum of 16 attempts.
Waiting for an instruction completion can be achieved with two different methods:
•
Polling: looping on the APB_BUSY flag on the STAT register, waiting to find it at zero (operation completed)
•
Interrupt: arming the instruction done interrupt (MASK_INSTR_DONE = 1b1 on INT_MASK register) and
waiting until the OTP shell triggers an interrupt, then verifying that the right interrupt occurred (checking
INSTR_DONE field set on INT_ACTIVE register) and clearing it (write into INT_ACTIVE_CLR)
OTP module configuration is based on a set of registers that can control specific timings such as the duration of
the READ pulse, the duration of the programming pulse or the duration of power-up delay and reset hold-time.
They can also influence some static behaviors, defining values for MRA-MRB-MR to be used during a READ, a
READ1 (read after programming) or READ2 (read after soaking).
15.4.3.3
Indirect OTP access
The basic registers to perform an OTP indirect access are INSTR, EXEC and STAT.
Register INSTR contains two fields:
•
OTP_ADDR, which selects the OTP row (address alignment is 128-bit data)
•
INSTRUCTION, which select the specific operation that has to be performed
Register EXEC is a write-only register; what is written on this register is not meaningful, but a write operation
itself triggers the indirect access to start. Reading from this register always returns to zero, and has no other
effects.
An instruction completion is monitored on the STAT register APB_BUSY field. APB_BUSY high signals that an
operation is ongoing; it is not possible to start another operation when APB_BUSY is high. It is also not possible
to access OTP AHB direct space while APB_BUSY is high, in case an AHB bus error is triggered to the
microcontroller (HARDFAULT).
Supported instructions are described in
