User Manual 484 of 562 V 1.0
2021-08-25
XDPP1100 technical reference manual
Digital power controller
Central processing unit subsystem
Register name Field name
Access Address
Bits
Description
0: dma_err is low
1: dma_err is high
On WRITE:
0: No effect, status of dma_err is
unchanged
1: Sets dma_err low
RIS
DMA_CH_INT_STAT
US
R
5000_1000h [15:0]
Raw DMA channel interrupt status
prior to masking by SMA_CH_MASK.
For each bit [x]:
0: No interrupt pending on DMA
channel x
1: Interrupt pending on DMA
channel x
RIS
DMA_ERR_INT_STA
TUS
R
5000_1000h [31]
Raw DMA error interrupt status
prior to masking by
SMA_ERR_MASK.
0: No error interrupt pending
1: Error interrupt pending
IMSC
DMA_CH_MSK
RW
5000_1004h [15:0]
DMA channel interrupt mask.
For each bit [x]:
0: DMA channel x interrupt disabled
0: DMA channel x interrupt enabled
IMSC
DMA_ERR_MSK
RW
5000_1004h [31]
Mask bit for DMA error interrupt.
0: DMA error interrupt disabled
1: DMA error interrupt enabled
MIS
DMA_CH_INT
R
5000_1008h [15:0]
DMA channel interrupt status after
masking by SMA_CH_MASK.
For each bit [x]:
0: DMA channel x interrupt disabled
or not pending
1: DMA channel x interrupt enabled
and pending
MIS
DMA_ERR_INT
R
5000_1008h [31]
DMA error interrupt status after
masking by SMA_ERR_MASK.
0: DMA error interrupt disabled or
not pending
1: DMA error interrupt enabled and
pending
ICR
DMA_CH_INT_CLR
W
5000_100Ch [15:0]
DMA channel interrupts clear.
For each bit [x]:
0: No change to DMA channel x
interrupt
1: Clear DMA channel x interrupt
ICR
DMA_ERR_INT_CLR W
5000_100Ch [31]
DMA error interrupt clear.
