User Manual
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V 1.0
2021-08-25
XDPP1100 technical reference manual
Digital power controller
Digital pulse width modulator
Peripheral Field name
Access Address
Bits
Description
LSB = 1.25 ns, range = 0.0 to
318.75 ns
pwm
pwm1_df
RW
7000_2C54h [15:8]
PWM1 falling edge delay (dead)
time from t1 or t2. Mapping of the
falling edge to t1 or t2 defined by
pwm1_fall_sel. In order to
synchronously update all dead
times simultaneously, an update to
any dead time register only
becomes effective after
7000_2C80h (pwm12_dr,
pwm12_df) is written.
Computed by FW from PMBus
command as follows:
pwm1_df[7:0] =
PWM_DEADTIME[7:0]
LSB = 1.25 ns, range = 0.0 to
318.75 ns
pwm
pwm2_dr
RW
7000_2C58h [7:0]
PWM2 rising edge delay (dead) time
from t1 or t2. Mapping of the rising
edge to t1 or t2 defined by
pwm2_rise_sel. In order to
synchronously update all pwmX_dr
and pwmX_df times
simultaneously, an update to any
dead time register only becomes
effective after 7000_2C80h
(pwm12_dr, pwm12_df) is written.
Computed by FW from PMBus
command as follows:
pwm2_dr[7:0] =
PWM_DEADTIME[31:@4]
LSB = 1.25 ns, range = 0.0 to
318.75 ns
pwm
pwm2_df
RW
7000_2C58h [15:8]
PWM2 falling edge delay (dead)
time from t1 or t2. Mapping of the
falling edge to t1 or t2 defined by
pwm2_fall_sel. In order to
synchronously update all dead
times simultaneously, an update to
any dead time register only
becomes effective after
7000_2C80h (pwm12_dr,
pwm12_df) is written.
Computed by FW from PMBus
command as follows:
pwm2_df[7:0] =
PWM_DEADTIME[23:!6]
