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Infineon XDPP1100, Technical Reference Manual

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User Manual                                                                                                            528 of 562                                                                                                                      V 1.0  
 

 

2021-08-25 

XDPP1100 technical reference manual 

Digital power controller 

Central processing unit subsystem  

 

 

Table 110

 

Status register codes 

Code 

Status 

00h 

Bus error 

08h 

START condition transmitted 

10h 

Repeated START condition transmitted 

18h 

A Write bit transmitted, ACK received 

20h 

A Write bit transmitted, ACK not received 

28h 

Data byte transmitted in master mode, ACK received 

30h 

Data byte transmitted in master mode, ACK not received 

38h 

Arbitration lost in address or data byte 

40h 

A Read bit transmitted, ACK received 

48h 

A Read bit transmitted, ACK not received 

50h 

Data byte received in master mode, ACK received 

58h 

Data byte received in master mode, ACK not received 

60h 

Slave a Write bit received, ACK transmitted 

68h 

Arbitration lost in address as master, slave a Write bit received, ACK 
transmitted 

70h 

General Call address received, ACK transmitted 

78h 

Arbitration lost in address as master, General Call address receved, ACK transmitter 

80h 

Data byte received after slave address received, ACK transmitted 

88h 

Data byte received after slave address received, not ACK transmitted 

90h 

Data byte received after General Call received, ACK transmitted 

98h 

Data byte received after General Call received, not ACK transmitted 

A0h 

STOP or repeated START condition received in slave mode 

A8h 

Slave a Read bit received, ACK transmitted 

B0h 

Arbitration lost in address as master, slave a Read bit received, ACK 
transmitted 

B8h 

Data byte transmitted in slave mode, ACK received 

C0h 

Data byte transmitted in slave mode, ACK not received 

C8h 

Last byte transmitted in slave mode, ACK received 

D0h 

Second Address byte + Write bit transmitted, ACK received 

D8h 

Second Address byte + Write bit transmitted, ACK not received 

E0h 

Unused 

E8h 

Unused 

F0h 

Unused 

F8h 

No relevant status information, IFLG = 0 

 

 

 

Summary of Contents for XDPP1100

Page 1: ...solated digital brick module designers telecom and server power system designers Table of contents About this document 1 Table of contents 1 1 Introduction 7 1 1 Applications 7 1 2 Control registers a...

Page 2: ...e ADC 66 4 2 TS input mux and sequencing 66 4 3 Telemetry sense current DAC 69 4 4 Telemetry sense processor 69 4 4 1 Sequencer 70 4 4 2 Gain and offset correction 70 4 4 3 VIN computation 71 4 4 4 In...

Page 3: ...eak current mode control 139 7 3 3 Maximum and minimum pulse width enforcement 140 7 3 4 Forced duty cycle T1 T2 141 7 4 Burst mode 142 7 5 Fast transient response 143 7 5 1 Fast transient response lo...

Page 4: ...s commands 271 10 Current sharing ISHARE 285 10 1 Current sharing circuit 285 10 2 Current sharing PI filter 287 10 3 Current sharing FW override 288 10 4 Current sharing pin DAC and ADC configuration...

Page 5: ...3 Reset generator unit 379 15 3 3 1 Reset sources 380 15 3 3 2 Software power down 381 15 3 3 3 Software reset 382 15 3 3 4 RGU registers 382 15 4 Memory 390 15 4 1 Read only memory 390 15 4 2 Random...

Page 6: ...ransaction 505 15 10 3 4 PMBus ARA command 508 15 10 4 PMBus registers 509 15 11 I2 C module 527 15 11 1 I2 C operating modes 527 15 11 1 1 Status information 527 15 11 1 2 Master transmit 529 15 11 1...

Page 7: ...tap CT secondary Half bridge HB primary with full wave or CT secondary Buck Boost Buck boost Unregulated LLC Independent application notes provide more details regarding certain product features and a...

Page 8: ...o as Loop 0 and Loop 1 Loop 0 is associated with voltage sense VS input pair VSEN VREF as well as HW blocks Voltage Control 0 PID 0 and typically PWM ramp0 PMBus commands relevant to Loop 0 are found...

Page 9: ...tance amplifier OTP One time programmable OV Overvoltage PCB Printed circuit board PCL Peak current limiting PCMC Peak current mode control PI Proportional integral PID Proportional integral derivativ...

Page 10: ...vative term of the compensator KFP Filter coefficient KI Integral term of thecompensator KP Proportional term of the compensator L Inductor Llk Transformer leakage inductance Lm Transformer magnetizin...

Page 11: ...nt format with x and y defined as described above for the unsigned case Figure 1 illustrates the x and y meanings Figure 1 Binary number format x y definitions Some unsigned and signed number examples...

Page 12: ...ctionalities are described in Chapters 5 6 and 7 focusing on the following topics Chapter 5 illustrates how the control voltage is set for the feedback system as well as the droop voltage computation...

Page 13: ...REF_BVRREF for VOUT sensing in dual loop operation or VRECT sensing for interleaved topology Typical connection of VSEN VREF and VRSEN VRREF in a FB converter with CT rectifier for VOUT and VRECT sens...

Page 14: ...tion for interleaved single loop topology This topology has two phases Phase 1 and Phase 2 and one control loop Simplified voltage module configuration for this topology is shown in Figure 3 The tasks...

Page 15: ...d in subsection 2 3 2 VS2 senses and processes Loop 1 output voltage through the input pins BVSEN BVREF and computes the error voltage for Loop 1 compensator PID1 as well as providing the digitalized...

Page 16: ...eceives the VSADC output as its input and it provides a digital representation of either VOUT VRECT or VIN depending which voltage is being sensed Figure 6 shows the VS module block diagram while VREC...

Page 17: ...nverter This section discusses the VSADC and its relevant submodules in more detail It receives the sensed voltage as its input and its output is the digitized version of the same voltage This ADC con...

Page 18: ...ain objective of the FEC is to reduce the effects of Temperature Stress Lifetime induced offset drift in the AFE It compares the differential voltages at the input and output of the AFE and compensate...

Page 19: ...e actually used The ADC tracking loop integrator step size is programmable via registers vsX_step_en enables user definable step size control vsX_step sets a fixed integrator step size The X in the re...

Page 20: ...el or vsp2_vrs_sel depending on which input pins are used to sense the voltage A simplified block diagram of the VOUT processing function and error computing is shown in Figure 9 Figure 9 Simplified b...

Page 21: ...re 10 Compared to the VOUT VRECT processing has many more additional features Figure 10 Simplified block diagram of the rectified voltage processing The VRECT VSP provides three outputs for further fu...

Page 22: ...The rising edge of the rectified voltage is detected via a comparator vrs_comp It is clocked at 200 MHz and has a programmable threshold via register vrs_cmp_ref_sel When VRECT exceeds this threshold...

Page 23: ...p_wdt_thr greater than the latest expected arrival time of the VRECT pulse at VRSEN as measured from the PWM output Set the tracking start timer count vrs_track_start_thr to a value at minimum 250 ns...

Page 24: ...n and odd The XDPP1100 measures and stores the PWM signals separately as shown in Figure 13 Figure 13 VSP VRECT even and odd cycle timing As previously discussed the even and odd VRECT outputs are uti...

Page 25: ...ut pre bias i e output ramps from 0 V the initial PWM pulses are narrower than the tracking start timer threshold During this time the VRECT tracking ADC continues to output the initial voltage set by...

Page 26: ...s a default feature the sensed rectified voltage is sampled once per cycle at the PWM falling edge Thus the current VRECT value does not contribute to the PWM turn off via FF function An alternate sam...

Page 27: ...comparator is clocked on a 5 ns clock period leading to an overall counter accuracy result of 10 ns In addition to the delay counters a third counter measures the rectification voltage pulse width as...

Page 28: ...ary side input voltage VIN directly This is obtained by Selecting the input voltage source VRSEN or BVRSEN with register tlm_vin_src_sel Selecting general purpose ADC mode 0 via register vsp1_vrs_sel...

Page 29: ..._BVRSEN tracking loop step size control 0 Automatic step size recommended for VRECT sense 1 Use vs2_step 2 0 recommended for VOUT VIN sense vsen vsp_verrn_clamp_thresh RW 7000_0800h VSEN 7000_1000h BV...

Page 30: ...wnstream processing vsen vsp_vout_fs R 7000_0810h VSEN 7000_0C10h VRSEN 7000_1010h BVSEN 11 0 Gain and offset trimmed VSADC output LSB 1 25 mV range 0 0 to 2 1 V common vrs_cmp_wdt_thr RW 7000_3018h 9...

Page 31: ...odd used for non bridge topologies 1 vrect_even vrect_odd 2 used for bridge topologies common vsp1_vrs_sel RW 7000_3018h 21 VRSEN input ADC rectification VS VRS mode select 0 General purpose ADC mode...

Page 32: ...ted otherwise the slow filter output is selected 0 8 ADC codes 1 16 ADC codes common vrs_bypass_slow_lpf RW 7000_3018h 29 VRS slow filter bypass control Shared by VRSEN and BVRSEN paths 0 Filter not b...

Page 33: ...voltage on the even half cycle LSB 1 25 mV range 0 0 to 2 1 V common vsp1_vrs_vrect_odd R 7000_3038h 11 0 Measured VRSEN rectification voltage on the odd half cycle LSB 1 25 mV range 0 0 to 2 1 V comm...

Page 34: ...to 1025 ns common vsp1_srr_b4_vrsf R 7000_3064h 22 Status flag indicating VRSEN detected SR FET rising edge before VRS comp falling edge i e no dead time on PWM falling edge on previous cycle 0 SR FET...

Page 35: ...ising edge before VRS comp falling edge i e no dead time on PWM falling edge on previous cycle 0 SR FET rising edge after VRS comp falling edge 1 SR FET rising edge before VRS comp falling edge common...

Page 36: ...DPP1100 technical reference manual Digital power controller Voltage sense Peripheral Field name Access Address Bits Description when sharing Loop 0 VRECT sense 6 VRSEN non pulsed primary VIN sense 7 B...

Page 37: ...ary side or primary side current sense In a single loop system for PCMC the ISEN IREF pin pair must be connected to the current being controlled IOUT for secondary side PCMC and IIN for primary side P...

Page 38: ...ed block diagram of these current sense modules is shown in Figure 19 Each module consists of three submodules IS AFE Current estimator CE Current sense processor ISP Submodules IS AFE and CE form the...

Page 39: ...ing methods Sensing method Advantages Disadvantages Applications Shunt resistor Most common solution Simple BOM cost Additional power dissipation All applications PCB trace No additional bill of mater...

Page 40: ...as the current sense voltage is referenced to the supported reference levels GND or 1 2 V as will be described later in this chapter The main requirement for using the integrated current sensing of I...

Page 41: ...reference level for current sense voltage The X in the register name denotes 1 for ISEN IREF and 2 for BISEN BIREF Table 4 IS AFE gain modes isenX_gain_mode ADC LSB V IREF Gain mode 0 Reserved not to...

Page 42: ...Current transformer Low gain mode 2 Non isolated buck with IPS Integrated current sense Low gain mode 3 The second sub block the 9 25 bit DAC has 640 quantization levels However some of the bits are u...

Page 43: ...e of the PWM pulse Therefore the PWM state is critical to both slope estimation and error tracking because it is used to determine the equation for voltage across the inductor in order to estimate the...

Page 44: ...n bridge topologies there are two on off states per switching cycle therefore mask0 defines the first on off state and mask1 the second In non bridge topologies e g ACF buck mask1 is typically set to...

Page 45: ...ifying the PWM state for current reconstruction Table 8 describes the relevant programming for this topology Figure 23 ACF topology FET naming Table 8 ACF PWM state programming example FET PWM output...

Page 46: ...nd other bit fields to 0 in ceX_off_mask1 ceX_off_mask1 004h SR2 PWM4 Set bit field values corresponding PWM4 to 1 and other bit fields to 0 in ceX_off_mask0 ceX_off_mask0 008h d HBCD topology The HBC...

Page 47: ...itches SR2 and SR4 define the inductor off time for the first half switching cycle and correspondingly SR1 and SR3 define the second half Table 11 describes the relevant programming for this topology...

Page 48: ...on whether the current is sensed on the primary or secondary side and on the topology The relevant parameters for slope specification are described below after inductor voltage definition Inductor vo...

Page 49: ...ologies e g buck forward ACF HB FB with secondary side current sense can be set through register ceX_kslope_didv The normalized current slope is defined according to Equation 3 3 where the kslope_real...

Page 50: ...ent sense The primary side and secondary side current waveforms are different as illustrated in Figure 28 The continuous secondary side current can be sensed during any PWM state However the primary s...

Page 51: ...th the ISEN and BISEN current sense paths simultaneously It should be noted that the registers ce0_ps_current_emu and ce1_ps_current_emu also need to be configured to indicate which input pin pair ISE...

Page 52: ...racking output is blanked to 0 3 2 2 4 Trace inductance of the PCB current sensing The PCB trace resistance can be used for current sensing In the ideal case the parasitic inductance would be zero and...

Page 53: ...are as follows CE output synth_i represented in ADC codes is multiplied by the PMBus command MFR_IOUT_APC APC refers to amps per code converting the code based word synth_i into a digital representati...

Page 54: ...ive current limiting The negative current limiting NCL block is illustrated in Figure 30 and it compares Instantaneous phase current prior to cycle averaging NCL threshold ispX_ncl_thresh If the phase...

Page 55: ...15 Current sense tracking error threshold ispX_err_ration_sel Error threshold Error ratio Min samples to fault Min time to fault s 0 4 4 36 11 1 percent 124 4 96 1 8 8 40 20 0 percent 248 9 92 2 12 1...

Page 56: ...select Defines LSB weight of ISEN2 ADC Also defines expected reference voltage level on IREF2 BIREF 0 Reserved 1 LSB 100 V BIREF level GND 2 LSB 1 45 mV BIREF level GND 3 LSB 1 45 mV BIREF level 1 2 V...

Page 57: ...t sense ce_kslope_didv 1 0 V 10 ns LOUT nH APC A For primary current sense ce_kslope_didv 1 0 V 10 ns Nturn LOUT nH APC A LSB 2 13 V V range 0 0 to 0 25 V V isen ce_pwmwin_dly RW 7000_2400h ISEN 7000_...

Page 58: ...ary topology set ce_on_mask0 bits corresponding to ACF Q1 HB Q1 FB Q1 Q3 Buck HSFET isen ce_on_mask1 RW 7000_2404h ISEN 7000_2804h BISEN 23 12 Defines the on state of the CE with respect to the PWM ou...

Page 59: ...nt I1 APC amps per code defined by MFR_IOUT_APC ce_dt_l_slope round 2 14 L0 L1 1 APC I1 Example L0 470 nH L1 420 nH at 50 A APC 0 25 ce_dt_l_slope round 2 14 470 420 1 0 25 50 10 LSB 2 14 Vs HA range...

Page 60: ...put inductor current is in its downward slope cycle e g primary FETs off secondary FETs in a bridge topology In bridge topologies there are two off states per switching cycle ce_off_mask0 defines the...

Page 61: ...fault detection LSB 1 A range 0 to 255 A isen isp_ncl_thresh RW 7000_240Ch ISEN 7000_280Ch BISEN 15 8 Inductor NCL fault threshold The NCL threshold is compared against the instantaneous phase curren...

Page 62: ...former magnetizing inductance Lm current sense slope normalized to code samples at 1 0 V Only used for primary side current sense ce_kslope_lm 1 0 V 10 ns Nturn Lm nH APC A LSB 2 13 V V range 0 0 to 0...

Page 63: ...topology RW 7000_2410h ISEN 7000_2810h BISEN 28 27 Current emulator topology select Defines the inductor voltage equations for VON VOFF 0 Buck ACF HB FB 1 Boost 2 3 Buck boost isen isp_fsw_sync_sel RW...

Page 64: ...1 mA range 0 0 to 3 998 A isen isp_ioffset RW 7000_2418h ISEN 7000_2818h BISEN 7 0 Phase current offset Computed by FW from PMBus command as follows isp_offset IOUT_CAL_OFFSET LSB 0 125 A range 16 to...

Page 65: ...technical reference manual Digital power controller Current sense IS Command name Access Length Address Bits Description MFR_IOUT_APC RW Word EAh 15 0 Current sense APC Linear11 format with suggested...

Page 66: ...ctions introduce these submodels in more detail Figure 31 TS block diagram 4 1 Telemetry sense ADC The TSADC is a successive approximation ADC and it has the following specifications 9 bits 1 Msps con...

Page 67: ...2 4 PRISEN IMON PRISEN ATSEN PRISEN IMON PRISEN BTSEN 5 PRISEN XADDR1 PRISEN ATSEN PRISEN MUX1 PRISEN BTSEN 6 PRISEN XADDR1 IMON ATSEN PRISEN MUX1 IMON BTSEN 7 PRISEN XADDR1 IMON ATSEN PRISEN MUX1 XAD...

Page 68: ...DAC A TSEN o atsen_meas_en enables the TSEN input for ADC o ts_tsidac_antc_sel enables the TSEN 100 A current source when used with an NTC or PTC sense element BTSEN o btsen_meas_en enables the BTSEN...

Page 69: ...sharing additional resolution up to 10 bits total is created through dithering It also requires a capacitor in parallel to the resistor from IMON to GND 4 4 Telemetry sense processor The TSP is shown...

Page 70: ...es the TSADC output into individual channel ADC outputs These outputs are then aligned to the associated update signal generated in the sequencer and they are accessible through the following read onl...

Page 71: ...c computation of VIN from the PRISEN input Figure 35 VIN computation 4 4 4 Internal temperature ITSEN computation The XDPP1100 internal temperature is computed from ADC codes based on the following re...

Page 72: ...submodule of the TSP is X valent XV measurement providing a HW controlled method to measure and decode the resistor programmed pinset on the XADDR1 two pins The XV measurement is enabled through the r...

Page 73: ...rc Registers ts_tsidac_xv1_sel and ts_tsidac_xv2_sel enable IDAC output on XADDR1 and XADDR2 respectively The unfiltered ADC output is available on read only registers xv1_adc and xv2_adc whereas the...

Page 74: ...y ts_muxmode and tx_muxctrl2 When disabled no BTSEN measurement will occur even if selected by ts_muxmode and ts_muxctrl2 0 Disabled 1 Enabled tsen itsen_meas_en RW 7000_4C00h 4 TSADC ITSEN measuremen...

Page 75: ...7000_4C00h 11 XADDR2 output current DAC enable This current DAC is enabled by FW during the XADDR2 resistor pinset measurement The current DAC should be disabled otherwise 0 Disabled 1 Enabled tsen xv...

Page 76: ...ts_muxmode RW 7000_4C00h 22 20 TSADC input sequence control When bit 2 is 0 the TSADC input is entirely determined by the settings of ts_muxctrl1 and ts_muxctrl2 When bit 2 is 1 MUX2 auto sequences it...

Page 77: ...0 24805 V V tsen vin_pwl_slope RW 7000_4C0Ch 11 0 TSADC PRISEN input voltage VIN piecewise linear slope term VIN computed as VIN ADC vin_pwl_slope vin_trim LSB 2 14 V code range 0 to 0 24994 V code ts...

Page 78: ...w pass filtered ITSEN measurement Filter BW fixed at approximately 950 Hz when the ITSEN measurement is enabled via ts_muxmode and ts_muxctrl1 LSB 0 125 C range 256 to 255 875 C tlmcom tlm_xaddr1_pins...

Page 79: ...User Manual 79 of 562 V 1 0 2021 08 25 XDPP1100 technical reference manual Digital power controller Telemetry sense Peripheral Field name Access Address Bits Description output 1 Use idac_fw_frc...

Page 80: ...e control module are defined relative to the sense voltage VSEN or BVSEN after the output voltage resistor divider scaling Multi segment droop High BW LPF U12 3 vc_vavp_kfp 4 0 vcontrol_ramp 14 0 U12...

Page 81: ...oltage during soft start and shutdown as well as in response to commanded output voltage changes For example During soft start from 0 V or pre bias voltage to VOUT_COMMAND at the TON_RISE rate During...

Page 82: ...ns During soft start Equation 5 3 During shutdown Equation 5 4 During regulation Equation 5 5 _ _ 62 5 222 _ _ _ _ 1 5 3 _ _ 62 5 222 _ _ _ _ 1 5 4 _ _ 62 5 219 _ _ _ _ 1 5 5 The programmable slew rat...

Page 83: ...vcontrol_at_target_window which is an internal signal that indicates vcontrol_ramp is within a window around the target voltage The target voltage window is defined by parameter vc_vramp_target_window...

Page 84: ...tive current segment allows the negative current droop to be independently programmed according to the system requirements 5 4 1 Droop voltage computation The droop resistance parameters are computed...

Page 85: ...elta In addition the FW can completely override the measured IOUT for use in the droop computation through registers vc_vavp_itot_uc and vc_vavp_itot_uc_sel In order to determine in which current segm...

Page 86: ...p kfp kfp_real F3db kHz vc_vavp_kfp kfp kfp_real F3db kHz 0 4 0 0002 0 97 16 64 0 0039 15 60 1 5 0 0003 1 21 17 80 0 0049 19 52 2 6 0 0004 1 46 18 96 0 0059 23 45 3 7 0 0004 1 70 19 112 0 0068 27 39 4...

Page 87: ...IOUT 5 5 Output summation and clamping The final Vcontrol output is a sum of vcontrol_ramp which is the output of the ramp generator vcontrol_vavp which results from the droop computations fault_iout_...

Page 88: ...itive droop refers to decreasing voltage with positive IOUT negative droop refers to increasing voltage with negative IOUT LSB 20 mV range 0 0 to 2 54 V vcontrol vc_vavp_clamp_pos RW 7000_1400h vcontr...

Page 89: ...ERATION setting LSB 0 15625 mV range 0 0 to 2 1 V vcontrol vc_vramp_target_windo w RW 7000_1404h vcontrol0 7000_1804h vcontrol1 22 15 Ramp target window used to define interrupt prior to reaching ramp...

Page 90: ...ning the time between 1 25 mV steps referenced to VSEN Computed by FW from PMBus commands as follows Using VOUT_TRANSITION_RATE tstep U18 2 1 25 mV 0 02 s 2 3 2 16 VOUT_TRANSITION_RATE U6 3 VOUT_SCALE...

Page 91: ...CALE_LOOP U0 16 2 y 2 16 7 where y 1 LINEAR11 exponent of VOUT_DROOP LSB 7 8125 range 0 0 to 15 992 m vcontrol vc_vcontrol_delta RW 7000_1414h vcontrol0 7000_1814h vcontrol1 12 0 Vcontrol output offse...

Page 92: ..._RDROOP_RLL_NEG Ux y VOUT_SCALE_LOOP U0 16 2 y 2 16 7 where y 1 LINEAR11 exponent of MFR_RDROOP_RLL_NEG LSB 7 8125 range 0 0 to 15 9922 m vcontrol vc_vcontrol_irq_en RW 7000_1420h vcontrol0 7000_1820h...

Page 93: ...ntrol1 7 Status flag indicating the Vcontrol ramp is slewing in a rising direction 0 Ramp not rising i e falling or at target 1 Ramp rising vcontrol vc_vcontrol R 7000_1428h vcontrol0 7000_1828h vcont...

Page 94: ...ITHR_SEG2 UX Y 2 Y where Y LINEAR11 exponent of MFR_RDROOP_ITHR_SEG2 LSB 0 5 A range 0 0 to 255 5 A vcontrol vc_vavp_ithr_seg3 RW 7000_1438h vcontrol0 7000_1838h vcontrol1 8 0 When load current is abo...

Page 95: ...tage command value It is most typically used by the end user to trim the output voltage at the time the PMBus device is assembled into the end user s system Format is SLINEAR16 with the exponent defin...

Page 96: ...e 7 to 2 VOUT_SCALE_LOOP RW Word 29h 15 0 Defines the VOUT sense resistor divider ratio Vsense VOUT Format is DIRECT U0 16 VOUT_SCALE_LOOP INT 2 16 Vsense VOUT VOUT_MIN RW Word 2Bh 15 0 Sets a lower l...

Page 97: ...R_SEG3 Format is LINEAR11 79 64 MFR_RDROOP_RLL_NEG Sets the VOUT droop rate in mV A when IOUT is negative Format is LINEAR11 95 80 MFR_RDROOP_ITHR_SEG2 Defines the output current threshold at which to...

Page 98: ...are described in more detail in the sections below Figure 45 Functional block diagram of the compensator 6 1 Compensation filter This section describes the proportional integral derivative PID filter...

Page 99: ...plemented as shown in Figure 47 and it consists of One input the error voltage Verrn Two outputs verrn_filt and verrn_slope The verrn_filt is the low pass filtered version of the computed error Verrn...

Page 100: ...6 5 The location of the first high frequency pole can be computed as provided in Equation 6 6 using the previously computed real number representation for KFP1 1 1 2 1_ 1 1_ 1 50 6 6 Note that pid_kfp...

Page 101: ...215 36 192 0 0234 37 208 0 0254 38 224 0 0273 39 240 0 0293 40 256 0 0313 41 288 0 0352 42 320 0 0391 43 352 0 0430 44 384 0 0469 45 416 0 0508 46 448 0 0547 47 480 0 0586 48 512 0 0625 49 576 0 0703...

Page 102: ...ive term D_term is computed based on verrn_slope the derivative of the filtered error signal The p_term and d_term are added to produce the pd_term which is downstream processed by the post filter The...

Page 103: ...represent the exponent and the lower three bits represent the mantissa The integer and real number representations of KP are computed as provided in Equations 6 7 to 6 10 _ _ 5 3 6 7 _ _ 2 0 6 8 8 _...

Page 104: ...15 30 0 0005 16 32 0 0005 17 36 0 0005 18 40 0 0006 19 44 0 0007 20 48 0 0007 21 52 0 0008 22 56 0 0009 23 60 0 0009 24 64 0 0010 25 72 0 0011 26 80 0 0012 27 88 0 0013 28 96 0 0015 29 104 0 0016 30 1...

Page 105: ...60 1536 0 0234 61 1664 0 0254 62 1792 0 0273 63 1920 0 0293 Correspondingly the integer and real number representations of KI are computed as given in Equations 6 11 to 6 14 Table 31 shows the corres...

Page 106: ...6E 07 20 48 7 15E 07 21 52 7 75E 07 22 56 8 34E 07 23 60 8 94E 07 24 64 9 54E 07 25 72 1 07E 06 26 80 1 19E 06 27 88 1 31E 06 28 96 1 43E 06 29 104 1 55E 06 30 112 1 67E 06 31 120 1 79E 06 32 128 1 91...

Page 107: ...ger and real number representations of KD are computed as provided in Equations 6 15 to 6 18 Table 32 shows the corresponding integer and real number representations of KD for each kd_index value Note...

Page 108: ...56 0 0273 23 60 0 0293 24 64 0 0313 25 72 0 0352 26 80 0 0391 27 88 0 0430 28 96 0 0469 29 104 0 0508 30 112 0 0547 31 120 0 0586 32 128 0 0625 33 144 0 0703 34 160 0 0781 35 176 0 0859 36 192 0 0938...

Page 109: ...0 8750 63 1920 0 9375 64 2048 1 000 65 2304 1 125 66 2560 1 250 67 2816 1 375 68 3072 1 500 69 3328 1 625 70 3584 1 750 71 3840 1 875 72 4096 2 000 73 4608 2 250 74 5120 2 500 75 5632 2 750 76 6144 3...

Page 110: ...118 229376 112 0 119 245760 120 0 The PID creates two mid band zeros fz1 and fz2 in the compensator transfer function Based on the real number representation of the PID coefficients the location of th...

Page 111: ...rresponding to a maximum exponent of 6 2_ 6 2_ 5 3 6 21 2_ 2_ 5 3 6 7 2_ 2 0 6 22 2 8 2_ 2 2_ 6 23 2_ 2 2 13 6 24 The location of the second high frequency pole can be computed as provided in Equation...

Page 112: ...is provided ramp0_force_duty ramp1_force_duty These functions are discussed in more detail in section 7 3 4 6 1 6 Coefficient scaling The PID coefficients are scaled with VRECT in order to maintain c...

Page 113: ...d therefore in this mode the FF is automatically set to zero Input voltage FF is part of the compensator and it is summed with the PID output to create the PWM duty cycle target as was shown in Figure...

Page 114: ...al purpose ADC input channels and it can be configured to sense the input voltage on the primary side PRISEN is obtained from the low speed TSADC and thereafter low pass filtered in telemetry In this...

Page 115: ...This option is suitable for boost or buck boost derived topologies and it can be also used to disable the FF functionality by setting the pid_ff_override to 0 Further FF adjustments include the follo...

Page 116: ...4 191 0 7 14 0 0273 223 7 8 16 0 0313 256 7 9 20 0 0391 323 5 10 24 0 0469 391 4 11 28 0 0547 460 4 12 32 0 0625 530 5 13 40 0 0781 674 4 14 48 0 0938 823 2 15 56 0 1094 977 3 16 64 0 1250 1136 8 17 8...

Page 117: ...in order to obtain the Type II response for PCMC the following need to be considered The compensator includes two single pole LPFs but neither of them is possible to bypass However by setting one of...

Page 118: ...y cycle limit of 0 3 and the minimum FF threshold of 0 05 and a scaling factor of 3 0 Figure 53 PID based open VS detection 6 5 Compensation filter registers The relevant compensator related registers...

Page 119: ...s Tswitch 4 s pid_ff_dt_adj 100 ns 2000 ns 0 05 LSB 2 10 range 0 to 0 2490 pid pid_kp_ff_lpf RW 7000_1C00h pid0 7000_2000h pid1 12 8 PID FF LPF coefficient The computed FF term is passed through a LPF...

Page 120: ...ents Kp Ki and KD Example VIN_nom 48 V FB topology Nturn 3 pid_vrect_ref VRECT_nom 48 V 3 16 V LSB 0 32 V range 0 0 to 81 6 V pid pid_kfp1_index_1ph RW 7000_1C04h pid0 7000_2004h pid1 5 0 PID pre filt...

Page 121: ...0 to 0 9961 pid pid_force_duty_en RW 7000_1C08h pid0 7000_2008h pid1 8 Forced duty cycle select 0 Use PID computed duty cycle 1 Use pid_force_duty pid pid_osp_ff_thr RW 7000_1C18h pid0 7000_2018h pid1...

Page 122: ..._override_sel RW 7000_1C20h pid0 7000_2020h pid1 10 PID FF override select 0 Use computed FF with VRECT selected by pid_ff_vrect_sel 1 Use pid_ff_override pid pid_ff_one_div_ vout_scale_loop RW 7000_1...

Page 123: ...to reset the accumulator by first writing a 1 to reset the accumulator followed by writing a 0 to release the reset 0 Accumulator operating normally 1 Accumulator reset to 0 pid pid_freeze_accum RW 70...

Page 124: ...prior to downstream adjustments LSB 0 3906 percent range 0 0 to 99 6094 percent pwm ramp0_force_duty_en RW 7000_2C34 8 PWM ramp0 forced duty cycle select 0 Use PID computed duty cycle 1 Use ramp0_for...

Page 125: ...commands are given The PWM converts the compensation filter output into one or more PWM pulses depending on the application The XDPP1100 has up to 12 PWM output pins The PWM consists of Two ramp gene...

Page 126: ...mp generator 1 The compensation filter receives its error input from the VS pins The corresponding PID source settings are rampX_pid_sel 0 selects PID0 VSEN rampX_pid_sel 1 selects PID1 BVSEN Typical...

Page 127: ...ed in Figure 55 Figure 55 Ramp counter for a non bridge and b bridge topologies The ramp counter operation depends on the topology For non bridge topologies buck ACF etc the ramp period is equal to th...

Page 128: ...ble FREQUENCY_SWITCH to a target Fswitch can be found using Equation 7 1 _ 50 6 50 6 7 1 Note 50e6 1 20e 9 7 1 1 PWM ramp modulation schemes The timing information provided by the ramp generator is a...

Page 129: ...ion ramp count 0 ramp count ramp_max t1 0 t1 0 t1 0 t1 0 a t1 t2 placement using trailing edge modulation t2 t2 t2 Ramp Count PWM ramp count 0 ramp count ramp_max t2 ramp_max b t1 t2 placement using l...

Page 130: ...ammed through the register rampX_sync_sel X 0 1 For ramp0 programming the register ramp0_sync_sel should always be set to 1 Thus ramp0 synchronizes to an external sync pulse if provided Otherwise its...

Page 131: ...sync function The direction of the external sync function input or output is defined by register sync_dir_out Set to 0 for sync input Set to 1 for sync output Multiple IO pins may be mapped as sync o...

Page 132: ...pulse generator The XDPP1100 contains 12 pulse generators as was shown in Figure 54 There is one dedicated pulse generator for each of the PWM outputs PWM1 through PWM12 These pulse generators use the...

Page 133: ...amp1 Loop 1 Phase 1 3 ramp1 Loop 0 Phase 2 For standard topologies HB FB forward buck etc the following considerations apply ramp0 is generally assigned to Loop 0 Phase 1 ramp1 is assigned to either L...

Page 134: ...ad time see section 7 2 4 to set the pulse width The VRSEN and BVRSEN options allow the definition of the rising edge based on the falling edge of VRECT This option may be used for example to turn on...

Page 135: ...1 even t2 even t1 odd t2 odd t1 even t2 odd pwmY_loop_map 1 0 1 ramp 0 pwmY_rise_sel 2 0 0 t1 pwmY_fall_sel 2 0 1 t2 pwmY_loop_map 1 0 1 ramp 0 pwmY_rise_sel 2 0 1 t2 pwmY_fall_sel 2 0 0 t1 pwmY_loop_...

Page 136: ..._df 7 0 PWM_DEADTIME 63 56 pwm4_dr 7 0 PWM_DEADTIME 159 152 pwm10_dr 7 0 PWM_DEADTIME 71 64 pwm5_df 7 0 PWM_DEADTIME 167 160 pwm11_df 7 0 PWM_DEADTIME 79 72 pwm5_dr 7 0 PWM_DEADTIME 175 168 pwm11_dr 7...

Page 137: ...ither high or low Register pwm_force_hi 11 0 forces the corresponding PWM output high Register pwm_force_lo 11 0 forces the corresponding PWM output low In both registers bit 0 corresponds to PWM1 and...

Page 138: ...n type as show in Table 42 Table 42 t1 and t2 computation by edge modulation type Modulation type t1_val t2_val Dual edge DE ramp_max ramp_pw 2 ramp_max ramp_pw 2 Leading edge LE ramp_max ramp_pw ramp...

Page 139: ...rent where the normalization is to the maximum range of the IADC This leads to a signed output range of 1 0 to 1 0 PCMC supports only TE modulation and therefore the register rampX_m_flavor should be...

Page 140: ...maximum duty cycle limit for the ramp X where the variable limit scales the maximum duty cycle with the measured VRECT in order to limit the transformer flux at high VIN The scaling is with respect t...

Page 141: ...applied at the beginning of the next ramp cycle i e ramp 0 after rampX_force_duty_en is set to 1 Subsequent changes to rampX_force_duty are applied at the beginning of the next ramp cycle after the ch...

Page 142: ...Equation 7 10 _ _ _ 2 _ _ _ _ _ 7 10 Where Iout_burst_entry_threshold is the output current value in amps at which to enter the BM and MFR_IOUT_APC is the PMBus command defining the APC setting of the...

Page 143: ...order to improve the transient performance the XDPP1100 supports two fast response modes for transient improvement These are Fast transient response for load steps Fast overshoot response for load rel...

Page 144: ...ent response mode These are pid_verr_exit_thrs which defines the error voltage Verr target voltage sensed voltage exit threshold as observed at VSEN i e after scaling by the VOUT resistor divider pid_...

Page 145: ...uces VOUT overshoot by providing maximum current decrease in the inductor Figure 64 shows an example of the fast overshoot response event Two registers control the entry into the fast overshoot respon...

Page 146: ...ast transient response due to the switching noise at the VSEN pin can be reduced in a similar way as discussed in the previous section by using the LPF The filter BW settings were summarized in Table...

Page 147: ...ch 2 Every 4 Tswitch 3 Every 8 Tswitch 4 Every 16 Tswitch 5 Every 32 Tswitch 6 7 Every 64 Tswitch It should be noted that rampX_irq_rate applies to both the t1 and t2 interrupts if they are both enabl...

Page 148: ...should be selected on interleaved designs due to the shared VOUT sense source VSEN on both phases PID1 should be selected on dual loop designs due to the different VOUT sense sources on both loops 0...

Page 149: ...secondary 2 PCMC on primary 3 Reserved pwm mode_control_loop1 RW 7000_2C00h 15 14 Loop 1 control mode select 0 VMC 1 PCMC on secondary 2 PCMC on primary 3 Reserved pwm ramp0_dutyc_lock RW 7000_2C00h 1...

Page 150: ...switch or 0 5 Tswitch and Tswitch for bridge topologies and t1 is modulated When using dual edge modulation t1 and t2 are centered around 0 5 Tswitch or 0 25 Tswitch and 0 75 Tswitch for bridge topolo...

Page 151: ...to the modulated edges created by the ramp When using TE modulation t1 is fixed at time 0 and t2 is modulated When using LE modulation t2 is fixed at Tswitch or 0 5 Tswitch and Tswitch for bridge topo...

Page 152: ...fication voltage 0 t1 1 t2 2 t1 even cycle 3 t2 even cycle 4 t1 odd cycle 5 t2 odd cycle 6 t1 delay 7 t2 delay 8 VRSEN neg edge 9 to 15 BVRSEN neg edge pwm pwm3_fall_sel RW 7000_2C04h 16 14 Topology d...

Page 153: ...h bridge topologies to distinguish between half cycles The VRSEN and BVRSEN options allow a PWM output to be set high after detection of the falling transition of the rectification voltage 0 t1 1 t2 2...

Page 154: ...0 5 Tswitch or 0 25 Tswitch and 0 75 Tswitch for bridge topologies and both are modulated Odd and even cycle designations are for use with bridge topologies to distinguish between half cycles The VRS...

Page 155: ...xed at time 0 and t2 is modulated When using LE modulation t2 is fixed at Tswitch or 0 5 Tswitch and Tswitch for bridge topologies and t1 is modulated When using DE modulation t1 and t2 are centered a...

Page 156: ...t1 odd cycle 5 t2 odd cycle 6 t1 delay 7 t2 delay pwm pwm6_rise_sel RW 7000_2C08h 13 10 Topology driven PWM6 rising edge select t1 and t2 refer to the modulated edges created by the ramp When using TE...

Page 157: ...ed Odd and even cycle designations are for use with bridge topologies to distinguish between half cycles 0 t1 1 t2 2 t1 even cycle 3 t2 even cycle 4 t1 odd cycle 5 t2 odd cycle 6 t1 delay 7 t2 delay p...

Page 158: ...DE modulation t1 and t2 are centered around 0 5 Tswitch or 0 25 Tswitch and 0 75 Tswitch for bridge topologies and both are modulated Odd and even cycle designations are for use with bridge topologie...

Page 159: ...by the ramp When using TE modulation t1 is fixed at time 0 and t2 is modulated When using LE modulation t2 is fixed at Tswitch or 0 5 Tswitch and Tswitch for bridge topologies and t1 is modulated When...

Page 160: ...0 t1 1 t2 2 t1 even cycle 3 t2 even cycle 4 t1 odd cycle 5 t2 odd cycle 6 t1 delay 7 t2 delay 8 VRSEN neg edge 9 to 15 BVRSEN neg edge pwm pwm10_fall_sel RW 7000_2C0Ch 9 7 Topology driven PWM10 fallin...

Page 161: ...h bridge topologies to distinguish between half cycles The VRSEN and BVRSEN options allow a PWM output to be set high after detection of the falling transition of the rectification voltage 0 t1 1 t2 2...

Page 162: ...0 5 Tswitch or 0 25 Tswitch and 0 75 Tswitch for bridge topologies and both are modulated Odd and even cycle designations are for use with bridge topologies to distinguish between half cycles The VRSE...

Page 163: ...modulation t1 is fixed at time 0 and t2 is modulated When using LE modulation t2 is fixed at Tswitch or 0 5 Tswitch and Tswitch for bridge topologies and t1 is modulated When using DE modulation t1 a...

Page 164: ...WM not in use 1 Loop 0 phase 0 2 Loop 1 phase 0 3 Loop 0 phase 1 pwm pwm5_loop_map RW 7000_2C10h 9 8 Defines the loop and phase mapping of the PWM5 output 0 PWM not in use 1 Loop 0 phase 0 2 Loop 1 ph...

Page 165: ...m RW 7000_2C14h 7 0 ramp0 nominal max duty cycle scaled by the rectification voltage VRECT The PMBus command MAX_DUTY defines a fixed max duty cycle limit This parameter defines a variable max duty cy...

Page 166: ...from the PID Above this threshold the FTR PW is reduced in proportion to VIN if VIN is less than lp0_ftr_vin_thresh FTR PW FF_Duty Tswitch 2 else FTR PW FF_Duty Tswitch 2 lp0_ftr_vin_thresh VIN LSB 1...

Page 167: ...priority than pwm_force_hi pwm pwm_on 7000_2C28h 11 0 PWM channel enabled for pulse generation when corresponding bit position high 0 corresponds to PWM1 11 corresponds to PWM12 Note Intended to be dr...

Page 168: ...percent range 0 0 to 99 6094 percent pwm ramp0_force_duty_e n RW 7000_2C34h 8 PWM ramp0 forced duty cycle select 0 Use PID computed duty cycle 1 Use ramp0_force_duty pwm ramp0_force_t1 RW 7000_2C38h...

Page 169: ...ation Computed by FW from PMBus command as follows ramp1_dc_max MAX_DUTY LSB 0 5 percent range 0 0 to 99 5 percent pwm ramp1_pw_min RW 7000_2C44h 15 8 PWM ramp1 min pulse width When the duty cycle fro...

Page 170: ...uty cycle 1 t1 set by ramp1_force_t1 pwm ramp1_force_t2 RW 7000_2C50h 10 0 PWM ramp1 forced t2 setting selected by ramp1_force_t2_en t2 is the time of the second PWM edge in a ramp cycle In a LE modul...

Page 171: ...318 75 ns pwm pwm2_dr RW 7000_2C58h 7 0 PWM2 rising edge delay dead time from t1 or t2 Mapping of the rising edge to t1 or t2 defined by pwm2_rise_sel In order to synchronously update all pwmX_dr and...

Page 172: ...wm pwm3_df RW 7000_2C5Ch 15 8 PWM3 falling edge delay dead time from t1 or t2 Mapping of the falling edge to t1 or t2 defined by pwm3_fall_sel In order to synchronously update all dead times simultane...

Page 173: ...7 0 PWM5 rising edge delay dead time from t1 or t2 Mapping of the rising edge to t1 or t2 defined by pwm5_rise_sel In order to synchronously update all pwmX_dr and pwmX_df times simultaneously an upd...

Page 174: ...2C68h 15 8 PWM6 falling edge delay dead time from t1 or t2 Mapping of the falling edge to t1 or t2 defined by pwm6_fall_sel In order to synchronously update all dead times simultaneously an update to...

Page 175: ...7 0 PWM8 rising edge delay dead time from t1 or t2 Mapping of the rising edge to t1 or t2 defined by pwm8_rise_sel In order to synchronously update all pwmX_dr and pwmX_df times simultaneously an upda...

Page 176: ...74h 15 8 PWM9 falling edge delay dead time from t1 or t2 Mapping of the falling edge to t1 or t2 defined by pwm9_fall_sel In order to synchronously update all dead times simultaneously an update to an...

Page 177: ...0 PWM11 rising edge delay dead time from t1 or t2 Mapping of the rising edge to t1 or t2 defined by pwm11_rise_sel In order to synchronously update all pwmX_dr and pwmX_df times simultaneously an upd...

Page 178: ...ping of the falling edge to t1 or t2 defined by pwm12_fall_sel In order to synchronously update all dead times simultaneously an update to any dead time register only becomes effective after 7000_2C80...

Page 179: ...ramp0_t1_irq_sel and ramp0_t2_irq_sel 0 Every Tswitch 1 Every 2 Tswitch 2 Every 4 Tswitch 3 Every 8 Tswitch 4 Every 16 Tswitch 5 Every 32 Tswitch 6 Every 64 Tswitch 7 Every 64 Tswitch pwm ramp1_t1_ir...

Page 180: ...icient scaling and variable max duty cycle limit PID coefficients are scaled with VRECT to maintain a constant loop gain This parameter defines the reference VRECT voltage at which the gain scale is 1...

Page 181: ...t VSEN pid pid_verr_entry_thrs RW 7000_1C0Ch pid0 7000_200Ch pid1 20 14 FTR mode Verr entry threshold where the error voltage is defined as Verr target voltage sense voltage When Verr is greater than...

Page 182: ...e control loop exits OVS mode Notes 1 This threshold is always negative indicating that the controller exits OVS mode prior to the sensed voltage undershooting the target 2 There is a 1 25 mV offset i...

Page 183: ...7 21 OVS mode error voltage Verr slope entry threshold where the error voltage is defined as Verr target voltage sense voltage When Verr is less than pid_ovs_entry_thrs AND Verr slope is less than pid...

Page 184: ...her cycle count can be used to increase the inductor peak current in a burst event which will increase the time between burst events at a given load current 0 1 cycle 1 2 cycles 2 4 cycles 3 8 cycles...

Page 185: ...cle in percent of the unit s power conversion stage Format is in LINEAR11 with exponent 2 FREQUENCY_SWITCH RW Word 33h 15 0 The FREQUENCY_SWITCH command sets the switching frequency in kHz Format is L...

Page 186: ...PAGE0 Loop 0 VSEN VOUT sense PMBus PAGE1 Loop 1 BVSEN VOUT sense 31 28 Reserved set to 0h 27 16 pwm_srfet_mask 11 0 0 PWM1 11 PWM12 15 12 Reserved set to 0h 11 0 pwm_on_mask 11 0 0 PWM1 11 PWM12 PWM_D...

Page 187: ...falling edge dead time pwm10_df 159 152 PWM10 rising edge dead time pwm10_dr 167 160 PWM11 falling edge dead time pwm11_df 175 168 PWM11 rising edge dead time pwm11_dr 183 176 PWM12 falling edge dead...

Page 188: ...43 136 PWM9 rising edge dead time pwm9_dr 151 144 PWM10 falling edge dead time pwm10_df 159 152 PWM10 rising edge dead time pwm10_dr 167 160 PWM11 falling edge dead time pwm11_df 175 168 PWM11 rising...

Page 189: ...V 1 0 2021 08 25 XDPP1100 technical reference manual Digital power controller Digital pulse width modulator Command name Access Length Address Bits Description ramp1 even in the case that both PWM ra...

Page 190: ...mmable BW determined by register tlmX_kfp_vout where X 0 1 for Loop 0 1 The BW programming via tlmX_kfp_vout is given in Table 50 Figure 65 Output voltage telemetry block diagram Table 50 VOUT LPF BW...

Page 191: ...t buck topology Register tlmX_vin_force which forces the VIN voltage value this can be used by the FW to override the HW VIN computation options Register tlmX_vin_src_sel which allows the selection of...

Page 192: ...lm_kfp_iout tlm_kfp_iin tlm_kfp_duty kfp kfp_real F3db Fswitch tlm_kfp_vin tlm_kfp_iout tlm_kfp_iin tlm_kfp_duty kfp kfp_real F3db Fswitch 0 4 0 0005 7 78E 05 20 128 0 0156 2 53E 03 1 5 0 0006 9 72E 0...

Page 193: ...viding the output current telemetry These are ISEN and BISEN which can be selected individually to provide IOUT or in the case of a dual phase or interleaved topology the sum of the ISEN and BISEN cur...

Page 194: ...is available as read only register tlmX_iin_lpf It is used for the READ_IIN PMBus command as well as the IIN fault functions 8 5 Input CE The IIN submodule is shown in Figure 69 The estimated input c...

Page 195: ...nd output current telemetry submodules and correspondlingly the registers tlmX_vin_lpf and tlmX_iin_lpf are the outputs of the input voltage and input current telemetry submodules 8 7 Temperature tele...

Page 196: ...0 029 26 384 0 0469 0 978 7 14 0 0017 0 034 27 448 0 0547 1 151 8 16 0 0020 0 039 28 512 0 0625 1 326 9 20 0 0024 0 049 29 640 0 0781 1 686 10 24 0 0029 0 058 30 768 0 0938 2 058 11 28 0 0034 0 068 31...

Page 197: ...Figure 71 The ramp on time t2 t1 is low pass filtered at a programmable BW defined by register tlmX_kfp_duty and the BW programming is shown in Table 52 Figure 71 Duty cycle telemetry block diagram T...

Page 198: ...n the ts_muxmode selection due to the different sample rates Figure 73 General purpose ADC telemetry block diagram The PRISEN BW is programmed through register tlm_kfp_prisen and follows a slightly di...

Page 199: ...1094 4 886 12 32 0 0039 0 156 32 1024 0 1250 5 684 13 40 0 0049 0 195 33 1280 0 1563 7 368 14 48 0 0059 0 235 34 1536 0 1875 9 182 15 56 0 0068 0 274 35 1792 0 2188 11 141 16 64 0 0078 0 313 36 2048...

Page 200: ...894 8 11 Telemetry interrupts The XDPP1100 provides 16 independently programmable telemetry IRQs Figure 74 shows a block diagram of one IRQ along with the ORing of the other IRQs to generate signal t...

Page 201: ...y register tlm_irq_stat 8 12 Telemetry high low watermark detect The XDPP1100 contains two watermark detectors per loop designated as A and B Figure 75 shows a block diagram of a single detector Each...

Page 202: ...s Description telem tlm_kfp_duty RW 7000_3400h Loop 0 7000_3800h Loop 1 5 0 Duty cycle telemetry LPF coefficient index Note that exp settings greater than 9 are clamped to 9 Set to 63 to bypass filter...

Page 203: ...Set to 63 to bypass filter kfp_exp tlm_kfp_iout 5 2 kfp_man 4 tlm_kfp_iout 1 0 kfp kfp_man 2 kfp_exp 2 13 F3db kHz kfp 1 kfp Fswitch kHz 2 pi telem tlm_vin_src_sel RW 7000_3400h Loop 0 7000_3800h Loop...

Page 204: ...db kHz kfp 1 kfp 50e3 2 pi telem tlm_vrect_rcorr RW 7000_3404h Loop 0 7000_3804h Loop 1 17 12 Resistive correction term applied to VRECT computation This term is multiplied by the output current and a...

Page 205: ...d1 1 d0 tlm_freq 10 1 else READ_FREQUENCY 15 0 5 d0 1 d0 tlm_freq 9 0 LSB 1 kHz range 0 to 2047 kHz telem tlm_iin_lpf R 7000_3410h Loop 0 7000_3810h Loop 1 12 0 Low pass filtered input current teleme...

Page 206: ...urce for VIN by tlm_vin_src_sel Can be used by FW to bypass the HW based VIN computation LSB 62 5 mV range 0 0 to 127 9375 V telem tlm_vin_convert_factor RW 7000_3428h Loop 0 7000_3828h Loop 1 21 0 Co...

Page 207: ...82 U 9 16 LSB 2 24 range 0 0 to 0 1250 telem tlm_vout_fs R 7000_3434h Loop 0 7000_3834h Loop 1 11 0 Output voltage VOUT telemetry at the sample clock rate 50 MHz Note This field is in VSADC code form...

Page 208: ...RMER_SCALE 9 0 0 else if hb 0 exp 12 tlm_vrect_scale_loop 11 0 00 MFR_TRANSFORMER_SCALE 9 0 else if hb 1 exp 10 tlm_vrect_scale_loop 11 0 0 MFR_TRANSFORMER_SCALE 9 0 0 else if hb 1 exp 11 tlm_vrect_sc...

Page 209: ...tor telem tlm_out_hi_A R 7000_3454h Loop 0 7000_3854h Loop 1 12 0 High watermark detector A output Format depends on input selected by tlm_hilo_mark_A_sel VIN Unsigned LSB 62 5 mV range 0 0 to 127 937...

Page 210: ...xp settings greater than 9 are clamped to 9 Set to 63 to bypass filter kfp_exp tlm_kfp_tsen 5 2 kfp_man 4 tlm_kfp_tsen 1 0 kfp kfp_man 2 kfp_exp 2 13 F3db kHz kfp 1 kfp 125 kHz 2 pi tlmcom tlm_kfp_pri...

Page 211: ...T S9 4 LSB 62 5 mA range 256 to 255 9375 A VOUT U12 3 LSB 156 25 V range 0 0 to 5 11984375 V IIN U6 7 LSB 7 8125 mA range 0 0 to 63 9922 A VIN U7 4 LSB 62 5 mV range 0 0 to 127 9375 V Duty U0 16 LSB 2...

Page 212: ...U6 7 LSB 7 8125 mA range 0 0 to 63 9922 A VIN U7 4 LSB 62 5 mV range 0 0 to 127 9375 V Duty U0 16 LSB 2 16 range 0 0 to 0 99998 Fswitch U11 0 LSB 1 kHz range 0 to 2047 kHz ATSEN BTSEN ITSEN U10 0 LSB...

Page 213: ...9922 A VIN U7 4 LSB 62 5 mV range 0 0 to 127 9375 V Duty U0 16 LSB 2 16 range 0 0 to 0 99998 Fswitch U11 0 LSB 1 kHz range 0 to 2047 kHz ATSEN BTSEN ITSEN U10 0 LSB 1 ADC code range 0 to 1023 ADC code...

Page 214: ...9998 Fswitch U11 0 LSB 1 kHz range 0 to 2047 kHz ATSEN BTSEN ITSEN U10 0 LSB 1 ADC code range 0 to 1023 ADC codes IMON PRISEN XADDR1 XADDR2 U10 4 LSB 0 0625 ADC code range 0 0 to 1023 9375 ADC codes t...

Page 215: ...DC codes IMON PRISEN XADDR1 XADDR2 U10 4 LSB 0 0625 ADC code range 0 0 to 1023 9375 ADC codes tlmcom tlm_irq_thr_src_sel_4 RW 7000_5014h 20 16 Telemetry IRQ 4 source select Selects signal to compare a...

Page 216: ...023 9375 ADC codes tlmcom tlm_irq_thr_src_sel_5 RW 7000_5018h 20 16 Telemetry IRQ 5 source select Selects signal to compare against tlm_irq_gereric_thr_5 for IRQ generation 0 Loop 0 IOUT 1 Loop 1 IOUT...

Page 217: ...emetry IRQ 6 source select Selects signal to compare against tlm_irq_gereric_thr_6 for IRQ generation 0 Loop 0 IOUT 1 Loop 1 IOUT 2 Loop 0 VOUT 3 Loop 1 VOUT 4 Loop 0 IIN 5 Loop 1 IIN 6 Loop 0 VIN 7 L...

Page 218: ...q_gereric_thr_7 for IRQ generation 0 Loop 0 IOUT 1 Loop 1 IOUT 2 Loop 0 VOUT 3 Loop 1 VOUT 4 Loop 0 IIN 5 Loop 1 IIN 6 Loop 0 VIN 7 Loop 1 VIN 8 Loop 0 duty 9 Loop 1 duty 10 Loop 0 Fswitch 11 Loop 1 F...

Page 219: ...VOUT 3 Loop 1 VOUT 4 Loop 0 IIN 5 Loop 1 IIN 6 Loop 0 VIN 7 Loop 1 VIN 8 Loop 0 duty 9 Loop 1 duty 10 Loop 0 Fswitch 11 Loop 1 Fswitch 12 ATSEN 13 BTSEN 14 Internal temp 15 IMON 16 PRISEN 17 XADDR1 18...

Page 220: ...VIN 7 Loop 1 VIN 8 Loop 0 duty 9 Loop 1 duty 10 Loop 0 Fswitch 11 Loop 1 Fswitch 12 ATSEN 13 BTSEN 14 Internal temp 15 IMON 16 PRISEN 17 XADDR1 18 XADDR2 19 to 31 Unused tlmcom tlm_irq_gereric_thr_10...

Page 221: ...y 10 Loop 0 Fswitch 11 Loop 1 Fswitch 12 ATSEN 13 BTSEN 14 Internal temp 15 IMON 16 PRISEN 17 XADDR1 18 XADDR2 19 to 31 Unused tlmcom tlm_irq_gereric_thr_11 RW 7000_5030h 15 0 Telemetry IRQ 11 thresho...

Page 222: ...XADDR2 19 to 31 Unused tlmcom tlm_irq_gereric_thr_12 RW 7000_5034h 15 0 Telemetry IRQ 12 threshold Compared against signal selected by tlm_irq_thr_src_sel_12 Format based on selected source IOUT S9 4...

Page 223: ...Compared against signal selected by tlm_irq_thr_src_sel_13 Format based on selected source IOUT S9 4 LSB 62 5 mA range 256 to 255 9375 A VOUT U12 3 LSB 156 25 V range 0 0 to 5 11984375 V IIN U6 7 LSB...

Page 224: ...sel_14 Format based on selected source IOUT S9 4 LSB 62 5 mA range 256 to 255 9375 A VOUT U12 3 LSB 156 25 V range 0 0 to 5 11984375 V IIN U6 7 LSB 7 8125 mA range 0 0 to 63 9922 A VIN U7 4 LSB 62 5 m...

Page 225: ...5 mA range 256 to 255 9375 A VOUT U12 3 LSB 156 25 V range 0 0 to 5 11984375 V IIN U6 7 LSB 7 8125 mA range 0 0 to 63 9922 A VIN U7 4 LSB 62 5 mV range 0 0 to 127 9375 V Duty U0 16 LSB 2 16 range 0 0...

Page 226: ...range 0 to 1023 75 ADC codes tlmcom tlm_btsen_lpf R 7000_504Ch 9 0 Low pass filtered BTSEN telemetry output Note that the format of this register is ADC codes The ADC code to temperature conversion is...

Page 227: ...to IRQX 0 IRQ not set 1 IRQ set tlmcom tlm_imon_adc_lpf R 7000_5068h 13 0 Low pass filtered IMON telemetry output when used as a general purpose ADC LSB 0 0625 ADC code range 0 to 1023 9375 ADC codes...

Page 228: ...h exponent defined by FW_CONFIG_TELEMETRY READ_IIN_EX P READ_VOUT R Word 8Bh 15 0 Returns the measured not commanded output voltage in the same format as set by the VOUT_MODE command READ_IOUT R Word...

Page 229: ...IN R Word 97h 15 0 Returns the FW computed input power in watts in the LINEAR11 format with exponent defined by FW_CONFIG_TELEMETRY READ_POWE R_EXP MFR_VRECT_SCALE RW Word CDh 15 0 Scales the VRECT in...

Page 230: ...sec Nturn_prim Note When tlm1_vin_src_sel 2 Loop 0 VOUT set PAGE 1 MFR_TRANSFORMER_SCALE B3FFh 0 999 for correct scaling of VIN telemetry FW_CONFIG_TELEMETRY RW Block 21 bytes C6h 103 10 0 READ_DUTY_E...

Page 231: ...al Digital power controller Telemetry Command name Access Length Address Bits Description READ_TEMPERATURE_2 ITSEN 4 READ_TEMPERATURE_1 ITSEN READ_TEMPERATURE_2 ATSEN 5 READ_TEMPERATURE_1 ITSEN READ_T...

Page 232: ...ng subsections Figure 76 Fault module block diagram 9 1 Loop faults The loop fault module is responsible for detecting and reporting faults that are specific to a loop such as Output and input voltage...

Page 233: ..._fault_cnt faultX_vin_uv_warn_thresh faultX_vin_uv_warn_cnt faultX_vin_fault_hyst IOUT faults tlmX_iout_fsw faultX_iout_oc_fault_thresh faultX_iout_oc_fault_cnt faultX_iout_oc_warn_thresh faultX_iout_...

Page 234: ...oltage definition do not need to be consecutive but a single sample above the value in Equation 9 3 will reset the count and deassert the fault The register fault_vout_uv_fault_thresh is referenced to...

Page 235: ...ined in Equation 9 6 fault_vin_ov_warn_thresh fault_vin_warn_hyst _ _ _ _ _ _ _ 9 6 The samples for the overvoltage warning definition do not need to be consecutive but a single sample below the value...

Page 236: ...ld fault_iout_oc_fault_thresh for the number of samples fault_iout_oc_fault_cnt without falling below the threshold defined in Equation 9 9 _ _ _ _ _ _ _ _ 9 9 The samples for the overcurrent fault do...

Page 237: ...h is computed by FW based on PMBus command IOUT_UC_FAULT_LIMIT Output current fault related PMBus commands The output current faults and warnings are reported on the following PMBus commands STATUS_BY...

Page 238: ...eshold defined in Equation 9 14 _ _ _ _ _ _ _ 9 14 The samples for the input overcurrent falut do not need to be consecutive but a single sample below the value in Equation 9 14 will reset the count a...

Page 239: ...nsor TC PTC OT_FAULT o Asserted when temp is greater than fault_ot_fault_thresh o Deasserted when temp is less than fault_ot_fault_thresh fault_temp_fault_hyst PTC OT_WARN o Asserted when temp is grea...

Page 240: ...its 1 0 All PMBus commands and their programming are described in section 9 8 9 1 7 Current sharing fault The XDPP1100 asserts a current sharing fault under the conditions described in section 10 1 Th...

Page 241: ...dividual faults reported on fault_reg_loop and fault_status_loop fault_force_loop is bitwise ORed with fault_loop_bus to provide a method for FW to trigger the HW based loop faults fault_clear_loop al...

Page 242: ...h 9 2 6 describe the details of the common faults shown in the block diagram Figure 79 Common fault submodule block diagram 9 2 1 Current sense tracking fault The XDPP1100 supports a current sense err...

Page 243: ...n VSEN or BVSEN the missing RH is detected through the PID compensators open sense fault detection as described in section 6 4 When VRECT or VIN is sensed on VRSEN or BVRSEN the missing RH leads to an...

Page 244: ...g after an initial shutdown fault has occurred Table 65 shows the shared bit to fault mapping that applies to registers fault_enable_com fault_force_com fault_clear_com fault_reg_com fault_status_com...

Page 245: ...ore practical method for determining the fault that has occurred is via the fault priority encoding module A portion of the priority encoder LUT is shown in Figure 82 The LUT input is formed from a 96...

Page 246: ...0000000000000000000000000 32d XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX_XXXXXXXXXXXXXXXXXXXXXXXXXXXXXX10_00000000000000000000000000000000 33d XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX_XXXXXXXXXXXXXXXXXXXXXXXXXXXXX100_0...

Page 247: ...gned shutdown is not available for common fault shutdown When a shutdown enabled fault occurs the event is registered as fault0_shut fault1_shut or faultcm_shut based on the fault type fault0_shut and...

Page 248: ...0 Output overvoltage fault count Defines the number of 50 MHz samples the output voltage must exceed the fault threshold by in order to assert a fault 0 1 sample 1 2 samples 2 4 samples 3 8 samples fa...

Page 249: ...R_IOUT_OC_FAST overcurrent fault count Defines the number of consecutive switching cycles Tswitch the cycle averaged current must exceed the fault threshold by in order to assert a fault Count fault_m...

Page 250: ...ult fault_iin_oc_fault_cnt RW 7000_3C04h Loop 0 7000_4004h Loop 1 12 8 Input overcurrent fault count Defines the number of consecutive switching cycles Tswitch the low pass filtered input current must...

Page 251: ...N_OV_WARN_LIMIT fault_vin_fault_hyst VIN_UV_WARN Assert when VIN is less than VIN_OV_WARN_LIMIT Deassert when VIN is greater than or equal to VIN_UV_WARN_LIMIT fault_vin_fa ult_hyst VIN_UV_FAULT Asser...

Page 252: ...OUT_OV_WARN_LIMIT fault_vout_fault_hyst VOUT_UV_WARN Assert when VOUT is less than VOUT_OV_WARN_LIMIT Deassert when VOUT is greater than or equal to VOUT_UV_WARN_LIMIT fault_vou t_fault_hyst VOUT_UV_F...

Page 253: ...tput overcurrent IOUT_OC fault warning deassertion hysteresis Internally the IOUT OC fault is asserted when IOUT exceeds IOUT_OC_FAULT_LIMIT for fault_iout_oc_fault_cnt samples without dropping below...

Page 254: ..._FAULT_LIMIT fault_iout _uc_fault_hyst will reset the count For the typical case this parameter should be set to a positive current This hysteresis parameter applies to only the IOUT UC fault as shown...

Page 255: ...is greater than fault_ut_warn_thresh fault_temp_fault_hyst PTC UT_FAULT Asserted when temp is less than fault_ut_fault_thresh Deasserted when temp is greater than fault_ut_fault_thresh fault_temp_fau...

Page 256: ..._OV_WARN 3 VOUT_UV_FAULT 4 VOUT_UV_WARN 5 VIN_OV_FAULT 6 VIN_OV_WARN 7 VIN_UV_FAULT 8 VIN_UV_WARN 9 IOUT_OC_FAULT 10 IOUT_OC_LV_FAULT 11 IOUT_OC_WARN 12 IOUT_UC_FAULT 13 MFR_IOUT_OC_FAST 14 IIN_OC_FAU...

Page 257: ..._FAULT 8 VIN_UV_WARN 9 IOUT_OC_FAULT 10 IOUT_OC_LV_FAULT 11 IOUT_OC_WARN 12 IOUT_UC_FAULT 13 MFR_IOUT_OC_FAST 14 IIN_OC_FAULT 15 IIN_OC_WARN 16 OT_FAULT 17 OT_WARN 18 UT_FAULT 19 UT_WARN 20 POWER_LIMI...

Page 258: ...esistor divider Computed by FW from PMBus command as follows fault_vout_ovp_fault_thresh Int VOUT_OV_FAULT_LIMIT U16 X X VOUT_SCALE_LOOP U0 16 200 2 X 2 16 where X negative of VOUT_MODE exponent LSB 5...

Page 259: ...VOUT_UV_WARN_LIMIT U16 X X VOUT_SCALE_LOOP U0 16 200 2 X 2 16 where X negative of VOUT_MODE exponent LSB 5 mV range 0 0 to 5 115 V fault fault_vin_ov_fault_thres h RW 7000_3C28h Loop 0 7000_4028h Loo...

Page 260: ...hresh RW 7000_3C3Ch Loop 0 7000_403Ch Loop 1 9 0 Output overcurrent LV fault threshold Note that this threshold is defined with respect to the voltage at the VSEN pin after the VOUT sense resistor di...

Page 261: ...LT_LIMIT 10 0 2 IIN_OC_FAULT_LIMIT 15 11 2 LSB 0 25 A range 0 0 to 63 75 A fault fault_iin_oc_warn_thres h RW 7000_3C50h Loop 0 7000_4050h Loop 1 7 0 Input overcurrent warning threshold Computed by FW...

Page 262: ...h Loop 1 2 0 Fault temperature source and sensor TC select 0 TSEN NTC 1 BTSEN NTC 2 XDPP1100 internal temperature 3 TSEN PTC 4 BTSEN PTC fault fault_shut_clr_loop W 7000_3C68h Loop 0 7000_4068h Loop 1...

Page 263: ..._MIN_WARN 23 SYNC_FAULT 24 to 31 Unused fault fault_force_loop RW 7000_3C70h Loop 0 7000_4070h Loop 1 31 0 Fault force set register When the bit corresponding to a fault warning is set to 1 that fault...

Page 264: ...WARN 9 IOUT_OC_FAULT 10 IOUT_OC_LV_FAULT 11 IOUT_OC_WARN 12 IOUT_UC_FAULT 13 MFR_IOUT_OC_FAST 14 IIN_OC_FAULT 15 IIN_OC_WARN 16 OT_FAULT 17 OT_WARN 18 UT_FAULT 19 UT_WARN 20 POWER_LIMIT_MODE 21 ISHARE...

Page 265: ...at 50 MHz Once a fault bit is set it is latched in this register and can only be cleared via fault_clear_loop 0 Reserved 1 VOUT_OV_FAULT 2 VOUT_OV_WARN 3 VOUT_UV_FAULT 4 VOUT_UV_WARN 5 VIN_OV_FAULT 6...

Page 266: ...bled fault fault_iout_cc_en_fast RW 7000_3C84h Loop 0 7000_4084h Loop 1 1 Constant current mode enable for MFR_IOUT_OC_FAST_FAULT Set by FW based on MFR_IOUT_OC_FAST_FAULT_RESP ONSE 0 Disabled 1 Enabl...

Page 267: ...faults are enabled for fault interrupt generation when their corresponding bit is high This register is controlled by FW based on the PMBus command FW_CONFIG_FAULTS bits 167 136 which have a 1 to 1 ma...

Page 268: ...t 2 Common fault 0 IRQ asserted 1 IRQ deasserted faultcom fault_force_com RW 7000_5418h 31 0 Fault force set register When the bit corresponding to a fault or warning is set to 1 that fault or warning...

Page 269: ...h 31 0 Fault status register generated by sub sampling fault_reg_com at 2 MHz Fault interrupts are generated from this register Once a fault bit is set it is latched in this register and can only be c...

Page 270: ...urn fault_encode 0 fault_irq_bus can be used along with fault_encode to distinguish between the two cases faultcom fault_reg_com R 7000_5428h 31 0 Fault status register updated at 50 MHz Once a fault...

Page 271: ...ult 7 6 Response 0 Continue operation without interruption 1 Continue operation for time specified by delay bits 2 0 then if fault condition still present shut down and respond according to retry bits...

Page 272: ...5 3 Retry setting 0 Remain disabled until fault cleared 1 to 6 Attempt to restart 5 3 times with delay 2 0 between restarts 7 Attempt to restart continuously until commanded OFF 2 0 Delay time 0 to 7...

Page 273: ...the IOUT_OC_LV_FAULT_LIMIT specifies that voltage threshold The data bytes are formatted according to the setting of the VOUT_MODE command Note that the IOUT_OC_LV_FAULT_RESPONSE command is not suppo...

Page 274: ...lt condition still present shut down and respond according to retry bits 5 3 2 Shut down and respond according to retry bits 5 3 3 Shut down until fault no longer present 5 3 Retry setting 0 Remain di...

Page 275: ...FF 2 0 Delay time 0 to 7 Number of delay time units between restart attempts unit defined by FW_CONFIG_FAULTS command VIN_OV_FAULT_LIMIT RW Word 55h 15 0 Sets the value of the input voltage that cause...

Page 276: ...NS E RW Byte 5Ah 7 0 Instructs the device on what action to take in response to an input undervoltage fault 7 6 Response 0 Continue operation without interruption 1 Continue operation for time specifi...

Page 277: ...rd 5Dh 15 0 Sets the value of the input current in amps that causes an input overcurrent warning The format is LINEAR11 The hardware is 0 25 A suggesting an exponent of 2 TON_MAX_FAULT_LIMIT RW Word 6...

Page 278: ...STATUS_BYTE RW Byte 78h 7 0 Returns one byte of information with a summary of the most critical faults 7 BUSY A fault was declared because the device was busy and unable to respond 6 OFF Asserted if t...

Page 279: ...fault or warning not listed in bits 15 9 of STATUS_WORD has occurred 7 0 See STATUS_BYTE STATUS_VOUT RW Byte 7Ah 7 0 Returns one data byte with contents as follows 7 VOUT_OV_FAULT 6 VOUT_OV_WARNING 5...

Page 280: ...eived 5 Packet error check PEC failed 4 Memory fault detected 3 Processor fault detected 2 Reserved 1 A communication fault not listed has occurred 0 Other memory or logic fault has occurred STATUS_OT...

Page 281: ...t_pin_mask_hw 31 0 FAULT pin masking for hardware faults Set bit to 1 to disable fault reporting on FAULT pin 0 Reserved 1 VOUT_OV_FAULT 2 VOUT_OV_WARN 3 VOUT_UV_FAULT 4 VOUT_UV_WARN 5 VIN_OV_FAULT 6...

Page 282: ...RN 5 VIN_OV_FAULT 6 VIN_OV_WARN 7 VIN_UV_FAULT 8 VIN_UV_WARN 9 IOUT_OC_FAULT 10 IOUT_OC_LV_FAULT 11 IOUT_OC_WARN 12 IOUT_UC_FAULT 13 MFR_IOUT_OC_FAST 14 IIN_OC_FAULT 15 IIN_OC_WARN 16 OT_FAULT 17 OT_W...

Page 283: ...F open fault 18 BVSEN_BVRSEN open fault 19 to 31 Unused 199 168 Fault_t2_shut_mask_loop_hw 31 0 Masking for loop hw fault shutdown on pwm ramp t2 time usually falling edge of PWM pulse Bits 199 168 co...

Page 284: ...s long as the voltage remains above IOUT_OC_LV_FAULT_LIMIT 2 Not supported 3 Shut down and respond according to retry bits 5 3 5 3 Retry setting 0 Remain disabled until fault cleared 1 to 6 Attempt to...

Page 285: ...esistance load line as described in section 5 4 No additional external components or connections are required and each supply is programmed with a non zero droop resistance A supply with a higher no l...

Page 286: ...ply output current to IMON DAC output current as given in Equation 10 2 10 _ 16 10 2 A block diagram of the current sharing function including the connections to the current DAC and TSADC is shown in...

Page 287: ...current proceeds to a PI compensation filter described in section 10 2 The output of this PI filter is in the format of an adjustment term to the target voltage Both positive and negative voltage adj...

Page 288: ...hr_kp 24 ishr_ki 16 Fswitch 250 kHz 10 3 Current sharing FW override The current share PI filter output ishare_adj may be overridden through the following registers ishr_fw_en ishr_fw_adj Similarly th...

Page 289: ...t to be measured by TSADC ts_tsidac_imon_sel 1 Connects current DAC output to IMON pin ts_muxmode 4 6 or 7 These settings include measurement of the IMON input in the TSADC input mux auto sequencing 1...

Page 290: ...ion 0 IMON analog IO select for current sharing 1 GPIO0 3 digital IO 2 GPIO1 3 digital IO 3 SYNC digital IO 4 FAN1_TACH digital input 5 to 7 Not used common imon_pd RW 7000_3008h 3 Pin IMON weak pull...

Page 291: ...al coefficient index Note that index settings greater than 55 are clamped to 55 ki_exp ishr_ki 5 3 ki_man 8 ishr_ki 2 0 ki kp_man 2 ki_exp 2 12 common ishare_clamp_neg RW 7000_3024h 7 0 Negative clamp...

Page 292: ...ich current sharing is not attempted To convert to amps divide by ishr_scale This register is computed by FW based on PMBus command MFR_ISHARE_THRESHOLD LSB 1 code range 0 to 255 codes tsen imon_meas_...

Page 293: ...ermined by the setting of ts_muxctrl1 0 to 3 Defined by ts_muxctrl1 2 4 Auto sequence 1 2 1 3 1 2 1 4 5 Auto sequence 1 5 1 3 1 7 1 4 6 Auto sequence 1 5 2 3 1 7 2 4 7 Auto sequence 1 5 2 3 1 7 6 4 Se...

Page 294: ...f a single loop with up to two phases driving a common output voltage Figure 89 shows an example of an interleaved HBCT topology where the inductor currents in LOUT1 and LOUT2 may become imbalanced Fi...

Page 295: ...ister is shown in Table 72 A setting to always enable the current balance is also provided Table 72 Current balance current enable threshold programming ibal_en_thresh Current balance enable threshold...

Page 296: ...48 ki_ibal 32 Fswitch 250 kHz Figure 91 Example PI magnitude plot for kp_ibal 48 ki_ibal 32 Fswitch 250 kHz 11 3 Current balance FW override The current balance output ibal_duty_adj may be overridden...

Page 297: ..._3000h 11 6 Current balance PI filter integral coefficient index Set to 0 to disable the integral component of the filter Note that index settings greater than 55 are clamped to 55 ki_exp ki_ibal 5 3...

Page 298: ...OM cost or board area or reducing efficiency To overcome these drawbacks while obtaining flux balance the XDPP1100 contains two flux balance circuits to support interleaved designs It is capable of ma...

Page 299: ...even Teven Vrect_odd Todd 0 1 Time Vrect_even Vrect_odd Teven Todd Vrect_avg Teven Todd 1 x Voltage Vrect_odd Vrect_even Subsequent to the balance mode selection the computed error voltage is filtered...

Page 300: ...balance duty cycle adjustment is applied after the duty cycle lock in the PWM function 12 2 Flux balance PI filter The voltage error is processed by the PI filter which consists of A proportional ter...

Page 301: ...fier SR devices If the SR FETs are disabled or diodes are used in their place the inductor current is discontinuous In this discontinuous conduction mode DCM the VRECT rising edge can occur prior to t...

Page 302: ...o 0 12 5 Flux balance fault detection If the flux balance circuit is unable to achieve balance between half cycles it can be configured to declare a fault Flux balance fault detection diagram is shown...

Page 303: ...ated error threshold 0 Disabled 1 25 percent 2 12 50 percent 3 6 25 percent As was shown in Figure 95 the results of the two error method comparisons are ORed together Thereafter they are sent to the...

Page 304: ...mmon fbal_time_only RW 7000_3000h 28 In the flux balance mode of the flux voltage balance PI filter select between volt second or time only balancing 0 Volt second balance mode 1 Time only balance mod...

Page 305: ...A setting of 63 disables this feature LSB 0 5 A range 0 0 to 31 5 A common fbal_dcm_dis_cnt RW 7000_3030h 21 20 Defines the number of consecutive current samples below fbal_dcm_thresh required to dis...

Page 306: ...0h 8 Enables FW controlled flux voltage balance loop via fbal2_fw_adj 0 Use HW computed flux voltage balance adjust 1 Use fbal2_fw_adj pwm ramp0_dutyc_lock RW 7000_2C00h 16 ramp0 duty cycle lock enabl...

Page 307: ...t The XDPP1100 provides HW support for up to two fan PWM outputs identified as FAN1_PWM FAN2_PWM The pin programming options for these fan PWM outputs are shown in Table 78 The PWM output switching fr...

Page 308: ...ractional duty cycle of FANx where X 1 2 o FAN_COMMAND_x C000h 0 256 0 0 percent o FAN_COMMAND_x C001h 1 256 0 390625 percent o FAN_COMMAND_x C0FEh 254 256 99 21875 percent o FAN_COMMAND_x C0FFh overr...

Page 309: ...er programming IMON common imon_func 4 PWM12 common pwm12_func 4 FAULT2 common fault2_func 4 PWM8 common pwm8_func 4 For fan speed input the following fan features are supported Fan speeds in the rang...

Page 310: ...cription fan fan_imax RW 7000_4400h Fan 1 7000_4800h Fan 2 7 0 Fan maximum current reference when operating in current mode When the output current exceeds fan_imax the output duty cycle will be 100 p...

Page 311: ...ce when operating in current mode 0 Loop 0 IOUT 1 Loop 1 IOUT fan fan_duty RW 7000_4404h Fan 1 7000_4804h Fan 2 7 0 Fan commanded duty cycle when operating in duty cycle mode Note fan_duty 0xFF overri...

Page 312: ...3 FAN2 enable 0 FAN2 disabled 1 FAN2 enabled 2 FAN2 control mode select Not supported by default FW patch Set to 0 for correct functioning of FAN_COMMAND_2 when in duty cycle mode as selected by regi...

Page 313: ...75 percent C0FFh 256 256 100 percent note FFh case overrides to 100 percent duty READ_FAN_SPEED _1 R Word 90h 15 0 Returns the measured FAN1 speed in RPM in the LINEAR11 format with exponent defined b...

Page 314: ...lt1_func pwm3_func etc Table 85 shows the programming options for the multipurpose digital IO pins showing the differences in pin numbering for the variants XDPP1100 Q040 and XDPP1100 Q024 The program...

Page 315: ...PWM3 25 15 PWM3 GPIO0 1 GPIO1 1 External sync N A N A N A N A PWM4 26 16 PWM4 GPIO0 2 GPIO1 2 External sync N A N A N A N A PWM5 27 17 PWM5 GPIO0 3 GPIO1 3 External sync UART_RX N A N A N A PWM6 28 18...

Page 316: ...ROM FW This is due to an erratum affecting all currently available XDPP1100 versions Therefore it should be noted that this section describes the actual behavior rather than the intended behavior Func...

Page 317: ...n_name _pd enables a weak pull down resistor pin_name _pu_n enables a weak pull up resistor pin_name _ppen selects between an open drain or CMOS output stage The pins SCL SDA and SMBALERT have special...

Page 318: ...own disabled 1 Pull down enabled common bpwrgd_pu_n RW 7000_3004h 10 Pin BPWRGD weak pull up enable 0 Pull up enabled 1 Pull up disabled common bpwrgd_ppen RW 7000_3004h 11 Pin BPWRGD output buffer CM...

Page 319: ...04h 26 24 Pin FAULT2 function definition 0 FAULT2 GPIO1 2 digital IO 1 GPIO0 2 digital IO 2 GPIO1 2 digital IO 3 SYNC digital IO 4 FAN2_TACH digital input 5 SCL2 digital IO 6 UARTTXD digital output 7...

Page 320: ...pwrgd_pu_n RW 7000_3008h 10 Pin PWRGD weak pull up enable 0 Pull up enabled 1 Pull up disabled common pwrgd_ppen RW 7000_3008h 11 Pin PWRGD output buffer CMOS open drain select 0 Open drain output 1 C...

Page 321: ...d select 0 1 8 V CMOS input 1 3 3 V CMOS input common sda_pd RW 7000_3008h 26 Pin SDA weak pull down enable 0 Pull down disabled 1 Pull down enabled common sda_en_3v3 RW 7000_3008h 27 Pin SDA 1 8 V 3...

Page 322: ...M3 function definition 0 PWM3 digital output 1 GPIO0 1 digital IO 2 GPIO1 1 digital IO 3 SYNC digital IO 4 to 7 Not used common pwm3_pd RW 7000_300Ch 15 Pin PWM3 weak pull down enable 0 Pull down disa...

Page 323: ...MOS open drain select 0 Open drain output 1 CMOS output common pwm6_func RW 7000_3010h 2 0 Pin PWM6 function definition 0 PWM6 digital output 1 GPIO0 4 digital IO 2 GPIO1 4 digital IO 3 SYNC digital I...

Page 324: ...bled common pwm8_pu_n RW 7000_3010h 16 Pin PWM8 weak pull up enable 0 Pull up enabled 1 Pull up disabled common pwm8_ppen RW 7000_3010h 17 Pin PWM8 output buffer CMOS open drain select 0 Open drain ou...

Page 325: ...ate biasing enabled integrated power stage usage common force_pwm56_in_en_n RW 7000_3010h 31 For test use only Set to 1 for normal operation 0 Force enable the input buffers on PWM5 PWM6 test only 1 P...

Page 326: ...i state biasing disabled typical usage 1 Tri state biasing enabled integrated power stage usage common sync_dir_out RW 7000_3014h 13 Defines direction of pin mapped to SYNC function 0 SYNC mapped pin...

Page 327: ...anual 327 of 562 V 1 0 2021 08 25 XDPP1100 technical reference manual Digital power controller IO muxing Peripheral Field name Access Address Bits Description 01h GPIO1 0 deglitch enabled 02 FFh Not a...

Page 328: ...BA bus protocol in which two AHB masters Cortex M0 and DMA access all peripherals through an Arm bus matrix The main features of the bus matrix are It allows concurrent access when the target peripher...

Page 329: ...t computing RISC processor with a von Neumann architecture single bus interface It uses an instruction set defined in the ARMv6 architecture with Thumb and Thumb 2 support Thumb 2 technology extended...

Page 330: ...memory address input The NVIC interrupt sources comes from several CPUS resources DMA controller DTIMER 1 2 3 WDT GPIOs 0 1 PMBus I2 C UART OTP module Control module The following interrupts table Ta...

Page 331: ...INT6 RAMP0_T2 EXT1 6 0000_0058h INT7 RAMP1_T1 EXT2 7 0000_005Ch INT8 RAMP1_T2 EXT3 8 0000_0060h INT9 CAL_ALL_DONE EXT4 9 0000_0064h INT10 PWM_IN EXT5 10 0000_0068h INT11 N A EXT6 11 0000_006Ch INT12 W...

Page 332: ...FFFh 48 kB Reserved 1002_0000h 1002_FFFFh 64 kB OTP 1003_0000h 1003_FFFFh 64 kB OTP replica 1004_0000h 1004_FFFFh Reserved 1005_0000h 1005_3FFFh 16 kB RAM1 replica M2 1005_4000h 1005_7FFFh 16 kB RAM1...

Page 333: ...6 kB memory size 18 bit address decoding allowing the memory replica and selecting by FW the proper space can grant a contiguous memory space 2005_C000h 2006_3FFFh 15 2 3 Remapping feature In microcon...

Page 334: ...kB RAM1 replica 1005_C000h 1005_FFFFh 16 kB RAM1 1006_0000h 1006_3FFFh 16 kB RAM2 M1 1006_4000h 1006_7FFFh 16 kB RAM2 replica 1006_8000h 1006_BFFFh 16 kB RAM2 replica 1006_C000h 1006_FFFFh 16 kB RAM2...

Page 335: ...and the resets of all peripherals accessed by the processor Cortex M0 15 3 1 System controller unit The SCU configures all the miscellaneous functions of the CPUS functions in particular it enables d...

Page 336: ...intain OTP APB peripheral register values on soft reset CPUS_CFG SEL_SRC_DTIMER3 2_KRN_CLK RW 4000_0000h 12 Select the source of DTIMER32_KERNEL_CLK 0 Internal CPUS clock source 1 Loop 1 Fswitch rate...

Page 337: ...GPIO0_IRQ to wakeup CPUS when in the power down or hibernate state 0 CPUS GPIO0_IRQ wakeup source is disabled 1 CPUS GPIO0_IRQ wakeup source is enabled CPUS_CFG EN_GPIO1_WKUP RW 4000_0000h 23 Enable...

Page 338: ...FG_SE T SEL_SRC_DTIMER3 2_KRN_CLK W 4000_0004h 12 Select the source of DTIMER32_KERNEL_CLK 0 No change to existing value 1 Loop 1 Fswitch rate clock CPUS_CFG_SE T SEL_SRC_DTIMER3 1_KRN_CLK W 4000_0004...

Page 339: ...r hibernate state 0 No change to existing value 1 CPUS GPIO0_IRQ wakeup source is enabled CPUS_CFG_SE T EN_GPIO1_WKUP W 4000_0004h 23 Enable internal source GPIO1_IRQ to wake up CPUS when in the power...

Page 340: ...1_KRN_CLK W 4000_0008h 13 Select the source of DTIMER31_KERNEL_CLK 0 No change to existing state 1 Internal CPUS clock source CPUS_CFG_CL R SEL_SRC_DTIMER2 2_KRN_CLK W 4000_0008h 14 Select the source...

Page 341: ...n the power down or hibernate state 0 No change to existing value 1 CPUS GPIO1_IRQ wakeup source is disabled NMI_SRC_EN EXT0_NMI_EN RW 4000_000Ch 0 External EXT0_IRQn NMI control 0 Disabled 1 Enabled...

Page 342: ...I control 0 Disabled 1 Enabled NMI_SRC_EN DTIMER3_0_NMI_E N RW 4000_000Ch 17 DTIMER_31 NMI control 0 Disabled 1 Enabled NMI_SRC_EN DTIMER3_1_NMI_E N RW 4000_000Ch 18 DTIMER_32 NMI control 0 Disabled 1...

Page 343: ...trol 0 Disabled 1 Enabled SPARE_FF SPARE_FF RW 4000_0020h 31 0 Spare register 15 3 2 Clock generator unit The clock generation unit CGU generates and controls the clock signals of the CPUS section of...

Page 344: ...if_per_clk DTIMER_clk WDT_clk HOSC_clk DIV Alpha_clk RAM1 AHB2APB APB PER or Apb_per_clk Cnfg_dma_clk SVID Bif_per_svid_clk Bif_per_pmbus_clk SSP Bif_per_ssp_clk CortexM0IM FCLK HCLK DCLK SCLK Amba_cl...

Page 345: ...rt_clk BIF PER UART peripheral 100 100 cnfg_clk CPU APB PER bridge 100 100 cnfg_dma_clk DMA config port 100 100 cnfg_otp1_w_clk OTP interface peripheral 100 100 otp_kernel_clk OTP kernel 25 100 apb_pe...

Page 346: ...nel_clk KRN_CLK_DIV_CTRL pmbus_kernel_clk_div 4 0 PMBus logic core clock divider dtimer1_kernel_clk KRN_CLK_DIV_CTRL dtimer1_kernel_clk_div 4 0 DTIMER1 counters clock divider dtimer2_kernel_clk KRN_CL...

Page 347: ...US_EN signal will gate the main clock forcing the CPUS to enter the hibernate state if it has not already a high level CPUS_EN signal will remove the clock gate HWEN_CLK 1 recovering the previous CPUS...

Page 348: ...LK_DI V_CTRL alpha_clk_div RW 4000_2000h 4 0 This register configures the divider of the main input gated clock source hosc_clk_gated The divide ratio is equal to alpha_clk_div 4 0 1 For example the r...

Page 349: ...DTIMER2 kernel clock The divide ratio is equal to dtimer2_kernel_clk_div 4 0 1 For example the reset setting dtimer2_kernel_clk_div 4 0 24 generates a default clock frequency of dtimer2_kernel_clk al...

Page 350: ...ck gating control has been enabled Note The primary clock gating is performed if this bit is set The KILL_ME_SOFTLY bit of the HOSC_SW_CLK_GATING_CTRL register is also set Make sure to enable an exter...

Page 351: ...lk and bif_per_clk Note The CRC32 peripheral is using the SVID slot so this actually controls the CRC32 clock 0 Clock bif_per_svid_clk is off 1 Clock bif_per_svid_clk and bif_per_clk are live CLK_EN_C...

Page 352: ...ble bit for the clock gpio0_clk and apb_per_clk 0 Clock gpio0_clk is off 1 Clock gpio0_clk and apb_per_clk are live CLK_EN_CTRL gpio1_clk_g RW 4000_2010h 22 Enable bit for the clock gpio1_clk and apb_...

Page 353: ...W 4000_2014h 1 Enable rom_clk clock gating when Cortex M0 enters sleep state 0 Clock rom_clk is not gated by CM0 power state status 1 Clock rom_clk is gated when CM0 is in sleep state CLK_SLEEP_M SK_C...

Page 354: ...1 Enable bif_reg_clk clock gating when Cortex M0 enters sleep state 0 Clock bif_reg_clk is not gated by CM0 power state status 1 Clock bif_reg_clk is gated when CM0 is in sleep state CLK_SLEEP_M SK_CN...

Page 355: ...mer1_clk is gated when CM0 is in sleep state CLK_SLEEP_M SK_CNFG se_dtimer2_clk_g RW 4000_2014h 18 Enable dtimer2_clk clock gating when Cortex M0 enters sleep state 0 Clock dtimer2_clk is not gated by...

Page 356: ...eep sleep if hosc_clk clock gating control has been enabled CLK_DEEP_SL EEP_MSK_CNF G dse_rom_clk_g RW 4000_2018h 1 Enable rom_clk clock gating when Cortex M0 enters deep sleep state 0 Clock rom_clk i...

Page 357: ...s deep sleep state 0 Clock cnfg_otp1_w_clk2 is not gated by CM0 power state status 1 Clock cnfg_otp1_w_clk2 is gated when CM0 is in deep sleep state CLK_DEEP_SL EEP_MSK_CNF G dse_cnfg_dma_clk_ g RW 40...

Page 358: ...is in deep sleep state CLK_DEEP_SL EEP_MSK_CNF G dse_bif_per_uart_c lk_g RW 4000_2018h 16 Enable bif_per_uart_clk clock gating when Cortex M0 enters deep sleep state 0 Clock bif_per_uart_clk is not ga...

Page 359: ...eep state 0 Clock gpio1_clk is not gated by CM0 power state status 1 Clock gpio1_clk is gated when CM0 is in deep sleep state HOSC_SW_CL K_GATING_CT RL kill_me_softly RW 4000_201Ch 0 Enable hosc_clk S...

Page 360: ...30h 2 Enable the ram1_clk clock 0 Status of ram1_clk clock is not affected 1 Enable ram1_clk clock CLK_EN_CTRL _SET ram2_clk_g W 4000_2030h 3 Enable the ram2_clk clock 0 Status of ram2_clk clock is no...

Page 361: ...2c_clk clock 0 Status of bif_per_i2c_clk clock is not affected 1 Enable bif_per_i2c_clk clock CLK_EN_CTRL _SET bif_per_uart_clk_g W 4000_2030h 16 Enable the bif_per_uart_clk clock 0 Status of bif_per_...

Page 362: ..._g W 4000_2030h 25 Enable the dtimer3_kernel_clk clock 0 Status of dtimer3_kernel_clk clock is not affected 1 Enable dtimer3_kernel_clk clock CLK_EN_CTRL _SET pmbus_kernel_clk_ g W 4000_2030h 26 Enabl...

Page 363: ...1 Disable amba_clk clock CLK_EN_CTRL _CLR dma_clk_g W 4000_2034h 5 Disable the dma_clk clock 0 Status of dma_clk clock is not affected 1 Disable dma_clk clock CLK_EN_CTRL _CLR cnfg_otp1_w_clk_g W 4000...

Page 364: ...dtimer1_clk clock is not affected 1 Disable dtimer1_clk clock CLK_EN_CTRL _CLR dtimer2_clk_g W 4000_2034h 18 Disable the dtimer2_clk clock 0 Status of dtimer2_clk clock is not affected 1 Disable dtime...

Page 365: ...2034h 27 Disable the otp_kernel_clk clock 0 Status of otp_kernel_clk clock is not affected 1 Disable otp_kernel_clk clock CLK_SLEEP_M SK_CNFG_SET se_hosc_clk_g W 4000_2038h 0 Enable hosc_clk clock gat...

Page 366: ...state 0 Clock dma_clk sleep state clock gating status unchanged 1 Enable clock dma_clk sleep state clock gating CLK_SLEEP_M SK_CNFG_SET se_cnfg_otp1_w_cl k_g W 4000_2038h 6 Enable cnfg_otp1_w_clk clo...

Page 367: ...00_2038h 14 Reserved CLK_SLEEP_M SK_CNFG_SET se_bif_per_i2c_clk_ g W 4000_2038h 15 Enable bif_per_i2c_clk clock gating when the Cortex M0 enters sleep state 0 Clock bif_per_i2c_clk sleep state clock g...

Page 368: ..._clk_g W 4000_2038h 21 Enable gpio2_clk clock gating when the Cortex M0 enters sleep state 0 Clock gpio2_clk sleep state clock gating status unchanged 1 Enable clock gpio2_clk sleep state clock gating...

Page 369: ...rtex M0 enters sleep state 0 Clock amba_clk sleep state clock gating status unchanged 1 Disable clock amba_clk sleep state clock gating CLK_SLEEP_M SK_CNFG_CLR se_dma_clk_g W 4000_203Ch 5 Disable dma_...

Page 370: ...Disable bif_per_pmbus_clk clock gating when the Cortex M0 enters sleep state 0 Clock bif_per_pmbus_clk sleep state clock gating status unchanged 1 Disable clock bif_per_pmbus_clk sleep state clock gat...

Page 371: ...SLEEP_M SK_CNFG_CLR se_wdt_clk_g W 4000_203Ch 20 Disable wdt_clk clock gating when the Cortex M0 enters sleep state 0 Clock wdt_clk sleep state clock gating status unchanged 1 Disable clock wdt_clk sl...

Page 372: ...Cortex M0 enters deep sleep state 0 Clock ram1_clk deep sleep state clock gating status unchanged 1 Enable clock ram1_clk deep sleep state clock gating CLK_DEEP_SL EEP_MSK_CNF G_SET dse_ram2_clk_g W 4...

Page 373: ...gating CLK_DEEP_SL EEP_MSK_CNF G_SET dse_bif_reg_clk_g W 4000_2040h 11 Enable bif_reg_clk clock gating when the Cortex M0 enters deep sleep state 0 Clock bif_reg_clk deep sleep state clock gating stat...

Page 374: ...ble clock bif_per_uart_clk deep sleep state clock gating CLK_DEEP_SL EEP_MSK_CNF G_SET dse_dtimer1_clk_g W 4000_2040h 17 Enable dtimer1_clk clock gating when the Cortex M0 enters deep sleep state 0 Cl...

Page 375: ...ting status unchanged 1 Enable clock gpio1_clk deep sleep state clock gating CLK_DEEP_SL EEP_MSK_CNF G_CLR dse_hosc_clk_g W 4000_2044h 0 Disable hosc_clk clock gating when Cortex M0 will enter the dee...

Page 376: ...ating CLK_DEEP_SL EEP_MSK_CNF G_CLR dse_dma_clk_g W 4000_2044h 5 Disable dma_clk clock gating when the Cortex M0 enters deep sleep state 0 Clock dma_clk deep sleep state clock gating status unchanged...

Page 377: ...NF G_CLR dse_bif_per_pmbus _clk_g W 4000_2044h 13 Disable bif_per_pmbus_clk clock gating when the Cortex M0 enters deep sleep state 0 Clock bif_per_pmbus_clk deep sleep state clock gating status uncha...

Page 378: ..._CLR dse_dtimer3_clk_g W 4000_2044h 19 Disable dtimer3_clk clock gating when the Cortex M0 enters deep sleep state 0 Clock dtimer3_clk deep sleep state clock gating status unchanged 1 Disable clock dt...

Page 379: ...3 CPUS reset tree CPU subsystem RGU Dma_rstn Bif_reg_rstn rstn SSP Hresetn Bif_per_ssp_rstn if_wdt_rstn Dly_rstn WDT Wdt_rst SWRST reg i_hresetn Module RST reg Clr FF FF Clk DMA OTP1_W Cnfg_otp1_w_rst...

Page 380: ...primary input source clock hosc_clk Figure 104 HW_PWD and SW_PWD signals are able to trigger internally to CPUS a logic reset state II_RSTN with RAMs and ROM in power down PWRONB and input clock hosc...

Page 381: ...propriate bits in the register RSTMODS 15 3 3 2 Software power down The CPUS can enter a power down reset state by executing a proper FW instruction WFE WFI FW power down needs to be enabled by EN_SWP...

Page 382: ...hat the last reset was a soft reset Figure 106 Software reset signal generation 15 3 3 4 RGU registers The relevant RGU related registers and their descriptions are provided in Table 96 Table 96 RGU r...

Page 383: ...the RSTMODS register 0 CPUS cannot be reset by SWRST bit 1 CPUS can be reset by SWRST bit SWRST_CTRL EN_SWRST RW 4000_1004h 0 The software reset control register is used to enable the CPU to reset th...

Page 384: ...al operation of the CRC32 1 Performs a reset of the CRC32 RSTMODS BIFPERPMBUSRST RW 4000_1008h 6 BIF PMBus PER IF reset bit To exercise a module reset FW has to set and clear the proper bit accordingl...

Page 385: ...08h 14 WDT module reset bit To exercise a module reset FW has to set and clear the proper bit accordingly 0 Normal operation of the WDT module 1 Performs a reset of the WDT module RSTMODS GPIO0RST RW...

Page 386: ...med by asserting the WKUP_IN signal if it has been enabled or the RSTN signal 0 CPUS cannot be powered down by using SW procedure 1 CPUS can be powered down by using SW procedure HW_PWDN_CT RL EN_HWPW...

Page 387: ...tus of module reset unchanged 1 Forces reset of module RSTMODS_SET BIFPERPMBUSRST W 4000_1020h 6 BIF PMBUS PER IF reset bit To exercise a module reset FW has to set and to clear the proper bit accordi...

Page 388: ...e proper bit accordingly 0 Status of module reset unchanged 1 Forces reset of module RSTMODS_SET GPIO0RST W 4000_1020h 15 GPIO0 module reset bit To exercise a module reset FW has to set and clear the...

Page 389: ...bit accordingly 0 Status of module reset unchanged 1 Release reset RSTMODS_CLR BIFPERSSPRST W 4000_1024h 7 Reserved RSTMODS_CLR BIFPERI2CRST W 4000_1024h 8 BIF I2 C PER IF reset bit To exercise a modu...

Page 390: ...has to set and clear the proper bit accordingly 0 Status of module reset unchanged 1 Release reset RSTMODS_CLR GPIO1RST W 4000_1024h 16 GPIO1 module reset bit To exercise a module reset FW has to set...

Page 391: ...ord access The SRAM memory BIST is a HW engine used during production to verify the proper functionality of the module self check functional test It reads and writes every memory cell macro using a sp...

Page 392: ...000h 0003_0000h and 1003_0000h All these regions point to the same physical memory space memory replicas Configuration registers can be accessed by the microcontroller starting from address 0x5002000...

Page 393: ...errupt MASK_INSTR_DONE 1b1 on INT_MASK register and waiting until the OTP shell triggers an interrupt then verifying that the right interrupt occurred checking INSTR_DONE field set on INT_ACTIVE regis...

Page 394: ...a BIST reset 5h09 BIST STRESS TEST Start a BIST stress test 5h0a BIST CLEAN ARRAY TEST Start a BIST clean array test 5h0b SETMODE MRB Data taken from READ_MRAB Write OTP MRB 5h0c SETMODE MR Data take...

Page 395: ...truction Writing the data into the OTP with a WRITE pulse with a timing defined in PROG_PULSE_REG field of OTP_PROG_C register Everything else READ1 soak and READ2 needs to be done manually with appro...

Page 396: ...ing for the OTP macro to assert the READ termination STATUS going high If STATUS is not asserted within this watchdog time to avoid deadlock the program is aborted and an error is flagged STAT registe...

Page 397: ...cle wait state The OTP module implements a prefetch FSM to mitigate the penalties on the access time After any access prefetch FSM automatically starts a read on the following OTP word caching 128 bit...

Page 398: ...quite ideal but the Arm Cortex M0 is based on a von Neumann architecture for which instruction and data interfaces are on the same bus It also does not support BURST memory access which can generate a...

Page 399: ...mpare status valid after direct access compare instruction STAT PRECH_STAT R 5002_0000h 9 Precharge status valid after direct access compare instruction STAT RD1_FL R 5002_0000h 16 READ1 fail indicato...

Page 400: ...y INSTR OTP_INSTR RW 5002_0008h 4 0 Indirect OTP access instruction 1 PROG and VERIFY 2 READ 3 PROG basic transaction 4 WRITE OTP data register 5 SETMODE MRA 6 CMP 7 PCH 8 BIST RESET 9 BIST STRESS TES...

Page 401: ...OTP READ1 during OTP programming READ2_MRAB MRB_READ2 RW 5002_0030h 15 0 MRB register setting to be used for OTP READ2 during OTP programming READ2_MRAB MRA_READ2 RW 5002_0030h 31 16 MRA register sett...

Page 402: ...Interrupt masked 1 Interrupt enabled INT_MASK MSK_INSTR_DONE RW 5002_0054h 1 Mask for INSTR_DONE 0 Interrupt masked 1 Interrupt enabled INT_MASK MSK_READ_FAULT RW 5002_0054h 2 Mask for READ_FAULT 0 In...

Page 403: ...OTP_CP_C VPP_WARMDOWN RW 5002_0068h 15 0 Charge pump warm down time in OTP kernel clocks OTP_CP_C VPP_WARMUP RW 5002_0068h 24 16 Charge pump warm up time in OTP kernel clocks OTP_READ_C READ_TIMEOUT...

Page 404: ...IST_ADDR_FAIL R 5002_0078h 28 16 Last OTP address in which BIST detected a FAIL 15 5 Memory management unit The memory management unit MMU module enables a configurable address remapping and a registe...

Page 405: ...o activate the address remapping logic When the EN_MMU bit is reset MMU is completely transparent the Cortex M0 address is directly propagated to the bus matrix The MMU has also a set of global bits o...

Page 406: ...M1 3 RAM2 MMU_LUT_RO M2_DATA PROT RW 4000_4008h 0 Defines the write protection of the target address block in the target memory space Any write attempt to a protected block will result in an illegal a...

Page 407: ...address block into which the ROM section is remapped MMU_LUT_RO M4_DATA BASE_ADR RW 4000_4010h 9 8 Defines the target memory space into which the ROM section is remapped 0 ROM 1 OTP 2 RAM1 3 RAM2 MMU...

Page 408: ...e Any write attempt to a protected block will result in an illegal access fault 0 Disable write protection 1 Enable write protection MMU_LUT_RO M7_DATA BLK_ADR RW 4000_401Ch 7 1 Defines the target add...

Page 409: ...emory space into which the ROM section is remapped 0 ROM 1 OTP 2 RAM1 3 RAM2 MMU_LUT_RO M10_DATA PROT RW 4000_4028h 0 Defines the write protection of the target address block in the target memory spac...

Page 410: ...ccess fault 0 Disable write protection 1 Enable write protection MMU_LUT_RO M12_DATA BLK_ADR RW 4000_4030h 7 1 Defines the target address block into which the ROM section is remapped MMU_LUT_RO M12_DA...

Page 411: ...1 3 RAM2 MMU_LUT_RO M15_DATA PROT RW 4000_403Ch 0 Defines the write protection of the target address block in the target memory space Any write attempt to a protected block will result in an illegal a...

Page 412: ...address block into which the ROM section is remapped MMU_LUT_RO M17_DATA BASE_ADR RW 4000_4044h 9 8 Defines the target memory space into which the ROM section is remapped 0 ROM 1 OTP 2 RAM1 3 RAM2 MMU...

Page 413: ...Any write attempt to a protected block will result in an illegal access fault 0 Disable write protection 1 Enable write protection MMU_LUT_RO M20_DATA BLK_ADR RW 4000_4050h 7 1 Defines the target add...

Page 414: ...memory space into which the ROM section is remapped 0 ROM 1 OTP 2 RAM1 3 RAM2 MMU_LUT_RO M23_DATA PROT RW 4000_405Ch 0 Defines the write protection of the target address block in the target memory spa...

Page 415: ...ccess fault 0 Disable write protection 1 Enable write protection MMU_LUT_RO M25_DATA BLK_ADR RW 4000_4064h 7 1 Defines the target address block into which the ROM section is remapped MMU_LUT_RO M25_DA...

Page 416: ...1 3 RAM2 MMU_LUT_RO M28_DATA PROT RW 4000_4070h 0 Defines the write protection of the target address block in the target memory space Any write attempt to a protected block will result in an illegal a...

Page 417: ...address block into which the ROM section is remapped MMU_LUT_RO M30_DATA BASE_ADR RW 4000_4078h 9 8 Defines the target memory space into which the ROM section is remapped 0 ROM 1 OTP 2 RAM1 3 RAM2 MMU...

Page 418: ...Any write attempt to a protected block will result in an illegal access fault 0 Disable write protection 1 Enable write protection MMU_LUT_RO M33_DATA BLK_ADR RW 4000_4084h 7 1 Defines the target add...

Page 419: ...memory space into which the ROM section is remapped 0 ROM 1 OTP 2 RAM1 3 RAM2 MMU_LUT_RO M36_DATA PROT RW 4000_4090h 0 Defines the write protection of the target address block in the target memory spa...

Page 420: ...ccess fault 0 Disable write protection 1 Enable write protection MMU_LUT_RO M38_DATA BLK_ADR RW 4000_4098h 7 1 Defines the target address block into which the ROM section is remapped MMU_LUT_RO M38_DA...

Page 421: ...1 3 RAM2 MMU_LUT_RO M41_DATA PROT RW 4000_40A4h 0 Defines the write protection of the target address block in the target memory space Any write attempt to a protected block will result in an illegal a...

Page 422: ...address block into which the ROM section is remapped MMU_LUT_RO M43_DATA BASE_ADR RW 4000_40ACh 9 8 Defines the target memory space into which the ROM section is remapped 0 ROM 1 OTP 2 RAM1 3 RAM2 MMU...

Page 423: ...Any write attempt to a protected block will result in an illegal access fault 0 Disable write protection 1 Enable write protection MMU_LUT_RO M46_DATA BLK_ADR RW 4000_40B8h 7 1 Defines the target add...

Page 424: ...memory space into which the ROM section is remapped 0 ROM 1 OTP 2 RAM1 3 RAM2 MMU_LUT_RO M49_DATA PROT RW 4000_40C4h 0 Defines the write protection of the target address block in the target memory spa...

Page 425: ...ccess fault 0 Disable write protection 1 Enable write protection MMU_LUT_RO M51_DATA BLK_ADR RW 4000_40CCh 7 1 Defines the target address block into which the ROM section is remapped MMU_LUT_RO M51_DA...

Page 426: ...1 3 RAM2 MMU_LUT_RO M54_DATA PROT RW 4000_40D8h 0 Defines the write protection of the target address block in the target memory space Any write attempt to a protected block will result in an illegal a...

Page 427: ...address block into which the ROM section is remapped MMU_LUT_RO M56_DATA BASE_ADR RW 4000_40E0h 9 8 Defines the target memory space into which the ROM section is remapped 0 ROM 1 OTP 2 RAM1 3 RAM2 MMU...

Page 428: ...Any write attempt to a protected block will result in an illegal access fault 0 Disable write protection 1 Enable write protection MMU_LUT_RO M59_DATA BLK_ADR RW 4000_40ECh 7 1 Defines the target add...

Page 429: ...memory space into which the ROM section is remapped 0 ROM 1 OTP 2 RAM1 3 RAM2 MMU_LUT_RO M62_DATA PROT RW 4000_40F8h 0 Defines the write protection of the target address block in the target memory spa...

Page 430: ...ccess fault 0 Disable write protection 1 Enable write protection MMU_LUT_RO M64_DATA BLK_ADR RW 4000_4100h 7 1 Defines the target address block into which the ROM section is remapped MMU_LUT_RO M64_DA...

Page 431: ...1 3 RAM2 MMU_LUT_RO M67_DATA PROT RW 4000_410Ch 0 Defines the write protection of the target address block in the target memory space Any write attempt to a protected block will result in an illegal a...

Page 432: ...address block into which the ROM section is remapped MMU_LUT_RO M69_DATA BASE_ADR RW 4000_4114h 9 8 Defines the target memory space into which the ROM section is remapped 0 ROM 1 OTP 2 RAM1 3 RAM2 MMU...

Page 433: ...Any write attempt to a protected block will result in an illegal access fault 0 Disable write protection 1 Enable write protection MMU_LUT_RO M72_DATA BLK_ADR RW 4000_4120h 7 1 Defines the target add...

Page 434: ...memory space into which the ROM section is remapped 0 ROM 1 OTP 2 RAM1 3 RAM2 MMU_LUT_RO M75_DATA PROT RW 4000_412Ch 0 Defines the write protection of the target address block in the target memory spa...

Page 435: ...ccess fault 0 Disable write protection 1 Enable write protection MMU_LUT_RO M77_DATA BLK_ADR RW 4000_4134h 7 1 Defines the target address block into which the ROM section is remapped MMU_LUT_RO M77_DA...

Page 436: ...RAM1 3 RAM2 MMU_LUT_OT P0_DATA PROT RW 4000_4200h 0 Defines the write protection of the target address block in the target memory space Any write attempt to a protected block will result in an illegal...

Page 437: ...address block into which the OTP section is remapped MMU_LUT_OT P2_DATA BASE_ADR RW 4000_4208h 9 8 Defines the target memory space into which the OTP section is remapped 0 ROM 1 OTP 2 RAM1 3 RAM2 MMU...

Page 438: ...e Any write attempt to a protected block will result in an illegal access fault 0 Disable write protection 1 Enable write protection MMU_LUT_OT P5_DATA BLK_ADR RW 4000_4214h 7 1 Defines the target add...

Page 439: ...memory space into which the OTP section is remapped 0 ROM 1 OTP 2 RAM1 3 RAM2 MMU_LUT_OT P8_DATA PROT RW 4000_4220h 0 Defines the write protection of the target address block in the target memory spa...

Page 440: ...cess fault 0 Disable write protection 1 Enable write protection MMU_LUT_OT P10_DATA BLK_ADR RW 4000_4228h 7 1 Defines the target address block into which the OTP section is remapped MMU_LUT_OT P10_DAT...

Page 441: ...1 3 RAM2 MMU_LUT_OT P13_DATA PROT RW 4000_4234h 0 Defines the write protection of the target address block in the target memory space Any write attempt to a protected block will result in an illegal a...

Page 442: ...address block into which the OTP section is remapped MMU_LUT_OT P15_DATA BASE_ADR RW 4000_423Ch 9 8 Defines the target memory space into which the OTP section is remapped 0 ROM 1 OTP 2 RAM1 3 RAM2 MMU...

Page 443: ...Any write attempt to a protected block will result in an illegal access fault 0 Disable write protection 1 Enable write protection MMU_LUT_OT P18_DATA BLK_ADR RW 4000_4248h 7 1 Defines the target add...

Page 444: ...memory space into which the OTP section is remapped 0 ROM 1 OTP 2 RAM1 3 RAM2 MMU_LUT_OT P21_DATA PROT RW 4000_4254h 0 Defines the write protection of the target address block in the target memory spa...

Page 445: ...ccess fault 0 Disable write protection 1 Enable write protection MMU_LUT_OT P23_DATA BLK_ADR RW 4000_425Ch 7 1 Defines the target address block into which the OTP section is remapped MMU_LUT_OT P23_DA...

Page 446: ...1 3 RAM2 MMU_LUT_OT P26_DATA PROT RW 4000_4268h 0 Defines the write protection of the target address block in the target memory space Any write attempt to a protected block will result in an illegal a...

Page 447: ...address block into which the OTP section is remapped MMU_LUT_OT P28_DATA BASE_ADR RW 4000_4270h 9 8 Defines the target memory space into which the OTP section is remapped 0 ROM 1 OTP 2 RAM1 3 RAM2 MMU...

Page 448: ...Any write attempt to a protected block will result in an illegal access fault 0 Disable write protection 1 Enable write protection MMU_LUT_OT P31_DATA BLK_ADR RW 4000_427Ch 7 1 Defines the target add...

Page 449: ...memory space into which the OTP section is remapped 0 ROM 1 OTP 2 RAM1 3 RAM2 MMU_LUT_OT P34_DATA PROT RW 4000_4288h 0 Defines the write protection of the target address block in the target memory spa...

Page 450: ...ccess fault 0 Disable write protection 1 Enable write protection MMU_LUT_OT P36_DATA BLK_ADR RW 4000_4290h 7 1 Defines the target address block into which the OTP section is remapped MMU_LUT_OT P36_DA...

Page 451: ...1 3 RAM2 MMU_LUT_OT P39_DATA PROT RW 4000_429Ch 0 Defines the write protection of the target address block in the target memory space Any write attempt to a protected block will result in an illegal a...

Page 452: ...address block into which the OTP section is remapped MMU_LUT_OT P41_DATA BASE_ADR RW 4000_42A4h 9 8 Defines the target memory space into which the OTP section is remapped 0 ROM 1 OTP 2 RAM1 3 RAM2 MMU...

Page 453: ...Any write attempt to a protected block will result in an illegal access fault 0 Disable write protection 1 Enable write protection MMU_LUT_OT P44_DATA BLK_ADR RW 4000_42B0h 7 1 Defines the target add...

Page 454: ...memory space into which the OTP section is remapped 0 ROM 1 OTP 2 RAM1 3 RAM2 MMU_LUT_OT P47_DATA PROT RW 4000_42BCh 0 Defines the write protection of the target address block in the target memory spa...

Page 455: ...ccess fault 0 Disable write protection 1 Enable write protection MMU_LUT_OT P49_DATA BLK_ADR RW 4000_42C4h 7 1 Defines the target address block into which the OTP section is remapped MMU_LUT_OT P49_DA...

Page 456: ...1 3 RAM2 MMU_LUT_OT P52_DATA PROT RW 4000_42D0h 0 Defines the write protection of the target address block in the target memory space Any write attempt to a protected block will result in an illegal a...

Page 457: ...address block into which the OTP section is remapped MMU_LUT_OT P54_DATA BASE_ADR RW 4000_42D8h 9 8 Defines the target memory space into which the OTP section is remapped 0 ROM 1 OTP 2 RAM1 3 RAM2 MMU...

Page 458: ...Any write attempt to a protected block will result in an illegal access fault 0 Disable write protection 1 Enable write protection MMU_LUT_OT P57_DATA BLK_ADR RW 4000_42E4h 7 1 Defines the target add...

Page 459: ...memory space into which the OTP section is remapped 0 ROM 1 OTP 2 RAM1 3 RAM2 MMU_LUT_OT P60_DATA PROT RW 4000_42F0h 0 Defines the write protection of the target address block in the target memory spa...

Page 460: ...ccess fault 0 Disable write protection 1 Enable write protection MMU_LUT_OT P62_DATA BLK_ADR RW 4000_42F8h 7 1 Defines the target address block into which the OTP section is remapped MMU_LUT_OT P62_DA...

Page 461: ...1 3 RAM2 MMU_LUT_RA M11_DATA PROT RW 4000_4404h 0 Defines the write protection of the target address block in the target memory space Any write attempt to a protected block will result in an illegal a...

Page 462: ...dress block into which the RAM1 section is remapped MMU_LUT_RA M13_DATA BASE_ADR RW 4000_440Ch 9 8 Defines the target memory space into which the RAM1 section is remapped 0 ROM 1 OTP 2 RAM1 3 RAM2 MMU...

Page 463: ...Any write attempt to a protected block will result in an illegal access fault 0 Disable write protection 1 Enable write protection MMU_LUT_RA M16_DATA BLK_ADR RW 4000_4418h 7 1 Defines the target addr...

Page 464: ...emory space into which the RAM1 section is remapped 0 ROM 1 OTP 2 RAM1 3 RAM2 MMU_LUT_RA M19_DATA PROT RW 4000_4424h 0 Defines the write protection of the target address block in the target memory spa...

Page 465: ...ess fault 0 Disable write protection 1 Enable write protection MMU_LUT_RA M111_DATA BLK_ADR RW 4000_442Ch 7 1 Defines the target address block into which the RAM1 section is remapped MMU_LUT_RA M111_D...

Page 466: ...3 RAM2 MMU_LUT_RA M114_DATA PROT RW 4000_4438h 0 Defines the write protection of the target address block in the target memory space Any write attempt to a protected block will result in an illegal a...

Page 467: ...ddress block into which the RAM2 section is remapped MMU_LUT_RA M20_DATA BASE_ADR RW 4000_4500h 9 8 Defines the target memory space into which the RAM2 section is remapped 0 ROM 1 OTP 2 RAM1 3 RAM2 MM...

Page 468: ...Any write attempt to a protected block will result in an illegal access fault 0 Disable write protection 1 Enable write protection MMU_LUT_RA M23_DATA BLK_ADR RW 4000_450Ch 7 1 Defines the target addr...

Page 469: ...emory space into which the RAM2 section is remapped 0 ROM 1 OTP 2 RAM1 3 RAM2 MMU_LUT_RA M26_DATA PROT RW 4000_4518h 0 Defines the write protection of the target address block in the target memory spa...

Page 470: ...cess fault 0 Disable write protection 1 Enable write protection MMU_LUT_RA M28_DATA BLK_ADR RW 4000_4520h 7 1 Defines the target address block into which the RAM2 section is remapped MMU_LUT_RA M28_DA...

Page 471: ...3 RAM2 MMU_LUT_RA M211_DATA PROT RW 4000_452Ch 0 Defines the write protection of the target address block in the target memory space Any write attempt to a protected block will result in an illegal a...

Page 472: ...ress block into which the RAM2 section is remapped MMU_LUT_RA M213_DATA BASE_ADR RW 4000_4534h 9 8 Defines the target memory space into which the RAM2 section is remapped 0 ROM 1 OTP 2 RAM1 3 RAM2 MMU...

Page 473: ...ch the RAM2 section is remapped MMU_LUT_RA M215_DATA BASE_ADR RW 4000_453Ch 9 8 Defines the target memory space into which the RAM2 section is remapped 0 ROM 1 OTP 2 RAM1 3 RAM2 MMU_PER_SP ACE PER RW...

Page 474: ...it position enables protection while a 0 retains the existing protection setting 0 Not used 1 WDT DTIMER GPIO 2 UART I2 C SSP PMBus 3 Trim 4 Analog 5 VSP0 6 VSP1 7 VSP2 8 VCTRL0 9 VCTRL1 10 PID0 11 PI...

Page 475: ...24 FAULTCOM 25 TEST 25 TESTSTAT 25 Reserved MMU_CNFG EN_MMU RW 4000_4700h 0 MMU function enable disable 0 Disable MMU function 1 Enable MMU function MMU_CNFG EN_LOAD_MMU_TA BLE RW 4000_4700h 1 MMU tab...

Page 476: ...using a 32 bit address bus and 32 bit data bus It has a configurable number of DMA channels Each DMA channel has dedicated handshake signals Each DMA channel has a programmable priority level Each pr...

Page 477: ...requests It indicates which channel is active It indicates when a channel is complete It indicates when an error has occurred on the AHB Lite interface It enables slow peripherals to stall the comple...

Page 478: ...Fh PMBus CRC I2 C M7 7010_0000h FFFF_FFFFh Reserved Remapping does not impact the DMA memory map 15 6 3 DMA channel assignment DMA channel assignment is shown in Table 104 The DMA macro supports singl...

Page 479: ...ate 2 Reading source data end pointer 3 Reading destination data end pointer 4 Reading source data 5 Writing destination data 6 Waiting for DMA request to clear 7 Writing channel controller data 8 Sta...

Page 480: ...base address of the primary data structure DMA_ALT_CTR L_BASE_PTR ALT_CTRL_BASE_P TR R 5000_000Ch 31 0 Returns the base address of the alternate data structure CHNL_WAITON REQ_STATUS DMA_WAITONREQ_ S...

Page 481: ...rating DMA requests on channel x The controller performs 2R transfers only DMA_CHNL_U SEBURST_CLR CHNL_USEBURST_ CLR W 5000_001Ch 15 0 This write only register enables dma_sreq to generate requests Fo...

Page 482: ...the corresponding channels For each bit x On READ 0 Channel x is disabled 1 Channel x is enabled On WRITE 0 No effect Use the CHNL_ENABLE_CLR Register to disable a channel 1 Enables channel x DMA_CHNL...

Page 483: ...This register enables you to configure a DMA channel to use the high priority level Reading the register returns the status of the channel priority mask For each bit x On READ 0 DMA channel x is usin...

Page 484: ...MA_CH_MSK RW 5000_1004h 15 0 DMA channel interrupt mask For each bit x 0 DMA channel x interrupt disabled 0 DMA channel x interrupt enabled IMSC DMA_ERR_MSK RW 5000_1004h 31 Mask bit for DMA error int...

Page 485: ...00h GPIO pin mapping on primary XDPP1100 IOs is summarized in Table 86 The GPIO block is an Arm PrimeCell IP PL061 extensive documentation can be found in the Arm PrimeCell General Purpose Input Outpu...

Page 486: ...alue A read from GPIODATA returns the last bit value written if the respective pins are configured as output or it returns the value on the corresponding input GPIN bit when these are configured as in...

Page 487: ...ister Bits set to high in GPIOIEV configure the corresponding pin to detect rising edges or high levels depending on the corresponding bit value in GPIOIS Clearing a bit configures the pin to detect f...

Page 488: ...lect the status of input lines triggering an interrupt Bits read as low indicate that either no interrupt has been generated or the interrupt is masked disabled by GPIOIE INTENA This register is read...

Page 489: ...r0 R 6004_0FE4h 6005_0FE4h 7 4 DesignerID 3 0 Together with the upper bits from Designer1 DesignerID 7 0 identifies the peripheral designer In this case it returns 0x41 indicating Arm Ltd GPIOPeriphID...

Page 490: ...4 4 Watchdog unit The watchdog module is based around a 32 bit downcounter that is initialized from the reload register WDOGLOAD The watchdog clock generates a regular interrupt WDOGINT depending on...

Page 491: ...is written to the counter starts decrementing immediately The minimum value write value is 1 WDOGVALUE VALUE R 6000_0004h 31 0 Returns the current value of the watchdog counter WDOGCONTR OL INTEN RW 6...

Page 492: ...s the masked interrupt status which is the logical AND of the raw interrupt status and WDOGCONTROL INTEN 0 Masked interrupt not asserted 1 Masked interrupt asserted WDOGLOCK LOCKEN RW 6000_0C00h 0 Wat...

Page 493: ...Designer1 DesignerID 7 0 identifies the peripheral designer In this case it returns 0x41 indicating Arm Ltd WDOGPERIPHI D2 Designer1 R 6000_0FE8h 3 0 DesignerID 7 4 Together with the lower bits from...

Page 494: ...it counter size and one of three timer modes using the control register The operation of each timer module is identical It has one of three timer modes Free running The counter wraps after reaching it...

Page 495: ...unter is to decrement This is the value used to reload the counter when periodic mode is enabled and the current count reaches zero When this register is written to directly the current count is immed...

Page 496: ...e decrementing counter TIM_SEQ0_TIM ERCONTROL ONESHOT RW 6001_0008h 6002_0008h 6003_0008h 0 One shot count Select one shot or wrapping counter mode 0 Wrapping mode default 1 One shot mode TIM_SEQ0_TIM...

Page 497: ...ALUE RW 6001_0018h 6002_0018h 6003_0018h 31 0 TIM_SEQ0_TIMERBGLOAD contains the value used to reload the counter when periodic mode is enabled and the current count reaches zero This register provides...

Page 498: ...es effect for periodic mode after the next time the counter reaches zero TIM_SEQ1_TIM ERVALUE VALUE R 6001_0024h 6002_0024h 6003_0024h 31 0 Returns the current value of the decrementing counter TIM_SE...

Page 499: ...6003_0034h 0 Timer interrupt status Reflects the counter interrupt status after masking by INTEN 0 Interrupt disabled or not asserted 1 Interrupt enabled and asserted TIM_SEQ1_TIM ERBGLOAD BVALUE RW 6...

Page 500: ...nal indicating when an I2 C PMBus transaction is in progress signal will be asserted from the start event until the stop event Finally the PMB_I2CF operates only when the PHY is enabled The PMB_APB bl...

Page 501: ...116 PMBus clock scheme 15 10 2 Interrupt generation The PMBus interrupt is generated at every I2 C phase completion it is generated at the detection of a start event start_irq when the first byte aft...

Page 502: ...upt source Write 1 on the interrupt source in the ISR register ISR_REG IE_PMB o Enable the PMBus PHY to operate set CNFG_REG EN_PHY to 1 At this point the PMBus will start to process all the incoming...

Page 503: ...te 1 into ISR I_PMB Read the status of the ACK signal STATUS_REG ACK_STATUS If ACK_STATUS 1 the command is valid then depending on the received command load DATA_LUT with a valid data range mask read...

Page 504: ...upt flag isr isr Load Adr_lut with a valid set of address Select Ack Source ADR_HIT Trigger CTRL_RX Load Data_lut with a valid command masks Select Ack Source DATA_HIT Trigger CTRL_RX Manage Command R...

Page 505: ...K signal STATUS_REG ACK_STATUS If ACK_STATUS 1 command is valid then depending on the received command load DATA_LUT with a valid data range mask read the data byte this is the CMD_BYTE select the pro...

Page 506: ...R with the expected data set the number of bytes to be transmitted then trigger the FSM to move forward Wait for irq_tx or irq_stop interrupt assertion If irq_tx clear the interrupt event write 1 into...

Page 507: ...irq_rx Clear Interrupt flag isr isr Read Command command rxdata data Command exist _expected_byte cmd_table command bytes Write_pec_trans false Irq_tx_after_start Clear Interrupt flag isr isr Read Cal...

Page 508: ...ice o if true set ACK write TXDATA with device SLAVE_ADDRESS associated with the SMBALERT clear the SMBALERT and trigger the FSM o if false set NACK and trigger the FSM to move forward Figure 120 ARA...

Page 509: ...rupt generation 0 NACK 1 ACK STATUS TOO_FEW_BITS R 7008_0000h 3 Reflects the flag status indicating a transaction termination not aligned to the byte 0 All transactions have been aligned to bytes 1 Tr...

Page 510: ...rnally for too long 1 SCL was held high externally for too long CNFG EN_PHY RW 7008_0004h 0 Enable Disable PMBus PHY operation When this bit is cleared the clock of the I2 CF section is frozen and the...

Page 511: ...reen out the transactions not belonging to the device the screen out will take place only on first start after stop and not for restart 0 START_IRQ interrupt always occurs at the start phase then the...

Page 512: ...atchdog timeout value This number is multiplied by 256 PMBUS_Kernel_clk period nominal 40 ns If the SCL clock line is continuously held low or high for longer than this time a timeout event is generat...

Page 513: ...T RW 7008_000Ch 16 10 Set the address generating the SMBALERT This address will be automatically shifted out as soon as an ARA address is detected and the SMBALERT is asserted CTRL_RX RX_TRIGGER W 700...

Page 514: ...operation selection By writing on this field it is possible to manage multiple DATA_LUTs with a single access 0 No operation 1 Clear all the DATA_LUTs 2 Set all DATA_LUTs in the index interval MIN_RAN...

Page 515: ...e transmitted byte or configured BYTE_TO_TX 0 Don t care 1 Drop byte transmission CTRL_TX BYTE_TO_TX RW 7008_0020h 10 2 Number of bytes to be transmitted Set the number of bytes to be automatically tr...

Page 516: ...7008_002Ch 0 Enable Disable DMARX request The DMARX request is generated as soon as an irq_rx event is generated This means the DMA can be used to move the received data received address is not inclu...

Page 517: ...ons ADDR_LUT1_A DDR_CW ADDR RW 7008_0044h 8 2 Sets the slave address at which the PMBus interface will respond ADDR_LUT1_A DDR_CW TYPE RW 7008_0044h 10 9 Transaction type Defines the type of transacti...

Page 518: ...saction type Defines the type of transaction associated with the defined slave address 0 PMBus transaction 1 I2 C 2 Reserved 3 Reserved ADDR_LUT4_A DDR_CW EN_ADDR RW 7008_0050h 1 0 Enable Disable this...

Page 519: ..._LUT6_A DDR_CW EN_ADDR RW 7008_0058h 1 0 Enable Disable this ADDR_LUT6 configuration word 0 ADDR configuration word is disabled 1 ADDR responds to write transactions only 2 ADDR responds to read trans...

Page 520: ...or the data to be transmitted over the PMBus interface 31 24 Byte 3 23 16 Byte 2 15 8 Byte 1 7 0 Byte 0 DATA_LUT1_D ATA_W DATA RW 7008_0084h 31 0 The 32 bit data word 1 in 8x32 bit or 8x4 byte scratch...

Page 521: ...The 32 bit data word 5 in 8x32 bit or 8x4 byte scratch table used in the prediction ACK NACK approach or as buffer for the data to be transmitted over the PMBus interface 31 24 Byte 3 23 16 Byte 2 15...

Page 522: ...corresponds to DATA_LUT0_DATA_W DATA 31 INDEX 224 corresponds to DATA_LUT7_DATA_W DATA 0 INDEX 255 corresponds to DATA_LUT7_DATA_W DATA 31 STATUS_WOR D 0 STATUS_WORD R 7008_0100h 15 0 Loop 0 STATUS_WO...

Page 523: ...ed SMBALERT generation STATUS_OTHE R 0 STATUS_OTHER RW 7008_0130h 7 0 Loop 0 STATUS_OTHER command data for HW based SMBALERT generation STATUS_OTHE R 1 STATUS_OTHER RW 7008_0134h 7 0 Loop 1 STATUS_OTH...

Page 524: ...0 status registers 0x0100 through 0x0160 on write STATUS_CLEA R_ALL 1 STATUS_CLEAR_AL L W 7008_016Ch 0 Clears all loop 1 status registers 0x0104 through 0x0164 on write STATUS_MASK _LP0 0 STATUS_VOUT_...

Page 525: ...S_MASK _LP0 6 STATUS_MFR_MAS K RW 7008_0188h 7 0 Loop 0 STATUS_MFR mask to enable disable bits for SMBALERT generation For each bit x 0 Bit x enabled for SMBALERT generation 1 Bit x enabled for SMBALE...

Page 526: ...S_CML_MAS K RW 7008_01A0h 7 0 Loop 1 STATUS_CML mask to enable disable bits for SMBALERT generation For each bit x 0 Bit x enabled for SMBALERT generation 1 Bit x enabled for SMBALERT generation STATU...

Page 527: ...lave transmit and slave receive The I2 C will automatically enter slave transmit mode if it receives its own slave address and a read bit It will similarly enter slave receive mode if it receives eith...

Page 528: ...e address Write bit received ACK transmitted 70h General Call address received ACK transmitted 78h Arbitration lost in address as master General Call address receved ACK transmitter 80h Data byte rece...

Page 529: ...IFLG will be set again The possible status register combinations are shown in Table 111 Table 111 Master transmit status after transmitting the 7 bit address Code MI2CV State Microprocessor Response...

Page 530: ...e Transmit START when bus free 68h Arbitration lost SLAX Write bit received ACK transmitted Clear IFLG AAK 0 Or clear IFLG AAK 1 Receive data byte transmit not ACK Receive data byte transmit ACK B0h A...

Page 531: ...C will receive a number of bytes from a slave transmitter After the START condition has been transmitted the IFLG bit will be set and status code 08h will be in the STAT register The DATA register sh...

Page 532: ...followed by the first part of the 10 bit address again plus the read bit after which the status code will be 40h or 48h It is the responsibility of the slave to remember that it was selected prior to...

Page 533: ...edge IFLG will be set and the STAT register will contain B8h Once the last byte to be transmitted has been loaded into the DATA register the AAK bit should be cleared when IFLG is cleared After the la...

Page 534: ...or 98h if slave receive mode was entered with the general call address When the IFLG bit has been cleared to 0 the MI2CV will return to idle state status code F8h 15 11 2 I2 C registers The relevant I...

Page 535: ...ter After each byte is transmitted the DATA register will contain the byte that was actually present on the bus so in the event of lost arbitration it will contain the received byte CNTR AAK RW 700B_0...

Page 536: ...et to 1 in master mode a STOP condition is transmitted on the I2 C bus If STP is set to 1 in slave mode the peripheral will behave as if a STOP condition has been received but no STOP condition will b...

Page 537: ...M controls the frequency at which the I2 C bus is sampled and the frequency of the clock line SCL when in master mode Fsamp Fclock 2N FSCL Fclock 2N M 1 10 where Fclock is the frequency of the I2 C pe...

Page 538: ...ta byte received after general call address received ACK transmitted 13h Data byte received after general call address received not ACK transmitted 14h STOP or repeated START condition received in sla...

Page 539: ...0 where Fclock is the frequency of the I2 C peripheral clock input XADDR SLAX RW 700B_0010h 7 0 Extended slave address bits 7 0 SLAX7 SLAX0 When ADDR SLA 4 0 11110b the I2 C peripheral recognizes this...

Page 540: ...ss Address Bits Description DATA VAL RW 7009_0000h 31 0 This register is used to feed the CRC module and to read the CRC result On write feed the CRC On read return the result of the CRC calculation I...

Page 541: ...ot reflected 1 CRC data output is reflected 15 13 UART The UART module is an Arm PrimeCell IP PL011 extensive documentation can be found in the Arm PrimeCell UART PL011 Technical Reference Manual The...

Page 542: ...re 123 shows a block diagram of the UART module Figure 123 UART block diagram 15 13 2 UART registers The relevant UART related registers and their descriptions are provided in Table 118 PRDATA 15 0 PW...

Page 543: ...s associated with the character at the top of the FIFO UARTDR BE R 700C_0000h 10 Break error This bit is set to 1 if a break condition was detected indicating that the received data input was held low...

Page 544: ...rity and stop bits This bit is cleared to 0 after a write to UARTECR In FIFO mode this error is associated with the character at the top of the FIFO When a break occurs only one 0 character is loaded...

Page 545: ...it is set when the receive holding register is empty If the FIFO is enabled the RXFE bit is set when the receive FIFO is empty UARTFR TXFF R 700C_0018h 5 Transmit FIFO full The meaning of this bit dep...

Page 546: ...ding down the UARTCLK signal according to the low power divisor value written to the UARTILPR register The low power divisor value is calculated as follows Low power divisor ILPDVSR FUARTCLK FIrLPBaud...

Page 547: ...k ticks UARTLCR_H BRK RW 700C_002Ch 0 Send break If this bit is set to 1 a low level is continually output on the UARTTXD output after completing transmission of the current character For the proper e...

Page 548: ...700C_002Ch 5 Word length These bits indicate the number of data bits transmitted or received in a frame as follows 0 5 bits 1 6 bits 2 7 bits 3 8 bits UARTLCR_H SPS RW 700C_002Ch 7 Stick parity selec...

Page 549: ...bits are transmitted with a pulse width that is three times the period of the IrLPBaud16 input signal regardless of the selected bit rate Setting this bit uses less power but might reduce transmissio...

Page 550: ...SIR signals depending on the setting of the SIREN bit When the UART is disabled in the middle of reception it completes the current character before stopping UARTCR DTR RW 700C_0030h 10 Data transmit...

Page 551: ...a is only transmitted when the nUARTCTS signal is asserted 0 CTS HW flow control is disabled 1 CTS HW flow control is enabled UARTIFLS TXIFLSEL RW 700C_0034h 2 0 Transmit interrupt FIFO level select T...

Page 552: ...e of 0 clears the mask UARTIMSC DSRMIM RW 700C_0038h 3 nUARTDSR modem interrupt mask A read returns the current mask for the UARTDSRINTR interrupt On a write of 1 the mask of the UARTDSRINTR interrupt...

Page 553: ...RTOEINTR interrupt is set A write of 0 clears the mask UARTRIS RIRMIS R 700C_003Ch 0 nUARTRI modem interrupt status Returns the raw interrupt state of the UARTRIINTR interrupt UARTRIS CTSRMIS R 700C_0...

Page 554: ...R interrupt UARTMIS DCDMMIS R 700C_0040h 2 nUARTDCD modem masked interrupt status Returns the masked interrupt state of the UARTDCDINTR interrupt UARTMIS DSRMMIS R 700C_0040h 3 nUARTDSR modem masked i...

Page 555: ...lear interrupt UARTICR DSRMIC W 700C_0044h 3 nUARTDSR modem interrupt clear 0 No effect 1 Clear interrupt UARTICR RXIC W 700C_0044h 4 Receive interrupt clear 0 No effect 1 Clear interrupt UARTICR TXIC...

Page 556: ...ipheral In this case the three digit product code 0x011 is returned UARTPeriphID 1 DESIGNER0 R 700C_0FE4h 7 4 DESIGNER 3 0 Together with the upper bits from DESIGNER1 DESIGNER 7 0 identifies the perip...

Page 557: ...to access the Cortex debug access point DAP Cortex DAP is a specific HW integrated into the M0 microcontroller that can take the control of the execution flow to allow an external debugger to access e...

Page 558: ...he host driving the line low when the clock is applied is interpreted by the target as idle cycle On the XDPP1100 due to IO limitations SWD pins are shared with other functionalities as alternate func...

Page 559: ...XADDR1 is connected to an external resistor so SWD IOs cannot be enabled by mistake The XADDR1 pin can used anyway for multi configuration purposes after the power up sequence The FW ensures proper c...

Page 560: ...erence manual Digital power controller Central processing unit subsystem Figure 126 XADDR1 timing diagram Additionally the SWD interface can be enabled any time after the power up by writing in the CP...

Page 561: ...of 562 V 1 0 2021 08 25 XDPP1100 technical reference manual Digital power controller Revision history Revision history Document version Date of release Description of changes V 1 0 2021 08 25 Initial...

Page 562: ...and standards concerning customer s products and any use of the product of Infineon Technologies in customer s applications The data contained in this document is exclusively intended for technically...

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